Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "New and updated SoC support.  Also included are some cleanups where
  the platform maintainers hadn't separated cleanups from new developent
  in separate branches.

  Some of the larger things worth pointing out:

   - A large set of changes from Alexandre Belloni and Nicolas Ferre
     preparing at91 platforms for multiplatform and cleaning up quite a
     bit in the process.

   - Removal of CSR's "Marco" SoC platform that never made it out to the
     market.  We love seeing these since it means the vendor published
     support before product was out, which is exactly what we want!

  New platforms this release are:

   - Conexant Digicolor (CX92755 SoC)
   - Hisilicon HiP01 SoC
   - CSR/sirf Atlas7 SoC
   - ST STiH418 SoC
   - Common code changes for Nvidia Tegra132 (64-bit SoC)

  We're seeing more and more platforms having a harder time labelling
  changes as cleanups vs new development -- which is a good sign that
  we've come quite far on the cleanup effort.  So over time we might
  start combining the cleanup and new-development branches more"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (124 commits)
  ARM: at91/trivial: unify functions and machine names
  ARM: at91: remove at91_dt_initialize and machine init_early()
  ARM: at91: change board files into SoC files
  ARM: at91: remove at91_boot_soc
  ARM: at91: move alternative initial mapping to board-dt-sama5.c
  ARM: at91: merge all SOC_AT91SAM9xxx
  ARM: at91: at91rm9200: set idle and restart from rm9200_dt_device_init()
  ARM: digicolor: select syscon and timer
  ARM: zynq: Simplify SLCR initialization
  ARM: zynq: PM: Fixed simple typo.
  ARM: zynq: Setup default gpio number for Xilinx Zynq
  ARM: digicolor: add low level debug support
  ARM: initial support for Conexant Digicolor CX92755 SoC
  ARM: OMAP2+: Add dm816x hwmod support
  ARM: OMAP2+: Add clock domain support for dm816x
  ARM: OMAP2+: Add board-generic.c entry for ti81xx
  ARM: at91: pm: remove warning to remove SOC_AT91SAM9263 usage
  ARM: at91: remove unused mach/system_rev.h
  ARM: at91: stop using HAVE_AT91_DBGUx
  ARM: at91: fix ordering of SRAM and PM initialization
  ...

7 files changed, 42 insertions, 132 deletions

diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
index 042f693ef423..a219dc310d5d 100644
--- a/arch/arm/mach-prima2/Kconfig
+++ b/arch/arm/mach-prima2/Kconfig
@@ -11,7 +11,7 @@ menuconfig ARCH_SIRF
 
 if ARCH_SIRF
 
-comment "CSR SiRF atlas6/primaII/Marco/Polo Specific Features"
+comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features"
 
 config ARCH_ATLAS6
         bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
@@ -20,6 +20,17 @@ config ARCH_ATLAS6
         help
           Support for CSR SiRFSoC ARM Cortex A9 Platform
 
+config ARCH_ATLAS7
+        bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform"
+        default y
+        select ARM_GIC
+        select CPU_V7
+        select HAVE_ARM_SCU if SMP
+        select HAVE_SMP
+        select SMP_ON_UP if SMP
+        help
+          Support for CSR SiRFSoC ARM Cortex A7 Platform
+
 config ARCH_PRIMA2
         bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
         default y
@@ -28,15 +39,6 @@ config ARCH_PRIMA2
         help
           Support for CSR SiRFSoC ARM Cortex A9 Platform
 
-config ARCH_MARCO
-        bool "CSR SiRFSoC MARCO ARM Cortex A9 Platform"
-        default y
-        select ARM_GIC
-        select HAVE_ARM_SCU if SMP
-        select SMP_ON_UP if SMP
-        help
-          Support for CSR SiRFSoC ARM Cortex A9 Platform
-
 config SIRF_IRQ
         bool
 
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index 8846e7d87ea5..d7d02b043449 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -1,7 +1,6 @@
 obj-y += rstc.o
 obj-y += common.o
 obj-y += rtciobrg.o
-obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_SUSPEND) += pm.o sleep.o
 obj-$(CONFIG_SMP) += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index a860ea27e8ae..0c819bb88418 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -20,12 +20,6 @@ static void __init sirfsoc_init_late(void)
         sirfsoc_pm_init();
 }
 
-static __init void sirfsoc_map_io(void)
-{
-        sirfsoc_map_lluart();
-        sirfsoc_map_scu();
-}
-
 #ifdef CONFIG_ARCH_ATLAS6
 static const char *atlas6_dt_match[] __initconst = {
         "sirf,atlas6",
@@ -36,7 +30,6 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
         /* Maintainer: Barry Song <baohua.song@csr.com> */
         .l2c_aux_val    = 0,
         .l2c_aux_mask   = ~0,
-        .map_io         = sirfsoc_map_io,
         .init_late      = sirfsoc_init_late,
         .dt_compat      = atlas6_dt_match,
 MACHINE_END
@@ -52,26 +45,21 @@ DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
         /* Maintainer: Barry Song <baohua.song@csr.com> */
         .l2c_aux_val    = 0,
         .l2c_aux_mask   = ~0,
-        .map_io         = sirfsoc_map_io,
         .dma_zone_size  = SZ_256M,
         .init_late      = sirfsoc_init_late,
         .dt_compat      = prima2_dt_match,
 MACHINE_END
 #endif
 
-#ifdef CONFIG_ARCH_MARCO
-static const char *marco_dt_match[] __initconst = {
-        "sirf,marco",
+#ifdef CONFIG_ARCH_ATLAS7
+static const char *atlas7_dt_match[] __initdata = {
+        "sirf,atlas7",
         NULL
 };
 
-DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
+DT_MACHINE_START(ATLAS7_DT, "Generic ATLAS7 (Flattened Device Tree)")
         /* Maintainer: Barry Song <baohua.song@csr.com> */
-        .l2c_aux_val    = 0,
-        .l2c_aux_mask   = ~0,
         .smp            = smp_ops(sirfsoc_smp_ops),
-        .map_io         = sirfsoc_map_io,
-        .init_late      = sirfsoc_init_late,
-        .dt_compat      = marco_dt_match,
+        .dt_compat      = atlas7_dt_match,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c
deleted file mode 100644
index 99c0c927ca4a..000000000000
--- a/arch/arm/mach-prima2/lluart.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Static memory mapping for DEBUG_LL
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <linux/kernel.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-#include "common.h"
-
-#if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1)
-#define SIRFSOC_UART1_PA_BASE          0xb0060000
-#elif defined(CONFIG_DEBUG_SIRFMARCO_UART1)
-#define SIRFSOC_UART1_PA_BASE          0xcc060000
-#else
-#define SIRFSOC_UART1_PA_BASE          0
-#endif
-
-#define SIRFSOC_UART1_VA_BASE          SIRFSOC_VA(0x060000)
-#define SIRFSOC_UART1_SIZE              SZ_4K
-
-void __init sirfsoc_map_lluart(void)
-{
-        struct map_desc sirfsoc_lluart_map = {
-                .virtual        = SIRFSOC_UART1_VA_BASE,
-                .pfn            = __phys_to_pfn(SIRFSOC_UART1_PA_BASE),
-                .length         = SIRFSOC_UART1_SIZE,
-                .type           = MT_DEVICE,
-        };
-
-        iotable_init(&sirfsoc_lluart_map, 1);
-}
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
index 335c12e92262..fc2b03c81e5f 100644
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -20,30 +20,10 @@
 
 #include "common.h"
 
-static void __iomem *scu_base;
-static void __iomem *rsc_base;
+static void __iomem *clk_base;
 
 static DEFINE_SPINLOCK(boot_lock);
 
-static struct map_desc scu_io_desc __initdata = {
-        .length         = SZ_4K,
-        .type           = MT_DEVICE,
-};
-
-void __init sirfsoc_map_scu(void)
-{
-        unsigned long base;
-
-        /* Get SCU base */
-        asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
-
-        scu_io_desc.virtual = SIRFSOC_VA(base);
-        scu_io_desc.pfn = __phys_to_pfn(base);
-        iotable_init(&scu_io_desc, 1);
-
-        scu_base = (void __iomem *)SIRFSOC_VA(base);
-}
-
 static void sirfsoc_secondary_init(unsigned int cpu)
 {
         /*
@@ -60,8 +40,8 @@ static void sirfsoc_secondary_init(unsigned int cpu)
         spin_unlock(&boot_lock);
 }
 
-static struct of_device_id rsc_ids[]  = {
-        { .compatible = "sirf,marco-rsc" },
+static struct of_device_id clk_ids[]  = {
+        { .compatible = "sirf,atlas7-clkc" },
         {},
 };
 
@@ -70,27 +50,27 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
         unsigned long timeout;
         struct device_node *np;
 
-        np = of_find_matching_node(NULL, rsc_ids);
+        np = of_find_matching_node(NULL, clk_ids);
         if (!np)
                 return -ENODEV;
 
-        rsc_base = of_iomap(np, 0);
-        if (!rsc_base)
+        clk_base = of_iomap(np, 0);
+        if (!clk_base)
                 return -ENOMEM;
 
         /*
-         * write the address of secondary startup into the sram register
-         * at offset 0x2C, then write the magic number 0x3CAF5D62 to the
-         * RSC register at offset 0x28, which is what boot rom code is
+         * write the address of secondary startup into the clkc register
+         * at offset 0x2bC, then write the magic number 0x3CAF5D62 to the
+         * clkc register at offset 0x2b8, which is what boot rom code is
          * waiting for. This would wake up the secondary core from WFE
          */
-#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2C
+#define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2bc
         __raw_writel(virt_to_phys(sirfsoc_secondary_startup),
-                rsc_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
+                clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
 
-#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x28
+#define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x2b8
         __raw_writel(0x3CAF5D62,
-                rsc_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
+                clk_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
 
         /* make sure write buffer is drained */
         mb();
@@ -132,13 +112,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle)
         return pen_release != -1 ? -ENOSYS : 0;
 }
 
-static void __init sirfsoc_smp_prepare_cpus(unsigned int max_cpus)
-{
-        scu_enable(scu_base);
-}
-
 struct smp_operations sirfsoc_smp_ops __initdata = {
-        .smp_prepare_cpus       = sirfsoc_smp_prepare_cpus,
         .smp_secondary_init     = sirfsoc_secondary_init,
         .smp_boot_secondary     = sirfsoc_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index e1f1f86f6a95..7c251eb11d01 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -34,36 +34,20 @@ static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
 
         mutex_lock(&rstc_lock);
 
-        if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) {
-                /*
-                 * Writing 1 to this bit resets corresponding block.
-                 * Writing 0 to this bit de-asserts reset signal of the
-                 * corresponding block. datasheet doesn't require explicit
-                 * delay between the set and clear of reset bit. it could
-                 * be shorter if tests pass.
-                 */
-                writel(readl(sirfsoc_rstc_base +
+        /*
+         * Writing 1 to this bit resets corresponding block.
+         * Writing 0 to this bit de-asserts reset signal of the
+         * corresponding block. datasheet doesn't require explicit
+         * delay between the set and clear of reset bit. it could
+         * be shorter if tests pass.
+         */
+        writel(readl(sirfsoc_rstc_base +
                         (reset_bit / 32) * 4) | (1 << reset_bit),
-                        sirfsoc_rstc_base + (reset_bit / 32) * 4);
-                msleep(20);
-                writel(readl(sirfsoc_rstc_base +
+                sirfsoc_rstc_base + (reset_bit / 32) * 4);
+        msleep(20);
+        writel(readl(sirfsoc_rstc_base +
                         (reset_bit / 32) * 4) & ~(1 << reset_bit),
-                        sirfsoc_rstc_base + (reset_bit / 32) * 4);
-        } else {
-                /*
-                 * For MARCO and POLO
-                 * Writing 1 to SET register resets corresponding block.
-                 * Writing 1 to CLEAR register de-asserts reset signal of the
-                 * corresponding block.
-                 * datasheet doesn't require explicit delay between the set and
-                 * clear of reset bit. it could be shorter if tests pass.
-                 */
-                writel(1 << reset_bit,
-                        sirfsoc_rstc_base + (reset_bit / 32) * 8);
-                msleep(20);
-                writel(1 << reset_bit,
-                        sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
-        }
+                sirfsoc_rstc_base + (reset_bit / 32) * 4);
 
         mutex_unlock(&rstc_lock);
 
@@ -106,7 +90,6 @@ static int sirfsoc_rstc_probe(struct platform_device *pdev)
 
 static const struct of_device_id rstc_ids[]  = {
         { .compatible = "sirf,prima2-rstc" },
-        { .compatible = "sirf,marco-rstc" },
         {},
 };
 
diff --git a/arch/arm/mach-prima2/rtciobrg.c b/arch/arm/mach-prima2/rtciobrg.c
index 70a0b475062b..8f66d8f7ca75 100644
--- a/arch/arm/mach-prima2/rtciobrg.c
+++ b/arch/arm/mach-prima2/rtciobrg.c
@@ -104,7 +104,6 @@ EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel);
 
 static const struct of_device_id rtciobrg_ids[] = {
         { .compatible = "sirf,prima2-rtciobg" },
-        { .compatible = "sirf,marco-rtciobg" },
         {}
 };