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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-02-25 17:10:38 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-02-25 17:10:38 -0500
commit9f33be2c3a80bdc2cc08342dd77fac87652e0548 (patch)
tree7ad6e825427a15c5ec0fc15540abc0429d7f4bce /arch/arm/mach-pnx4008
parent2741ecb4ce5c2d430b5c44b0a169038338c21df5 (diff)
parenteed18b5fa4d297c681b00144e8c6942dd35d39a7 (diff)
Merge branches 'clks' and 'pnx' into devel
Diffstat (limited to 'arch/arm/mach-pnx4008')
-rw-r--r--arch/arm/mach-pnx4008/clock.c173
-rw-r--r--arch/arm/mach-pnx4008/clock.h6
-rw-r--r--arch/arm/mach-pnx4008/i2c.c108
-rw-r--r--arch/arm/mach-pnx4008/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-pnx4008/include/mach/timex.h54
-rw-r--r--arch/arm/mach-pnx4008/pm.c2
-rw-r--r--arch/arm/mach-pnx4008/time.c2
-rw-r--r--arch/arm/mach-pnx4008/time.h70
8 files changed, 181 insertions, 241 deletions
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c
index 898c0e88acbc..9d1975fa4d9f 100644
--- a/arch/arm/mach-pnx4008/clock.c
+++ b/arch/arm/mach-pnx4008/clock.c
@@ -22,8 +22,9 @@
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/io.h> 23#include <linux/io.h>
24 24
25#include <mach/hardware.h> 25#include <asm/clkdev.h>
26 26
27#include <mach/hardware.h>
27#include <mach/clock.h> 28#include <mach/clock.h>
28#include "clock.h" 29#include "clock.h"
29 30
@@ -56,18 +57,19 @@ static void propagate_rate(struct clk *clk)
56 } 57 }
57} 58}
58 59
59static inline void clk_reg_disable(struct clk *clk) 60static void clk_reg_disable(struct clk *clk)
60{ 61{
61 if (clk->enable_reg) 62 if (clk->enable_reg)
62 __raw_writel(__raw_readl(clk->enable_reg) & 63 __raw_writel(__raw_readl(clk->enable_reg) &
63 ~(1 << clk->enable_shift), clk->enable_reg); 64 ~(1 << clk->enable_shift), clk->enable_reg);
64} 65}
65 66
66static inline void clk_reg_enable(struct clk *clk) 67static int clk_reg_enable(struct clk *clk)
67{ 68{
68 if (clk->enable_reg) 69 if (clk->enable_reg)
69 __raw_writel(__raw_readl(clk->enable_reg) | 70 __raw_writel(__raw_readl(clk->enable_reg) |
70 (1 << clk->enable_shift), clk->enable_reg); 71 (1 << clk->enable_shift), clk->enable_reg);
72 return 0;
71} 73}
72 74
73static inline void clk_reg_disable1(struct clk *clk) 75static inline void clk_reg_disable1(struct clk *clk)
@@ -636,31 +638,34 @@ static struct clk flash_ck = {
636static struct clk i2c0_ck = { 638static struct clk i2c0_ck = {
637 .name = "i2c0_ck", 639 .name = "i2c0_ck",
638 .parent = &per_ck, 640 .parent = &per_ck,
639 .flags = NEEDS_INITIALIZATION, 641 .flags = NEEDS_INITIALIZATION | FIXED_RATE,
640 .round_rate = &on_off_round_rate,
641 .set_rate = &on_off_set_rate,
642 .enable_shift = 0, 642 .enable_shift = 0,
643 .enable_reg = I2CCLKCTRL_REG, 643 .enable_reg = I2CCLKCTRL_REG,
644 .rate = 13000000,
645 .enable = clk_reg_enable,
646 .disable = clk_reg_disable,
644}; 647};
645 648
646static struct clk i2c1_ck = { 649static struct clk i2c1_ck = {
647 .name = "i2c1_ck", 650 .name = "i2c1_ck",
648 .parent = &per_ck, 651 .parent = &per_ck,
649 .flags = NEEDS_INITIALIZATION, 652 .flags = NEEDS_INITIALIZATION | FIXED_RATE,
650 .round_rate = &on_off_round_rate,
651 .set_rate = &on_off_set_rate,
652 .enable_shift = 1, 653 .enable_shift = 1,
653 .enable_reg = I2CCLKCTRL_REG, 654 .enable_reg = I2CCLKCTRL_REG,
655 .rate = 13000000,
656 .enable = clk_reg_enable,
657 .disable = clk_reg_disable,
654}; 658};
655 659
656static struct clk i2c2_ck = { 660static struct clk i2c2_ck = {
657 .name = "i2c2_ck", 661 .name = "i2c2_ck",
658 .parent = &per_ck, 662 .parent = &per_ck,
659 .flags = NEEDS_INITIALIZATION, 663 .flags = NEEDS_INITIALIZATION | FIXED_RATE,
660 .round_rate = &on_off_round_rate,
661 .set_rate = &on_off_set_rate,
662 .enable_shift = 2, 664 .enable_shift = 2,
663 .enable_reg = USB_OTG_CLKCTRL_REG, 665 .enable_reg = USB_OTG_CLKCTRL_REG,
666 .rate = 13000000,
667 .enable = clk_reg_enable,
668 .disable = clk_reg_disable,
664}; 669};
665 670
666static struct clk spi0_ck = { 671static struct clk spi0_ck = {
@@ -738,16 +743,16 @@ static struct clk wdt_ck = {
738 .name = "wdt_ck", 743 .name = "wdt_ck",
739 .parent = &per_ck, 744 .parent = &per_ck,
740 .flags = NEEDS_INITIALIZATION, 745 .flags = NEEDS_INITIALIZATION,
741 .round_rate = &on_off_round_rate,
742 .set_rate = &on_off_set_rate,
743 .enable_shift = 0, 746 .enable_shift = 0,
744 .enable_reg = TIMCLKCTRL_REG, 747 .enable_reg = TIMCLKCTRL_REG,
748 .enable = clk_reg_enable,
749 .disable = clk_reg_disable,
745}; 750};
746 751
747/* These clocks are visible outside this module 752/* These clocks are visible outside this module
748 * and can be initialized 753 * and can be initialized
749 */ 754 */
750static struct clk *onchip_clks[] = { 755static struct clk *onchip_clks[] __initdata = {
751 &ck_13MHz, 756 &ck_13MHz,
752 &ck_pll1, 757 &ck_pll1,
753 &ck_pll4, 758 &ck_pll4,
@@ -777,49 +782,74 @@ static struct clk *onchip_clks[] = {
777 &wdt_ck, 782 &wdt_ck,
778}; 783};
779 784
780static int local_clk_enable(struct clk *clk) 785static struct clk_lookup onchip_clkreg[] = {
781{ 786 { .clk = &ck_13MHz, .con_id = "ck_13MHz" },
782 int ret = 0; 787 { .clk = &ck_pll1, .con_id = "ck_pll1" },
783 788 { .clk = &ck_pll4, .con_id = "ck_pll4" },
784 if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate 789 { .clk = &ck_pll5, .con_id = "ck_pll5" },
785 && clk->user_rate) 790 { .clk = &ck_pll3, .con_id = "ck_pll3" },
786 ret = clk->set_rate(clk, clk->user_rate); 791 { .clk = &vfp9_ck, .con_id = "vfp9_ck" },
787 return ret; 792 { .clk = &m2hclk_ck, .con_id = "m2hclk_ck" },
788} 793 { .clk = &hclk_ck, .con_id = "hclk_ck" },
794 { .clk = &dma_ck, .con_id = "dma_ck" },
795 { .clk = &flash_ck, .con_id = "flash_ck" },
796 { .clk = &dum_ck, .con_id = "dum_ck" },
797 { .clk = &keyscan_ck, .con_id = "keyscan_ck" },
798 { .clk = &pwm1_ck, .con_id = "pwm1_ck" },
799 { .clk = &pwm2_ck, .con_id = "pwm2_ck" },
800 { .clk = &jpeg_ck, .con_id = "jpeg_ck" },
801 { .clk = &ms_ck, .con_id = "ms_ck" },
802 { .clk = &touch_ck, .con_id = "touch_ck" },
803 { .clk = &i2c0_ck, .dev_id = "pnx-i2c.0" },
804 { .clk = &i2c1_ck, .dev_id = "pnx-i2c.1" },
805 { .clk = &i2c2_ck, .dev_id = "pnx-i2c.2" },
806 { .clk = &spi0_ck, .con_id = "spi0_ck" },
807 { .clk = &spi1_ck, .con_id = "spi1_ck" },
808 { .clk = &uart3_ck, .con_id = "uart3_ck" },
809 { .clk = &uart4_ck, .con_id = "uart4_ck" },
810 { .clk = &uart5_ck, .con_id = "uart5_ck" },
811 { .clk = &uart6_ck, .con_id = "uart6_ck" },
812 { .clk = &wdt_ck, .dev_id = "pnx4008-watchdog" },
813};
789 814
790static void local_clk_disable(struct clk *clk) 815static void local_clk_disable(struct clk *clk)
791{ 816{
792 if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate) 817 if (WARN_ON(clk->usecount == 0))
793 clk->set_rate(clk, 0); 818 return;
794}
795 819
796static void local_clk_unuse(struct clk *clk) 820 if (!(--clk->usecount)) {
797{ 821 if (clk->disable)
798 if (clk->usecount > 0 && !(--clk->usecount)) { 822 clk->disable(clk);
799 local_clk_disable(clk); 823 else if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
824 clk->set_rate(clk, 0);
800 if (clk->parent) 825 if (clk->parent)
801 local_clk_unuse(clk->parent); 826 local_clk_disable(clk->parent);
802 } 827 }
803} 828}
804 829
805static int local_clk_use(struct clk *clk) 830static int local_clk_enable(struct clk *clk)
806{ 831{
807 int ret = 0; 832 int ret = 0;
808 if (clk->usecount++ == 0) {
809 if (clk->parent)
810 ret = local_clk_use(clk->parent);
811 833
812 if (ret != 0) { 834 if (clk->usecount == 0) {
813 clk->usecount--; 835 if (clk->parent) {
814 goto out; 836 ret = local_clk_enable(clk->parent);
837 if (ret != 0)
838 goto out;
815 } 839 }
816 840
817 ret = local_clk_enable(clk); 841 if (clk->enable)
842 ret = clk->enable(clk);
843 else if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
844 && clk->user_rate)
845 ret = clk->set_rate(clk, clk->user_rate);
818 846
819 if (ret != 0 && clk->parent) { 847 if (ret != 0 && clk->parent) {
820 local_clk_unuse(clk->parent); 848 local_clk_disable(clk->parent);
821 clk->usecount--; 849 goto out;
822 } 850 }
851
852 clk->usecount++;
823 } 853 }
824out: 854out:
825 return ret; 855 return ret;
@@ -866,35 +896,6 @@ out:
866 896
867EXPORT_SYMBOL(clk_set_rate); 897EXPORT_SYMBOL(clk_set_rate);
868 898
869struct clk *clk_get(struct device *dev, const char *id)
870{
871 struct clk *clk = ERR_PTR(-ENOENT);
872 struct clk **clkp;
873
874 clock_lock();
875 for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
876 clkp++) {
877 if (strcmp(id, (*clkp)->name) == 0
878 && try_module_get((*clkp)->owner)) {
879 clk = (*clkp);
880 break;
881 }
882 }
883 clock_unlock();
884
885 return clk;
886}
887EXPORT_SYMBOL(clk_get);
888
889void clk_put(struct clk *clk)
890{
891 clock_lock();
892 if (clk && !IS_ERR(clk))
893 module_put(clk->owner);
894 clock_unlock();
895}
896EXPORT_SYMBOL(clk_put);
897
898unsigned long clk_get_rate(struct clk *clk) 899unsigned long clk_get_rate(struct clk *clk)
899{ 900{
900 unsigned long ret; 901 unsigned long ret;
@@ -907,10 +908,10 @@ EXPORT_SYMBOL(clk_get_rate);
907 908
908int clk_enable(struct clk *clk) 909int clk_enable(struct clk *clk)
909{ 910{
910 int ret = 0; 911 int ret;
911 912
912 clock_lock(); 913 clock_lock();
913 ret = local_clk_use(clk); 914 ret = local_clk_enable(clk);
914 clock_unlock(); 915 clock_unlock();
915 return ret; 916 return ret;
916} 917}
@@ -920,7 +921,7 @@ EXPORT_SYMBOL(clk_enable);
920void clk_disable(struct clk *clk) 921void clk_disable(struct clk *clk)
921{ 922{
922 clock_lock(); 923 clock_lock();
923 local_clk_unuse(clk); 924 local_clk_disable(clk);
924 clock_unlock(); 925 clock_unlock();
925} 926}
926 927
@@ -967,18 +968,24 @@ static int __init clk_init(void)
967 968
968 for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks); 969 for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
969 clkp++) { 970 clkp++) {
970 if (((*clkp)->flags & NEEDS_INITIALIZATION) 971 struct clk *clk = *clkp;
971 && ((*clkp)->set_rate)) { 972 if (clk->flags & NEEDS_INITIALIZATION) {
972 (*clkp)->user_rate = (*clkp)->rate; 973 if (clk->set_rate) {
973 local_set_rate((*clkp), (*clkp)->user_rate); 974 clk->user_rate = clk->rate;
974 if ((*clkp)->set_parent) 975 local_set_rate(clk, clk->user_rate);
975 (*clkp)->set_parent((*clkp), (*clkp)->parent); 976 if (clk->set_parent)
977 clk->set_parent(clk, clk->parent);
978 }
979 if (clk->enable && clk->usecount)
980 clk->enable(clk);
981 if (clk->disable && !clk->usecount)
982 clk->disable(clk);
976 } 983 }
977 pr_debug("%s: clock %s, rate %ld\n", 984 pr_debug("%s: clock %s, rate %ld\n",
978 __func__, (*clkp)->name, (*clkp)->rate); 985 __func__, clk->name, clk->rate);
979 } 986 }
980 987
981 local_clk_use(&ck_pll4); 988 local_clk_enable(&ck_pll4);
982 989
983 /* if ck_13MHz is not used, disable it. */ 990 /* if ck_13MHz is not used, disable it. */
984 if (ck_13MHz.usecount == 0) 991 if (ck_13MHz.usecount == 0)
@@ -987,6 +994,8 @@ static int __init clk_init(void)
987 /* Disable autoclocking */ 994 /* Disable autoclocking */
988 __raw_writeb(0xff, AUTOCLK_CTRL); 995 __raw_writeb(0xff, AUTOCLK_CTRL);
989 996
997 clkdev_add_table(onchip_clkreg, ARRAY_SIZE(onchip_clkreg));
998
990 return 0; 999 return 0;
991} 1000}
992 1001
diff --git a/arch/arm/mach-pnx4008/clock.h b/arch/arm/mach-pnx4008/clock.h
index cd58f372cfd0..39720d6c0d01 100644
--- a/arch/arm/mach-pnx4008/clock.h
+++ b/arch/arm/mach-pnx4008/clock.h
@@ -14,8 +14,6 @@
14#define __ARCH_ARM_PNX4008_CLOCK_H__ 14#define __ARCH_ARM_PNX4008_CLOCK_H__
15 15
16struct clk { 16struct clk {
17 struct list_head node;
18 struct module *owner;
19 const char *name; 17 const char *name;
20 struct clk *parent; 18 struct clk *parent;
21 struct clk *propagate_next; 19 struct clk *propagate_next;
@@ -29,9 +27,11 @@ struct clk {
29 u8 enable_shift1; 27 u8 enable_shift1;
30 u32 enable_reg1; 28 u32 enable_reg1;
31 u32 parent_switch_reg; 29 u32 parent_switch_reg;
32 u32(*round_rate) (struct clk *, u32); 30 u32(*round_rate) (struct clk *, u32);
33 int (*set_rate) (struct clk *, u32); 31 int (*set_rate) (struct clk *, u32);
34 int (*set_parent) (struct clk * clk, struct clk * parent); 32 int (*set_parent) (struct clk * clk, struct clk * parent);
33 int (*enable)(struct clk *);
34 void (*disable)(struct clk *);
35}; 35};
36 36
37/* Flags */ 37/* Flags */
diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c
index f3fea29c00d3..8103f9644e2d 100644
--- a/arch/arm/mach-pnx4008/i2c.c
+++ b/arch/arm/mach-pnx4008/i2c.c
@@ -18,120 +18,24 @@
18#include <mach/irqs.h> 18#include <mach/irqs.h>
19#include <mach/i2c.h> 19#include <mach/i2c.h>
20 20
21static int set_clock_run(struct platform_device *pdev) 21static struct i2c_pnx_data i2c0_data = {
22{ 22 .name = I2C_CHIP_NAME "0",
23 struct clk *clk;
24 char name[10];
25 int retval = 0;
26
27 snprintf(name, 10, "i2c%d_ck", pdev->id);
28 clk = clk_get(&pdev->dev, name);
29 if (!IS_ERR(clk)) {
30 clk_set_rate(clk, 1);
31 clk_put(clk);
32 } else
33 retval = -ENOENT;
34
35 return retval;
36}
37
38static int set_clock_stop(struct platform_device *pdev)
39{
40 struct clk *clk;
41 char name[10];
42 int retval = 0;
43
44 snprintf(name, 10, "i2c%d_ck", pdev->id);
45 clk = clk_get(&pdev->dev, name);
46 if (!IS_ERR(clk)) {
47 clk_set_rate(clk, 0);
48 clk_put(clk);
49 } else
50 retval = -ENOENT;
51
52 return retval;
53}
54
55static int i2c_pnx_suspend(struct platform_device *pdev, pm_message_t state)
56{
57 int retval = 0;
58#ifdef CONFIG_PM
59 retval = set_clock_run(pdev);
60#endif
61 return retval;
62}
63
64static int i2c_pnx_resume(struct platform_device *pdev)
65{
66 int retval = 0;
67#ifdef CONFIG_PM
68 retval = set_clock_run(pdev);
69#endif
70 return retval;
71}
72
73static u32 calculate_input_freq(struct platform_device *pdev)
74{
75 return HCLK_MHZ;
76}
77
78
79static struct i2c_pnx_algo_data pnx_algo_data0 = {
80 .base = PNX4008_I2C1_BASE, 23 .base = PNX4008_I2C1_BASE,
81 .irq = I2C_1_INT, 24 .irq = I2C_1_INT,
82}; 25};
83 26
84static struct i2c_pnx_algo_data pnx_algo_data1 = { 27static struct i2c_pnx_data i2c1_data = {
28 .name = I2C_CHIP_NAME "1",
85 .base = PNX4008_I2C2_BASE, 29 .base = PNX4008_I2C2_BASE,
86 .irq = I2C_2_INT, 30 .irq = I2C_2_INT,
87}; 31};
88 32
89static struct i2c_pnx_algo_data pnx_algo_data2 = { 33static struct i2c_pnx_data i2c2_data = {
34 .name = "USB-I2C",
90 .base = (PNX4008_USB_CONFIG_BASE + 0x300), 35 .base = (PNX4008_USB_CONFIG_BASE + 0x300),
91 .irq = USB_I2C_INT, 36 .irq = USB_I2C_INT,
92}; 37};
93 38
94static struct i2c_adapter pnx_adapter0 = {
95 .name = I2C_CHIP_NAME "0",
96 .algo_data = &pnx_algo_data0,
97};
98static struct i2c_adapter pnx_adapter1 = {
99 .name = I2C_CHIP_NAME "1",
100 .algo_data = &pnx_algo_data1,
101};
102
103static struct i2c_adapter pnx_adapter2 = {
104 .name = "USB-I2C",
105 .algo_data = &pnx_algo_data2,
106};
107
108static struct i2c_pnx_data i2c0_data = {
109 .suspend = i2c_pnx_suspend,
110 .resume = i2c_pnx_resume,
111 .calculate_input_freq = calculate_input_freq,
112 .set_clock_run = set_clock_run,
113 .set_clock_stop = set_clock_stop,
114 .adapter = &pnx_adapter0,
115};
116
117static struct i2c_pnx_data i2c1_data = {
118 .suspend = i2c_pnx_suspend,
119 .resume = i2c_pnx_resume,
120 .calculate_input_freq = calculate_input_freq,
121 .set_clock_run = set_clock_run,
122 .set_clock_stop = set_clock_stop,
123 .adapter = &pnx_adapter1,
124};
125
126static struct i2c_pnx_data i2c2_data = {
127 .suspend = i2c_pnx_suspend,
128 .resume = i2c_pnx_resume,
129 .calculate_input_freq = calculate_input_freq,
130 .set_clock_run = set_clock_run,
131 .set_clock_stop = set_clock_stop,
132 .adapter = &pnx_adapter2,
133};
134
135static struct platform_device i2c0_device = { 39static struct platform_device i2c0_device = {
136 .name = "pnx-i2c", 40 .name = "pnx-i2c",
137 .id = 0, 41 .id = 0,
diff --git a/arch/arm/mach-pnx4008/include/mach/clkdev.h b/arch/arm/mach-pnx4008/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do { } while (0)
6
7#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/timex.h b/arch/arm/mach-pnx4008/include/mach/timex.h
index 5ff0196c0f16..b383c7de7ab4 100644
--- a/arch/arm/mach-pnx4008/include/mach/timex.h
+++ b/arch/arm/mach-pnx4008/include/mach/timex.h
@@ -14,60 +14,6 @@
14#ifndef __PNX4008_TIMEX_H 14#ifndef __PNX4008_TIMEX_H
15#define __PNX4008_TIMEX_H 15#define __PNX4008_TIMEX_H
16 16
17#include <linux/io.h>
18#include <mach/hardware.h>
19
20#define CLOCK_TICK_RATE 1000000 17#define CLOCK_TICK_RATE 1000000
21 18
22#define TICKS2USECS(x) (x)
23
24/* MilliSecond Timer - Chapter 21 Page 202 */
25
26#define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
27#define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
28#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
29#define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
30#define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
31#define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
32
33/* High Speed Timer - Chpater 22, Page 205 */
34
35#define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
36#define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
37#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
38#define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
39#define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
40#define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
41#define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
42#define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
43#define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
44#define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
45#define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
46#define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
47
48/* IMPORTANT: both timers are UPCOUNTING */
49
50/* xSTIM_MCTRL bit definitions */
51#define MR0_INT 1
52#define RESET_COUNT0 (1<<1)
53#define STOP_COUNT0 (1<<2)
54#define MR1_INT (1<<3)
55#define RESET_COUNT1 (1<<4)
56#define STOP_COUNT1 (1<<5)
57#define MR2_INT (1<<6)
58#define RESET_COUNT2 (1<<7)
59#define STOP_COUNT2 (1<<8)
60
61/* xSTIM_CTRL bit definitions */
62#define COUNT_ENAB 1
63#define RESET_COUNT (1<<1)
64#define DEBUG_EN (1<<2)
65
66/* xSTIM_INT bit definitions */
67#define MATCH0_INT 1
68#define MATCH1_INT (1<<1)
69#define MATCH2_INT (1<<2)
70#define RTC_TICK0 (1<<4)
71#define RTC_TICK1 (1<<5)
72
73#endif 19#endif
diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c
index b3d8d53e32ef..1f0585329be4 100644
--- a/arch/arm/mach-pnx4008/pm.c
+++ b/arch/arm/mach-pnx4008/pm.c
@@ -21,6 +21,8 @@
21#include <linux/io.h> 21#include <linux/io.h>
22 22
23#include <asm/cacheflush.h> 23#include <asm/cacheflush.h>
24
25#include <mach/hardware.h>
24#include <mach/pm.h> 26#include <mach/pm.h>
25#include <mach/clock.h> 27#include <mach/clock.h>
26 28
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
index fc0ba183fe12..0c8aad4bb0dc 100644
--- a/arch/arm/mach-pnx4008/time.c
+++ b/arch/arm/mach-pnx4008/time.c
@@ -30,6 +30,8 @@
30#include <asm/mach/time.h> 30#include <asm/mach/time.h>
31#include <asm/errno.h> 31#include <asm/errno.h>
32 32
33#include "time.h"
34
33/*! Note: all timers are UPCOUNTING */ 35/*! Note: all timers are UPCOUNTING */
34 36
35/*! 37/*!
diff --git a/arch/arm/mach-pnx4008/time.h b/arch/arm/mach-pnx4008/time.h
new file mode 100644
index 000000000000..75e88c570aa7
--- /dev/null
+++ b/arch/arm/mach-pnx4008/time.h
@@ -0,0 +1,70 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/timex.h
3 *
4 * PNX4008 timers header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#ifndef PNX_TIME_H
14#define PNX_TIME_H
15
16#include <linux/io.h>
17#include <mach/hardware.h>
18
19#define TICKS2USECS(x) (x)
20
21/* MilliSecond Timer - Chapter 21 Page 202 */
22
23#define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
24#define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
25#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
26#define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
27#define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
28#define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
29
30/* High Speed Timer - Chpater 22, Page 205 */
31
32#define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
33#define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
34#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
35#define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
36#define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
37#define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
38#define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
39#define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
40#define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
41#define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
42#define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
43#define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
44
45/* IMPORTANT: both timers are UPCOUNTING */
46
47/* xSTIM_MCTRL bit definitions */
48#define MR0_INT 1
49#define RESET_COUNT0 (1<<1)
50#define STOP_COUNT0 (1<<2)
51#define MR1_INT (1<<3)
52#define RESET_COUNT1 (1<<4)
53#define STOP_COUNT1 (1<<5)
54#define MR2_INT (1<<6)
55#define RESET_COUNT2 (1<<7)
56#define STOP_COUNT2 (1<<8)
57
58/* xSTIM_CTRL bit definitions */
59#define COUNT_ENAB 1
60#define RESET_COUNT (1<<1)
61#define DEBUG_EN (1<<2)
62
63/* xSTIM_INT bit definitions */
64#define MATCH0_INT 1
65#define MATCH1_INT (1<<1)
66#define MATCH2_INT (1<<2)
67#define RTC_TICK0 (1<<4)
68#define RTC_TICK1 (1<<5)
69
70#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 13:20:59 -0400