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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-11-23 06:41:32 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-11-30 07:24:47 -0500
commit10dd5ce28d78e2440e8fa1135d17e33399d75340 (patch)
treed2e76765a57e7e47a9c424f99c3a22bf99c6da64 /arch/arm/mach-pnx4008
parent127e477e0cd8da4d3058709ab2dc7b92dccbcba5 (diff)
[ARM] Remove compatibility layer for ARM irqs
set_irq_chipdata -> set_irq_chip_data get_irq_chipdata -> get_irq_chip_data do_level_IRQ -> handle_level_irq do_edge_IRQ -> handle_edge_irq do_simple_IRQ -> handle_simple_irq irqdesc -> irq_desc irqchip -> irq_chip Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-pnx4008')
-rw-r--r--arch/arm/mach-pnx4008/irq.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index 3a4bcf3d91fa..968d0b027597 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -59,22 +59,22 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
59 case IRQT_RISING: 59 case IRQT_RISING:
60 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ 60 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
61 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */ 61 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */
62 set_irq_handler(irq, do_edge_IRQ); 62 set_irq_handler(irq, handle_edge_irq);
63 break; 63 break;
64 case IRQT_FALLING: 64 case IRQT_FALLING:
65 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */ 65 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
66 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */ 66 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */
67 set_irq_handler(irq, do_edge_IRQ); 67 set_irq_handler(irq, handle_edge_irq);
68 break; 68 break;
69 case IRQT_LOW: 69 case IRQT_LOW:
70 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ 70 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
71 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */ 71 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */
72 set_irq_handler(irq, do_level_IRQ); 72 set_irq_handler(irq, handle_level_irq);
73 break; 73 break;
74 case IRQT_HIGH: 74 case IRQT_HIGH:
75 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */ 75 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
76 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */ 76 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */
77 set_irq_handler(irq, do_level_IRQ); 77 set_irq_handler(irq, handle_level_irq);
78 break; 78 break;
79 79
80 /* IRQT_BOTHEDGE is not supported */ 80 /* IRQT_BOTHEDGE is not supported */
@@ -85,7 +85,7 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
85 return 0; 85 return 0;
86} 86}
87 87
88static struct irqchip pnx4008_irq_chip = { 88static struct irq_chip pnx4008_irq_chip = {
89 .ack = pnx4008_mask_ack_irq, 89 .ack = pnx4008_mask_ack_irq,
90 .mask = pnx4008_mask_irq, 90 .mask = pnx4008_mask_irq,
91 .unmask = pnx4008_unmask_irq, 91 .unmask = pnx4008_unmask_irq,