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authorTony Lindgren <tony@atomide.com>2009-10-19 18:25:26 -0400
committerTony Lindgren <tony@atomide.com>2009-10-19 18:25:26 -0400
commite4e7a13af2007edf215ad1164fc8d94c366cb72c (patch)
treebbdfe804dd03cfd9f73e7069abf6b913ffa95669 /arch/arm/mach-omap2
parentf059429ea055c71648ae81c581eaa91d3761942b (diff)
omap: Use ioremap for omap4 L4 code
Use ioremap for omap4 L4 code Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c13
-rw-r--r--arch/arm/mach-omap2/omap-smp.c29
-rw-r--r--arch/arm/mach-omap2/timer-gp.c3
3 files changed, 34 insertions, 11 deletions
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index eb37c40ea83a..1035b22441ba 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -52,8 +52,17 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
52 52
53static void __init gic_init_irq(void) 53static void __init gic_init_irq(void)
54{ 54{
55 gic_dist_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29); 55 void __iomem *base;
56 gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)); 56
57 /* Static mapping, never released */
58 base = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
59 BUG_ON(!base);
60 gic_dist_init(0, base, 29);
61
62 /* Static mapping, never released */
63 gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
64 BUG_ON(!gic_cpu_base_addr);
65 gic_cpu_init(0, gic_cpu_base_addr);
57} 66}
58 67
59static void __init omap_4430sdp_init_irq(void) 68static void __init omap_4430sdp_init_irq(void)
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 48ee295db275..8813ac25c5ed 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -24,13 +24,14 @@
24#include <asm/localtimer.h> 24#include <asm/localtimer.h>
25#include <asm/smp_scu.h> 25#include <asm/smp_scu.h>
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/common.h>
27 28
28/* Registers used for communicating startup information */ 29/* Registers used for communicating startup information */
29#define OMAP4_AUXCOREBOOT_REG0 (OMAP44XX_VA_WKUPGEN_BASE + 0x800) 30static void __iomem *omap4_auxcoreboot_reg0;
30#define OMAP4_AUXCOREBOOT_REG1 (OMAP44XX_VA_WKUPGEN_BASE + 0x804) 31static void __iomem *omap4_auxcoreboot_reg1;
31 32
32/* SCU base address */ 33/* SCU base address */
33static void __iomem *scu_base = OMAP44XX_VA_SCU_BASE; 34static void __iomem *scu_base;
34 35
35/* 36/*
36 * Use SCU config register to count number of cores 37 * Use SCU config register to count number of cores
@@ -53,8 +54,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
53 * core (e.g. timer irq), then they will not have been enabled 54 * core (e.g. timer irq), then they will not have been enabled
54 * for us: do so 55 * for us: do so
55 */ 56 */
56 57 gic_cpu_init(0, gic_cpu_base_addr);
57 gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
58 58
59 /* 59 /*
60 * Synchronise with the boot thread. 60 * Synchronise with the boot thread.
@@ -79,7 +79,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
79 * the AuxCoreBoot1 register is updated with cpu state 79 * the AuxCoreBoot1 register is updated with cpu state
80 * A barrier is added to ensure that write buffer is drained 80 * A barrier is added to ensure that write buffer is drained
81 */ 81 */
82 __raw_writel(cpu, OMAP4_AUXCOREBOOT_REG1); 82 __raw_writel(cpu, omap4_auxcoreboot_reg1);
83 smp_wmb(); 83 smp_wmb();
84 84
85 timeout = jiffies + (1 * HZ); 85 timeout = jiffies + (1 * HZ);
@@ -104,7 +104,7 @@ static void __init wakeup_secondary(void)
104 * A barrier is added to ensure that write buffer is drained 104 * A barrier is added to ensure that write buffer is drained
105 */ 105 */
106 __raw_writel(virt_to_phys(omap_secondary_startup), \ 106 __raw_writel(virt_to_phys(omap_secondary_startup), \
107 OMAP4_AUXCOREBOOT_REG0); 107 omap4_auxcoreboot_reg0);
108 smp_wmb(); 108 smp_wmb();
109 109
110 /* 110 /*
@@ -120,7 +120,13 @@ static void __init wakeup_secondary(void)
120 */ 120 */
121void __init smp_init_cpus(void) 121void __init smp_init_cpus(void)
122{ 122{
123 unsigned int i, ncores = get_core_count(); 123 unsigned int i, ncores;
124
125 /* Never released */
126 scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
127 BUG_ON(!scu_base);
128
129 ncores = get_core_count();
124 130
125 for (i = 0; i < ncores; i++) 131 for (i = 0; i < ncores; i++)
126 set_cpu_possible(i, true); 132 set_cpu_possible(i, true);
@@ -130,6 +136,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
130{ 136{
131 unsigned int ncores = get_core_count(); 137 unsigned int ncores = get_core_count();
132 unsigned int cpu = smp_processor_id(); 138 unsigned int cpu = smp_processor_id();
139 void __iomem *omap4_wkupgen_base;
133 int i; 140 int i;
134 141
135 /* sanity check */ 142 /* sanity check */
@@ -161,6 +168,12 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
161 for (i = 0; i < max_cpus; i++) 168 for (i = 0; i < max_cpus; i++)
162 set_cpu_present(i, true); 169 set_cpu_present(i, true);
163 170
171 /* Never released */
172 omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
173 BUG_ON(!omap4_wkupgen_base);
174 omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800;
175 omap4_auxcoreboot_reg1 = omap4_wkupgen_base + 0x804;
176
164 if (max_cpus > 1) { 177 if (max_cpus > 1) {
165 /* 178 /*
166 * Enable the local timer or broadcast device for the 179 * Enable the local timer or broadcast device for the
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index e2338c0aebcf..cd729706b3a9 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -231,7 +231,8 @@ static void __init omap2_gp_clocksource_init(void)
231static void __init omap2_gp_timer_init(void) 231static void __init omap2_gp_timer_init(void)
232{ 232{
233#ifdef CONFIG_LOCAL_TIMERS 233#ifdef CONFIG_LOCAL_TIMERS
234 twd_base = OMAP2_IO_ADDRESS(OMAP44XX_LOCAL_TWD_BASE); 234 twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
235 BUG_ON(!twd_base);
235#endif 236#endif
236 omap_dm_timer_init(); 237 omap_dm_timer_init();
237 238