diff options
| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2009-02-01 12:53:26 -0500 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-02-01 12:53:26 -0500 |
| commit | de8696203e64f19ea26f8e096ac8a796e78216b3 (patch) | |
| tree | d932f2f04d6c81c75c5104ae86b1e5d47e6591e3 /arch/arm/mach-omap2 | |
| parent | 807a96cd0e5f5311e7f7a1030b43aab624cd7d9f (diff) | |
| parent | 0dc23d704874e892c3fb5f2c0e4dfbef3c9c6edf (diff) | |
Merge branch 'omap-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6
Diffstat (limited to 'arch/arm/mach-omap2')
| -rw-r--r-- | arch/arm/mach-omap2/devices.c | 11 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/id.c | 6 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/irq.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/mcbsp.c | 145 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/sleep24xx.S | 3 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/timer-gp.c | 3 |
6 files changed, 41 insertions, 128 deletions
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 9d7216ff6c9f..ce03fa750775 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
| @@ -421,6 +421,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, | |||
| 421 | int nr_controllers) | 421 | int nr_controllers) |
| 422 | { | 422 | { |
| 423 | int i; | 423 | int i; |
| 424 | char *name; | ||
| 424 | 425 | ||
| 425 | for (i = 0; i < nr_controllers; i++) { | 426 | for (i = 0; i < nr_controllers; i++) { |
| 426 | unsigned long base, size; | 427 | unsigned long base, size; |
| @@ -450,12 +451,14 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, | |||
| 450 | continue; | 451 | continue; |
| 451 | } | 452 | } |
| 452 | 453 | ||
| 453 | if (cpu_is_omap2420()) | 454 | if (cpu_is_omap2420()) { |
| 454 | size = OMAP2420_MMC_SIZE; | 455 | size = OMAP2420_MMC_SIZE; |
| 455 | else | 456 | name = "mmci-omap"; |
| 457 | } else { | ||
| 456 | size = HSMMC_SIZE; | 458 | size = HSMMC_SIZE; |
| 457 | 459 | name = "mmci-omap-hs"; | |
| 458 | omap_mmc_add(i, base, size, irq, mmc_data[i]); | 460 | } |
| 461 | omap_mmc_add(name, i, base, size, irq, mmc_data[i]); | ||
| 459 | }; | 462 | }; |
| 460 | } | 463 | } |
| 461 | 464 | ||
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index b0f8e7d62798..b52a02fc7cd6 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
| @@ -172,9 +172,13 @@ void __init omap34xx_check_revision(void) | |||
| 172 | omap_revision = OMAP3430_REV_ES3_0; | 172 | omap_revision = OMAP3430_REV_ES3_0; |
| 173 | rev_name = "ES3.0"; | 173 | rev_name = "ES3.0"; |
| 174 | break; | 174 | break; |
| 175 | case 4: | ||
| 176 | omap_revision = OMAP3430_REV_ES3_1; | ||
| 177 | rev_name = "ES3.1"; | ||
| 178 | break; | ||
| 175 | default: | 179 | default: |
| 176 | /* Use the latest known revision as default */ | 180 | /* Use the latest known revision as default */ |
| 177 | omap_revision = OMAP3430_REV_ES3_0; | 181 | omap_revision = OMAP3430_REV_ES3_1; |
| 178 | rev_name = "Unknown revision\n"; | 182 | rev_name = "Unknown revision\n"; |
| 179 | } | 183 | } |
| 180 | } | 184 | } |
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 636e2821af7d..9ba20d985dda 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c | |||
| @@ -134,6 +134,7 @@ static struct irq_chip omap_irq_chip = { | |||
| 134 | .ack = omap_mask_ack_irq, | 134 | .ack = omap_mask_ack_irq, |
| 135 | .mask = omap_mask_irq, | 135 | .mask = omap_mask_irq, |
| 136 | .unmask = omap_unmask_irq, | 136 | .unmask = omap_unmask_irq, |
| 137 | .disable = omap_mask_irq, | ||
| 137 | }; | 138 | }; |
| 138 | 139 | ||
| 139 | static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) | 140 | static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) |
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index e20023c9d15d..a9e631fc1134 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c | |||
| @@ -24,106 +24,7 @@ | |||
| 24 | #include <mach/cpu.h> | 24 | #include <mach/cpu.h> |
| 25 | #include <mach/mcbsp.h> | 25 | #include <mach/mcbsp.h> |
| 26 | 26 | ||
| 27 | struct mcbsp_internal_clk { | 27 | const char *clk_names[] = { "mcbsp_ick", "mcbsp_fck" }; |
| 28 | struct clk clk; | ||
| 29 | struct clk **childs; | ||
| 30 | int n_childs; | ||
| 31 | }; | ||
| 32 | |||
| 33 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | ||
| 34 | static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk) | ||
| 35 | { | ||
| 36 | const char *clk_names[] = { "mcbsp_ick", "mcbsp_fck" }; | ||
| 37 | int i; | ||
| 38 | |||
| 39 | mclk->n_childs = ARRAY_SIZE(clk_names); | ||
| 40 | mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *), | ||
| 41 | GFP_KERNEL); | ||
| 42 | |||
| 43 | for (i = 0; i < mclk->n_childs; i++) { | ||
| 44 | /* We fake a platform device to get correct device id */ | ||
| 45 | struct platform_device pdev; | ||
| 46 | |||
| 47 | pdev.dev.bus = &platform_bus_type; | ||
| 48 | pdev.id = mclk->clk.id; | ||
| 49 | mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]); | ||
| 50 | if (IS_ERR(mclk->childs[i])) | ||
| 51 | printk(KERN_ERR "Could not get clock %s (%d).\n", | ||
| 52 | clk_names[i], mclk->clk.id); | ||
| 53 | } | ||
| 54 | } | ||
| 55 | |||
| 56 | static int omap_mcbsp_clk_enable(struct clk *clk) | ||
| 57 | { | ||
| 58 | struct mcbsp_internal_clk *mclk = container_of(clk, | ||
| 59 | struct mcbsp_internal_clk, clk); | ||
| 60 | int i; | ||
| 61 | |||
| 62 | for (i = 0; i < mclk->n_childs; i++) | ||
| 63 | clk_enable(mclk->childs[i]); | ||
| 64 | return 0; | ||
| 65 | } | ||
| 66 | |||
| 67 | static void omap_mcbsp_clk_disable(struct clk *clk) | ||
| 68 | { | ||
| 69 | struct mcbsp_internal_clk *mclk = container_of(clk, | ||
| 70 | struct mcbsp_internal_clk, clk); | ||
| 71 | int i; | ||
| 72 | |||
| 73 | for (i = 0; i < mclk->n_childs; i++) | ||
| 74 | clk_disable(mclk->childs[i]); | ||
| 75 | } | ||
| 76 | |||
| 77 | static struct mcbsp_internal_clk omap_mcbsp_clks[] = { | ||
| 78 | { | ||
| 79 | .clk = { | ||
| 80 | .name = "mcbsp_clk", | ||
| 81 | .id = 1, | ||
| 82 | .enable = omap_mcbsp_clk_enable, | ||
| 83 | .disable = omap_mcbsp_clk_disable, | ||
| 84 | }, | ||
| 85 | }, | ||
| 86 | { | ||
| 87 | .clk = { | ||
| 88 | .name = "mcbsp_clk", | ||
| 89 | .id = 2, | ||
| 90 | .enable = omap_mcbsp_clk_enable, | ||
| 91 | .disable = omap_mcbsp_clk_disable, | ||
| 92 | }, | ||
| 93 | }, | ||
| 94 | { | ||
| 95 | .clk = { | ||
| 96 | .name = "mcbsp_clk", | ||
| 97 | .id = 3, | ||
| 98 | .enable = omap_mcbsp_clk_enable, | ||
| 99 | .disable = omap_mcbsp_clk_disable, | ||
| 100 | }, | ||
| 101 | }, | ||
| 102 | { | ||
| 103 | .clk = { | ||
| 104 | .name = "mcbsp_clk", | ||
| 105 | .id = 4, | ||
| 106 | .enable = omap_mcbsp_clk_enable, | ||
| 107 | .disable = omap_mcbsp_clk_disable, | ||
| 108 | }, | ||
| 109 | }, | ||
| 110 | { | ||
| 111 | .clk = { | ||
| 112 | .name = "mcbsp_clk", | ||
| 113 | .id = 5, | ||
| 114 | .enable = omap_mcbsp_clk_enable, | ||
| 115 | .disable = omap_mcbsp_clk_disable, | ||
| 116 | }, | ||
| 117 | }, | ||
| 118 | }; | ||
| 119 | |||
| 120 | #define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks) | ||
| 121 | #else | ||
| 122 | #define omap_mcbsp_clks_size 0 | ||
| 123 | static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks; | ||
| 124 | static inline void omap_mcbsp_clk_init(struct clk *clk) | ||
| 125 | { } | ||
| 126 | #endif | ||
| 127 | 28 | ||
| 128 | static void omap2_mcbsp2_mux_setup(void) | 29 | static void omap2_mcbsp2_mux_setup(void) |
| 129 | { | 30 | { |
| @@ -156,7 +57,8 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { | |||
| 156 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | 57 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
| 157 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | 58 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
| 158 | .ops = &omap2_mcbsp_ops, | 59 | .ops = &omap2_mcbsp_ops, |
| 159 | .clk_name = "mcbsp_clk", | 60 | .clk_names = clk_names, |
| 61 | .num_clks = 2, | ||
| 160 | }, | 62 | }, |
| 161 | { | 63 | { |
| 162 | .phys_base = OMAP24XX_MCBSP2_BASE, | 64 | .phys_base = OMAP24XX_MCBSP2_BASE, |
| @@ -165,7 +67,8 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { | |||
| 165 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 67 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| 166 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | 68 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
| 167 | .ops = &omap2_mcbsp_ops, | 69 | .ops = &omap2_mcbsp_ops, |
| 168 | .clk_name = "mcbsp_clk", | 70 | .clk_names = clk_names, |
| 71 | .num_clks = 2, | ||
| 169 | }, | 72 | }, |
| 170 | }; | 73 | }; |
| 171 | #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) | 74 | #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) |
| @@ -183,7 +86,8 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 183 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | 86 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
| 184 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | 87 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
| 185 | .ops = &omap2_mcbsp_ops, | 88 | .ops = &omap2_mcbsp_ops, |
| 186 | .clk_name = "mcbsp_clk", | 89 | .clk_names = clk_names, |
| 90 | .num_clks = 2, | ||
| 187 | }, | 91 | }, |
| 188 | { | 92 | { |
| 189 | .phys_base = OMAP24XX_MCBSP2_BASE, | 93 | .phys_base = OMAP24XX_MCBSP2_BASE, |
| @@ -192,7 +96,8 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 192 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 96 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| 193 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | 97 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
| 194 | .ops = &omap2_mcbsp_ops, | 98 | .ops = &omap2_mcbsp_ops, |
| 195 | .clk_name = "mcbsp_clk", | 99 | .clk_names = clk_names, |
| 100 | .num_clks = 2, | ||
| 196 | }, | 101 | }, |
| 197 | { | 102 | { |
| 198 | .phys_base = OMAP2430_MCBSP3_BASE, | 103 | .phys_base = OMAP2430_MCBSP3_BASE, |
| @@ -201,7 +106,8 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 201 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, | 106 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, |
| 202 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, | 107 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, |
| 203 | .ops = &omap2_mcbsp_ops, | 108 | .ops = &omap2_mcbsp_ops, |
| 204 | .clk_name = "mcbsp_clk", | 109 | .clk_names = clk_names, |
| 110 | .num_clks = 2, | ||
| 205 | }, | 111 | }, |
| 206 | { | 112 | { |
| 207 | .phys_base = OMAP2430_MCBSP4_BASE, | 113 | .phys_base = OMAP2430_MCBSP4_BASE, |
| @@ -210,7 +116,8 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 210 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, | 116 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, |
| 211 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, | 117 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, |
| 212 | .ops = &omap2_mcbsp_ops, | 118 | .ops = &omap2_mcbsp_ops, |
| 213 | .clk_name = "mcbsp_clk", | 119 | .clk_names = clk_names, |
| 120 | .num_clks = 2, | ||
| 214 | }, | 121 | }, |
| 215 | { | 122 | { |
| 216 | .phys_base = OMAP2430_MCBSP5_BASE, | 123 | .phys_base = OMAP2430_MCBSP5_BASE, |
| @@ -219,7 +126,8 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 219 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, | 126 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, |
| 220 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, | 127 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, |
| 221 | .ops = &omap2_mcbsp_ops, | 128 | .ops = &omap2_mcbsp_ops, |
| 222 | .clk_name = "mcbsp_clk", | 129 | .clk_names = clk_names, |
| 130 | .num_clks = 2, | ||
| 223 | }, | 131 | }, |
| 224 | }; | 132 | }; |
| 225 | #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) | 133 | #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) |
| @@ -237,7 +145,8 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 237 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | 145 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
| 238 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | 146 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
| 239 | .ops = &omap2_mcbsp_ops, | 147 | .ops = &omap2_mcbsp_ops, |
| 240 | .clk_name = "mcbsp_clk", | 148 | .clk_names = clk_names, |
| 149 | .num_clks = 2, | ||
| 241 | }, | 150 | }, |
| 242 | { | 151 | { |
| 243 | .phys_base = OMAP34XX_MCBSP2_BASE, | 152 | .phys_base = OMAP34XX_MCBSP2_BASE, |
| @@ -246,7 +155,8 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 246 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 155 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| 247 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | 156 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
| 248 | .ops = &omap2_mcbsp_ops, | 157 | .ops = &omap2_mcbsp_ops, |
| 249 | .clk_name = "mcbsp_clk", | 158 | .clk_names = clk_names, |
| 159 | .num_clks = 2, | ||
| 250 | }, | 160 | }, |
| 251 | { | 161 | { |
| 252 | .phys_base = OMAP34XX_MCBSP3_BASE, | 162 | .phys_base = OMAP34XX_MCBSP3_BASE, |
| @@ -255,7 +165,8 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 255 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, | 165 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, |
| 256 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, | 166 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, |
| 257 | .ops = &omap2_mcbsp_ops, | 167 | .ops = &omap2_mcbsp_ops, |
| 258 | .clk_name = "mcbsp_clk", | 168 | .clk_names = clk_names, |
| 169 | .num_clks = 2, | ||
| 259 | }, | 170 | }, |
| 260 | { | 171 | { |
| 261 | .phys_base = OMAP34XX_MCBSP4_BASE, | 172 | .phys_base = OMAP34XX_MCBSP4_BASE, |
| @@ -264,7 +175,8 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 264 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, | 175 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, |
| 265 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, | 176 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, |
| 266 | .ops = &omap2_mcbsp_ops, | 177 | .ops = &omap2_mcbsp_ops, |
| 267 | .clk_name = "mcbsp_clk", | 178 | .clk_names = clk_names, |
| 179 | .num_clks = 2, | ||
| 268 | }, | 180 | }, |
| 269 | { | 181 | { |
| 270 | .phys_base = OMAP34XX_MCBSP5_BASE, | 182 | .phys_base = OMAP34XX_MCBSP5_BASE, |
| @@ -273,7 +185,8 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 273 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, | 185 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, |
| 274 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, | 186 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, |
| 275 | .ops = &omap2_mcbsp_ops, | 187 | .ops = &omap2_mcbsp_ops, |
| 276 | .clk_name = "mcbsp_clk", | 188 | .clk_names = clk_names, |
| 189 | .num_clks = 2, | ||
| 277 | }, | 190 | }, |
| 278 | }; | 191 | }; |
| 279 | #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) | 192 | #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) |
| @@ -284,14 +197,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 284 | 197 | ||
| 285 | static int __init omap2_mcbsp_init(void) | 198 | static int __init omap2_mcbsp_init(void) |
| 286 | { | 199 | { |
| 287 | int i; | ||
| 288 | |||
| 289 | for (i = 0; i < omap_mcbsp_clks_size; i++) { | ||
| 290 | /* Once we call clk_get inside init, we do not register it */ | ||
| 291 | omap_mcbsp_clk_init(&omap_mcbsp_clks[i]); | ||
| 292 | clk_register(&omap_mcbsp_clks[i].clk); | ||
| 293 | } | ||
| 294 | |||
| 295 | if (cpu_is_omap2420()) | 200 | if (cpu_is_omap2420()) |
| 296 | omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; | 201 | omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ; |
| 297 | if (cpu_is_omap2430()) | 202 | if (cpu_is_omap2430()) |
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S index 43336b93b21c..bf9e96105e11 100644 --- a/arch/arm/mach-omap2/sleep24xx.S +++ b/arch/arm/mach-omap2/sleep24xx.S | |||
| @@ -93,9 +93,8 @@ ENTRY(omap24xx_cpu_suspend) | |||
| 93 | orr r4, r4, #0x40 @ enable self refresh on idle req | 93 | orr r4, r4, #0x40 @ enable self refresh on idle req |
| 94 | mov r5, #0x2000 @ set delay (DPLL relock + DLL relock) | 94 | mov r5, #0x2000 @ set delay (DPLL relock + DLL relock) |
| 95 | str r4, [r2] @ make it so | 95 | str r4, [r2] @ make it so |
| 96 | mov r2, #0 | ||
| 97 | nop | 96 | nop |
| 98 | mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt | 97 | mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt |
| 99 | nop | 98 | nop |
| 100 | loop: | 99 | loop: |
| 101 | subs r5, r5, #0x1 @ awake, wait just a bit | 100 | subs r5, r5, #0x1 @ awake, wait just a bit |
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index ae6036300f60..9fc13a2cc3f4 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c | |||
| @@ -118,7 +118,8 @@ static void __init omap2_gp_clockevent_init(void) | |||
| 118 | clockevent_gpt.max_delta_ns = | 118 | clockevent_gpt.max_delta_ns = |
| 119 | clockevent_delta2ns(0xffffffff, &clockevent_gpt); | 119 | clockevent_delta2ns(0xffffffff, &clockevent_gpt); |
| 120 | clockevent_gpt.min_delta_ns = | 120 | clockevent_gpt.min_delta_ns = |
| 121 | clockevent_delta2ns(1, &clockevent_gpt); | 121 | clockevent_delta2ns(3, &clockevent_gpt); |
| 122 | /* Timer internal resynch latency. */ | ||
| 122 | 123 | ||
| 123 | clockevent_gpt.cpumask = cpumask_of(0); | 124 | clockevent_gpt.cpumask = cpumask_of(0); |
| 124 | clockevents_register_device(&clockevent_gpt); | 125 | clockevents_register_device(&clockevent_gpt); |
