diff options
author | Philip Avinash <avinashphilip@ti.com> | 2013-01-02 08:24:48 -0500 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2013-02-08 09:56:48 -0500 |
commit | bee76659e268ab9165e4dceee5b5410f3b22cd1c (patch) | |
tree | d39c3a9483ff1fd98d54e12cd677cb99fb5c4f49 /arch/arm/mach-omap2 | |
parent | f6575c90f6fc637697f130ea4a05892296c9a473 (diff) |
ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries
EQEP IP block integration data is not present in HWMOD data. Also
address ranges specified for EACP & EHRPWM are not correct & HWMOD
flags of ADDR_TYPE_RT are added to PWM subsystem register address
space. This patch:
1. Corrects register address mapping for ECAP & EHRPWM
2. Removes HWMOD flags in PWM submodule register address space.
3. Adds EQEP HWMOD entries.
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
[paul@pwsan.com: tweaked patch description]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 158 |
1 files changed, 145 insertions, 13 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index 9e34d4cbc586..4b1cc4d4c9a3 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c | |||
@@ -784,7 +784,7 @@ static struct omap_hwmod am33xx_elm_hwmod = { | |||
784 | }; | 784 | }; |
785 | 785 | ||
786 | /* | 786 | /* |
787 | * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2 | 787 | * 'epwmss' class: ehrpwm0,1,2 eqep0,1,2 ecap0,1,2 |
788 | */ | 788 | */ |
789 | static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { | 789 | static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { |
790 | .rev_offs = 0x0, | 790 | .rev_offs = 0x0, |
@@ -864,6 +864,66 @@ static struct omap_hwmod am33xx_ehrpwm2_hwmod = { | |||
864 | }, | 864 | }, |
865 | }; | 865 | }; |
866 | 866 | ||
867 | /* eqep0 */ | ||
868 | static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = { | ||
869 | { .irq = 79 + OMAP_INTC_START, }, | ||
870 | { .irq = -1 }, | ||
871 | }; | ||
872 | |||
873 | static struct omap_hwmod am33xx_eqep0_hwmod = { | ||
874 | .name = "eqep0", | ||
875 | .class = &am33xx_epwmss_hwmod_class, | ||
876 | .clkdm_name = "l4ls_clkdm", | ||
877 | .mpu_irqs = am33xx_eqep0_irqs, | ||
878 | .main_clk = "l4ls_gclk", | ||
879 | .prcm = { | ||
880 | .omap4 = { | ||
881 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, | ||
882 | .modulemode = MODULEMODE_SWCTRL, | ||
883 | }, | ||
884 | }, | ||
885 | }; | ||
886 | |||
887 | /* eqep1 */ | ||
888 | static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = { | ||
889 | { .irq = 88 + OMAP_INTC_START, }, | ||
890 | { .irq = -1 }, | ||
891 | }; | ||
892 | |||
893 | static struct omap_hwmod am33xx_eqep1_hwmod = { | ||
894 | .name = "eqep1", | ||
895 | .class = &am33xx_epwmss_hwmod_class, | ||
896 | .clkdm_name = "l4ls_clkdm", | ||
897 | .mpu_irqs = am33xx_eqep1_irqs, | ||
898 | .main_clk = "l4ls_gclk", | ||
899 | .prcm = { | ||
900 | .omap4 = { | ||
901 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, | ||
902 | .modulemode = MODULEMODE_SWCTRL, | ||
903 | }, | ||
904 | }, | ||
905 | }; | ||
906 | |||
907 | /* eqep2 */ | ||
908 | static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = { | ||
909 | { .irq = 89 + OMAP_INTC_START, }, | ||
910 | { .irq = -1 }, | ||
911 | }; | ||
912 | |||
913 | static struct omap_hwmod am33xx_eqep2_hwmod = { | ||
914 | .name = "eqep2", | ||
915 | .class = &am33xx_epwmss_hwmod_class, | ||
916 | .clkdm_name = "l4ls_clkdm", | ||
917 | .mpu_irqs = am33xx_eqep2_irqs, | ||
918 | .main_clk = "l4ls_gclk", | ||
919 | .prcm = { | ||
920 | .omap4 = { | ||
921 | .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET, | ||
922 | .modulemode = MODULEMODE_SWCTRL, | ||
923 | }, | ||
924 | }, | ||
925 | }; | ||
926 | |||
867 | /* ecap0 */ | 927 | /* ecap0 */ |
868 | static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = { | 928 | static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = { |
869 | { .irq = 31 + OMAP_INTC_START, }, | 929 | { .irq = 31 + OMAP_INTC_START, }, |
@@ -2559,8 +2619,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = { | |||
2559 | }, | 2619 | }, |
2560 | { | 2620 | { |
2561 | .pa_start = 0x48300200, | 2621 | .pa_start = 0x48300200, |
2562 | .pa_end = 0x48300200 + SZ_256 - 1, | 2622 | .pa_end = 0x48300200 + SZ_128 - 1, |
2563 | .flags = ADDR_TYPE_RT | ||
2564 | }, | 2623 | }, |
2565 | { } | 2624 | { } |
2566 | }; | 2625 | }; |
@@ -2585,8 +2644,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = { | |||
2585 | }, | 2644 | }, |
2586 | { | 2645 | { |
2587 | .pa_start = 0x48302200, | 2646 | .pa_start = 0x48302200, |
2588 | .pa_end = 0x48302200 + SZ_256 - 1, | 2647 | .pa_end = 0x48302200 + SZ_128 - 1, |
2589 | .flags = ADDR_TYPE_RT | ||
2590 | }, | 2648 | }, |
2591 | { } | 2649 | { } |
2592 | }; | 2650 | }; |
@@ -2611,8 +2669,7 @@ static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = { | |||
2611 | }, | 2669 | }, |
2612 | { | 2670 | { |
2613 | .pa_start = 0x48304200, | 2671 | .pa_start = 0x48304200, |
2614 | .pa_end = 0x48304200 + SZ_256 - 1, | 2672 | .pa_end = 0x48304200 + SZ_128 - 1, |
2615 | .flags = ADDR_TYPE_RT | ||
2616 | }, | 2673 | }, |
2617 | { } | 2674 | { } |
2618 | }; | 2675 | }; |
@@ -2629,6 +2686,81 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = { | |||
2629 | * Splitting the resources to handle access of PWMSS config space | 2686 | * Splitting the resources to handle access of PWMSS config space |
2630 | * and module specific part independently | 2687 | * and module specific part independently |
2631 | */ | 2688 | */ |
2689 | static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = { | ||
2690 | { | ||
2691 | .pa_start = 0x48300000, | ||
2692 | .pa_end = 0x48300000 + SZ_16 - 1, | ||
2693 | .flags = ADDR_TYPE_RT | ||
2694 | }, | ||
2695 | { | ||
2696 | .pa_start = 0x48300180, | ||
2697 | .pa_end = 0x48300180 + SZ_128 - 1, | ||
2698 | }, | ||
2699 | { } | ||
2700 | }; | ||
2701 | |||
2702 | static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep0 = { | ||
2703 | .master = &am33xx_l4_ls_hwmod, | ||
2704 | .slave = &am33xx_eqep0_hwmod, | ||
2705 | .clk = "l4ls_gclk", | ||
2706 | .addr = am33xx_eqep0_addr_space, | ||
2707 | .user = OCP_USER_MPU, | ||
2708 | }; | ||
2709 | |||
2710 | /* | ||
2711 | * Splitting the resources to handle access of PWMSS config space | ||
2712 | * and module specific part independently | ||
2713 | */ | ||
2714 | static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = { | ||
2715 | { | ||
2716 | .pa_start = 0x48302000, | ||
2717 | .pa_end = 0x48302000 + SZ_16 - 1, | ||
2718 | .flags = ADDR_TYPE_RT | ||
2719 | }, | ||
2720 | { | ||
2721 | .pa_start = 0x48302180, | ||
2722 | .pa_end = 0x48302180 + SZ_128 - 1, | ||
2723 | }, | ||
2724 | { } | ||
2725 | }; | ||
2726 | |||
2727 | static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep1 = { | ||
2728 | .master = &am33xx_l4_ls_hwmod, | ||
2729 | .slave = &am33xx_eqep1_hwmod, | ||
2730 | .clk = "l4ls_gclk", | ||
2731 | .addr = am33xx_eqep1_addr_space, | ||
2732 | .user = OCP_USER_MPU, | ||
2733 | }; | ||
2734 | |||
2735 | /* | ||
2736 | * Splitting the resources to handle access of PWMSS config space | ||
2737 | * and module specific part independently | ||
2738 | */ | ||
2739 | static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = { | ||
2740 | { | ||
2741 | .pa_start = 0x48304000, | ||
2742 | .pa_end = 0x48304000 + SZ_16 - 1, | ||
2743 | .flags = ADDR_TYPE_RT | ||
2744 | }, | ||
2745 | { | ||
2746 | .pa_start = 0x48304180, | ||
2747 | .pa_end = 0x48304180 + SZ_128 - 1, | ||
2748 | }, | ||
2749 | { } | ||
2750 | }; | ||
2751 | |||
2752 | static struct omap_hwmod_ocp_if am33xx_l4_ls__eqep2 = { | ||
2753 | .master = &am33xx_l4_ls_hwmod, | ||
2754 | .slave = &am33xx_eqep2_hwmod, | ||
2755 | .clk = "l4ls_gclk", | ||
2756 | .addr = am33xx_eqep2_addr_space, | ||
2757 | .user = OCP_USER_MPU, | ||
2758 | }; | ||
2759 | |||
2760 | /* | ||
2761 | * Splitting the resources to handle access of PWMSS config space | ||
2762 | * and module specific part independently | ||
2763 | */ | ||
2632 | static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = { | 2764 | static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = { |
2633 | { | 2765 | { |
2634 | .pa_start = 0x48300000, | 2766 | .pa_start = 0x48300000, |
@@ -2637,8 +2769,7 @@ static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = { | |||
2637 | }, | 2769 | }, |
2638 | { | 2770 | { |
2639 | .pa_start = 0x48300100, | 2771 | .pa_start = 0x48300100, |
2640 | .pa_end = 0x48300100 + SZ_256 - 1, | 2772 | .pa_end = 0x48300100 + SZ_128 - 1, |
2641 | .flags = ADDR_TYPE_RT | ||
2642 | }, | 2773 | }, |
2643 | { } | 2774 | { } |
2644 | }; | 2775 | }; |
@@ -2663,8 +2794,7 @@ static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = { | |||
2663 | }, | 2794 | }, |
2664 | { | 2795 | { |
2665 | .pa_start = 0x48302100, | 2796 | .pa_start = 0x48302100, |
2666 | .pa_end = 0x48302100 + SZ_256 - 1, | 2797 | .pa_end = 0x48302100 + SZ_128 - 1, |
2667 | .flags = ADDR_TYPE_RT | ||
2668 | }, | 2798 | }, |
2669 | { } | 2799 | { } |
2670 | }; | 2800 | }; |
@@ -2689,8 +2819,7 @@ static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = { | |||
2689 | }, | 2819 | }, |
2690 | { | 2820 | { |
2691 | .pa_start = 0x48304100, | 2821 | .pa_start = 0x48304100, |
2692 | .pa_end = 0x48304100 + SZ_256 - 1, | 2822 | .pa_end = 0x48304100 + SZ_128 - 1, |
2693 | .flags = ADDR_TYPE_RT | ||
2694 | }, | 2823 | }, |
2695 | { } | 2824 | { } |
2696 | }; | 2825 | }; |
@@ -3395,6 +3524,9 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { | |||
3395 | &am33xx_l4_ls__ehrpwm0, | 3524 | &am33xx_l4_ls__ehrpwm0, |
3396 | &am33xx_l4_ls__ehrpwm1, | 3525 | &am33xx_l4_ls__ehrpwm1, |
3397 | &am33xx_l4_ls__ehrpwm2, | 3526 | &am33xx_l4_ls__ehrpwm2, |
3527 | &am33xx_l4_ls__eqep0, | ||
3528 | &am33xx_l4_ls__eqep1, | ||
3529 | &am33xx_l4_ls__eqep2, | ||
3398 | &am33xx_l4_ls__ecap0, | 3530 | &am33xx_l4_ls__ecap0, |
3399 | &am33xx_l4_ls__ecap1, | 3531 | &am33xx_l4_ls__ecap1, |
3400 | &am33xx_l4_ls__ecap2, | 3532 | &am33xx_l4_ls__ecap2, |