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authorLinus Torvalds <torvalds@linux-foundation.org>2009-09-23 13:07:49 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-09-23 13:07:49 -0400
commita7c367b95a9d8e65e0f0e7da31f700a556794efb (patch)
tree5b1bb202801e29e3237381aa7aad5aa288378d5b /arch/arm/mach-omap2
parent15f964bed054821d6d940d3752508c5f96a9ffd3 (diff)
parente1070211f7327a1f197d535aa886f721a241c32f (diff)
Merge git://git.infradead.org/mtd-2.6
* git://git.infradead.org/mtd-2.6: (58 commits) mtd: jedec_probe: add PSD4256G6V id mtd: OneNand support for Nomadik 8815 SoC (on NHK8815 board) mtd: nand: driver for Nomadik 8815 SoC (on NHK8815 board) m25p80: Add Spansion S25FL129P serial flashes jffs2: Use SLAB_HWCACHE_ALIGN for jffs2_raw_{dirent,inode} slabs mtd: sh_flctl: register sh_flctl using platform_driver_probe() mtd: nand: txx9ndfmc: transfer 512 byte at a time if possible mtd: nand: fix tmio_nand ecc correction mtd: nand: add __nand_correct_data helper function mtd: cfi_cmdset_0002: add 0xFF intolerance for M29W128G mtd: inftl: fix fold chain block number mtd: jedec: fix compilation problem with I28F640C3B definition mtd: nand: fix ECC Correction bug for SMC ordering for NDFC driver mtd: ofpart: Check availability of reg property instead of name property driver/Makefile: Initialize "mtd" and "spi" before "net" mtd: omap: adding DMA mode support in nand prefetch/post-write mtd: omap: add support for nand prefetch-read and post-write mtd: add nand support for w90p910 (v2) mtd: maps: add mtd-ram support to physmap_of mtd: pxa3xx_nand: add single-bit error corrections reporting ...
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/board-apollon.c4
-rw-r--r--arch/arm/mach-omap2/gpmc.c63
2 files changed, 64 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 7a2b54c7291a..a1132288c701 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -87,7 +87,7 @@ static struct mtd_partition apollon_partitions[] = {
87 }, 87 },
88}; 88};
89 89
90static struct flash_platform_data apollon_flash_data = { 90static struct onenand_platform_data apollon_flash_data = {
91 .parts = apollon_partitions, 91 .parts = apollon_partitions,
92 .nr_parts = ARRAY_SIZE(apollon_partitions), 92 .nr_parts = ARRAY_SIZE(apollon_partitions),
93}; 93};
@@ -99,7 +99,7 @@ static struct resource apollon_flash_resource[] = {
99}; 99};
100 100
101static struct platform_device apollon_onenand_device = { 101static struct platform_device apollon_onenand_device = {
102 .name = "onenand", 102 .name = "onenand-flash",
103 .id = -1, 103 .id = -1,
104 .dev = { 104 .dev = {
105 .platform_data = &apollon_flash_data, 105 .platform_data = &apollon_flash_data,
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index f91934b2b092..15876828db23 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -57,6 +57,11 @@
57#define GPMC_CHUNK_SHIFT 24 /* 16 MB */ 57#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
58#define GPMC_SECTION_SHIFT 28 /* 128 MB */ 58#define GPMC_SECTION_SHIFT 28 /* 128 MB */
59 59
60#define PREFETCH_FIFOTHRESHOLD (0x40 << 8)
61#define CS_NUM_SHIFT 24
62#define ENABLE_PREFETCH (0x1 << 7)
63#define DMA_MPU_MODE 2
64
60static struct resource gpmc_mem_root; 65static struct resource gpmc_mem_root;
61static struct resource gpmc_cs_mem[GPMC_CS_NUM]; 66static struct resource gpmc_cs_mem[GPMC_CS_NUM];
62static DEFINE_SPINLOCK(gpmc_mem_lock); 67static DEFINE_SPINLOCK(gpmc_mem_lock);
@@ -386,6 +391,63 @@ void gpmc_cs_free(int cs)
386} 391}
387EXPORT_SYMBOL(gpmc_cs_free); 392EXPORT_SYMBOL(gpmc_cs_free);
388 393
394/**
395 * gpmc_prefetch_enable - configures and starts prefetch transfer
396 * @cs: nand cs (chip select) number
397 * @dma_mode: dma mode enable (1) or disable (0)
398 * @u32_count: number of bytes to be transferred
399 * @is_write: prefetch read(0) or write post(1) mode
400 */
401int gpmc_prefetch_enable(int cs, int dma_mode,
402 unsigned int u32_count, int is_write)
403{
404 uint32_t prefetch_config1;
405
406 if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
407 /* Set the amount of bytes to be prefetched */
408 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
409
410 /* Set dma/mpu mode, the prefetch read / post write and
411 * enable the engine. Set which cs is has requested for.
412 */
413 prefetch_config1 = ((cs << CS_NUM_SHIFT) |
414 PREFETCH_FIFOTHRESHOLD |
415 ENABLE_PREFETCH |
416 (dma_mode << DMA_MPU_MODE) |
417 (0x1 & is_write));
418 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
419 } else {
420 return -EBUSY;
421 }
422 /* Start the prefetch engine */
423 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
424
425 return 0;
426}
427EXPORT_SYMBOL(gpmc_prefetch_enable);
428
429/**
430 * gpmc_prefetch_reset - disables and stops the prefetch engine
431 */
432void gpmc_prefetch_reset(void)
433{
434 /* Stop the PFPW engine */
435 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
436
437 /* Reset/disable the PFPW engine */
438 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
439}
440EXPORT_SYMBOL(gpmc_prefetch_reset);
441
442/**
443 * gpmc_prefetch_status - reads prefetch status of engine
444 */
445int gpmc_prefetch_status(void)
446{
447 return gpmc_read_reg(GPMC_PREFETCH_STATUS);
448}
449EXPORT_SYMBOL(gpmc_prefetch_status);
450
389static void __init gpmc_mem_init(void) 451static void __init gpmc_mem_init(void)
390{ 452{
391 int cs; 453 int cs;
@@ -452,6 +514,5 @@ void __init gpmc_init(void)
452 l &= 0x03 << 3; 514 l &= 0x03 << 3;
453 l |= (0x02 << 3) | (1 << 0); 515 l |= (0x02 << 3) | (1 << 0);
454 gpmc_write_reg(GPMC_SYSCONFIG, l); 516 gpmc_write_reg(GPMC_SYSCONFIG, l);
455
456 gpmc_mem_init(); 517 gpmc_mem_init();
457} 518}