diff options
author | Jon Hunter <jon-hunter@ti.com> | 2013-02-20 16:53:38 -0500 |
---|---|---|
committer | Jon Hunter <jon-hunter@ti.com> | 2013-04-01 15:53:40 -0400 |
commit | 9f8331562aa1fd72e80dd6037c958cb3faf4cc38 (patch) | |
tree | d1989fd4b4ec933b36f5645948094e31d51c0e13 /arch/arm/mach-omap2 | |
parent | be9f10c04fb13d32fc30d599c1971a10916a2209 (diff) |
ARM: OMAP2+: Add variable to store number of GPMC waitpins
The GPMC has wait-pin signals that can be assigned to a chip-select
to monitor the ready signal of an external device. Add a variable to
indicate the total number of wait-pins for a given device. This will
allow us to detect if the wait-pin being selected is valid or not.
When booting with device-tree read the number of wait-pins from the
device-tree blob. When device-tree is not used set the number of
wait-pins to 4 which is valid for OMAP2-5 devices. Newer devices
that have less wait-pins (such as AM335x) only support booting with
device-tree and so hard-coding the wait-pin number when not using
device-tree is fine.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r-- | arch/arm/mach-omap2/gpmc.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 586dba7e5f23..8833c349f23c 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
@@ -108,6 +108,8 @@ | |||
108 | #define GPMC_HAS_WR_ACCESS 0x1 | 108 | #define GPMC_HAS_WR_ACCESS 0x1 |
109 | #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 | 109 | #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 |
110 | 110 | ||
111 | #define GPMC_NR_WAITPINS 4 | ||
112 | |||
111 | /* XXX: Only NAND irq has been considered,currently these are the only ones used | 113 | /* XXX: Only NAND irq has been considered,currently these are the only ones used |
112 | */ | 114 | */ |
113 | #define GPMC_NR_IRQ 2 | 115 | #define GPMC_NR_IRQ 2 |
@@ -153,6 +155,7 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM]; | |||
153 | static DEFINE_SPINLOCK(gpmc_mem_lock); | 155 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
154 | /* Define chip-selects as reserved by default until probe completes */ | 156 | /* Define chip-selects as reserved by default until probe completes */ |
155 | static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); | 157 | static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); |
158 | static unsigned int gpmc_nr_waitpins; | ||
156 | static struct device *gpmc_dev; | 159 | static struct device *gpmc_dev; |
157 | static int gpmc_irq; | 160 | static int gpmc_irq; |
158 | static resource_size_t phys_base, mem_size; | 161 | static resource_size_t phys_base, mem_size; |
@@ -1294,6 +1297,13 @@ static int gpmc_probe_dt(struct platform_device *pdev) | |||
1294 | if (!of_id) | 1297 | if (!of_id) |
1295 | return 0; | 1298 | return 0; |
1296 | 1299 | ||
1300 | ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", | ||
1301 | &gpmc_nr_waitpins); | ||
1302 | if (ret < 0) { | ||
1303 | pr_err("%s: number of wait pins not found!\n", __func__); | ||
1304 | return ret; | ||
1305 | } | ||
1306 | |||
1297 | for_each_node_by_name(child, "nand") { | 1307 | for_each_node_by_name(child, "nand") { |
1298 | ret = gpmc_probe_nand_child(pdev, child); | 1308 | ret = gpmc_probe_nand_child(pdev, child); |
1299 | if (ret < 0) { | 1309 | if (ret < 0) { |
@@ -1372,6 +1382,9 @@ static int gpmc_probe(struct platform_device *pdev) | |||
1372 | /* Now the GPMC is initialised, unreserve the chip-selects */ | 1382 | /* Now the GPMC is initialised, unreserve the chip-selects */ |
1373 | gpmc_cs_map = 0; | 1383 | gpmc_cs_map = 0; |
1374 | 1384 | ||
1385 | if (!pdev->dev.of_node) | ||
1386 | gpmc_nr_waitpins = GPMC_NR_WAITPINS; | ||
1387 | |||
1375 | rc = gpmc_probe_dt(pdev); | 1388 | rc = gpmc_probe_dt(pdev); |
1376 | if (rc < 0) { | 1389 | if (rc < 0) { |
1377 | clk_disable_unprepare(gpmc_l3_clk); | 1390 | clk_disable_unprepare(gpmc_l3_clk); |