diff options
| author | Sakari Ailus <sakari.ailus@iki.fi> | 2015-03-25 18:57:35 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@osg.samsung.com> | 2015-04-02 15:45:07 -0400 |
| commit | 8644cdf972dd6dfebf98161025900f6a9d1ad58a (patch) | |
| tree | 58e04bf1a5776d2457ea298180a50b6e4adb54ce /arch/arm/mach-omap2 | |
| parent | 503596a15225e00bdf24f0805567d5195f6c749f (diff) | |
[media] omap3isp: Replace many MMIO regions by two
The omap3isp MMIO register block is contiguous in the MMIO register space
apart from the fact that the ISP IOMMU register block is in the middle of
the area. Ioremap it at two occasions, and keep the rest of the layout of
the register space internal to the omap3isp driver.
Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Diffstat (limited to 'arch/arm/mach-omap2')
| -rw-r--r-- | arch/arm/mach-omap2/devices.c | 66 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap34xx.h | 36 |
2 files changed, 6 insertions, 96 deletions
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index e945957c1604..990338fbaa59 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
| @@ -74,72 +74,12 @@ omap_postcore_initcall(omap3_l3_init); | |||
| 74 | static struct resource omap3isp_resources[] = { | 74 | static struct resource omap3isp_resources[] = { |
| 75 | { | 75 | { |
| 76 | .start = OMAP3430_ISP_BASE, | 76 | .start = OMAP3430_ISP_BASE, |
| 77 | .end = OMAP3430_ISP_END, | 77 | .end = OMAP3430_ISP_BASE + 0x12fc, |
| 78 | .flags = IORESOURCE_MEM, | 78 | .flags = IORESOURCE_MEM, |
| 79 | }, | 79 | }, |
| 80 | { | 80 | { |
| 81 | .start = OMAP3430_ISP_CCP2_BASE, | 81 | .start = OMAP3430_ISP_BASE2, |
| 82 | .end = OMAP3430_ISP_CCP2_END, | 82 | .end = OMAP3430_ISP_BASE2 + 0x0600, |
| 83 | .flags = IORESOURCE_MEM, | ||
| 84 | }, | ||
| 85 | { | ||
| 86 | .start = OMAP3430_ISP_CCDC_BASE, | ||
| 87 | .end = OMAP3430_ISP_CCDC_END, | ||
| 88 | .flags = IORESOURCE_MEM, | ||
| 89 | }, | ||
| 90 | { | ||
| 91 | .start = OMAP3430_ISP_HIST_BASE, | ||
| 92 | .end = OMAP3430_ISP_HIST_END, | ||
| 93 | .flags = IORESOURCE_MEM, | ||
| 94 | }, | ||
| 95 | { | ||
| 96 | .start = OMAP3430_ISP_H3A_BASE, | ||
| 97 | .end = OMAP3430_ISP_H3A_END, | ||
| 98 | .flags = IORESOURCE_MEM, | ||
| 99 | }, | ||
| 100 | { | ||
| 101 | .start = OMAP3430_ISP_PREV_BASE, | ||
| 102 | .end = OMAP3430_ISP_PREV_END, | ||
| 103 | .flags = IORESOURCE_MEM, | ||
| 104 | }, | ||
| 105 | { | ||
| 106 | .start = OMAP3430_ISP_RESZ_BASE, | ||
| 107 | .end = OMAP3430_ISP_RESZ_END, | ||
| 108 | .flags = IORESOURCE_MEM, | ||
| 109 | }, | ||
| 110 | { | ||
| 111 | .start = OMAP3430_ISP_SBL_BASE, | ||
| 112 | .end = OMAP3430_ISP_SBL_END, | ||
| 113 | .flags = IORESOURCE_MEM, | ||
| 114 | }, | ||
| 115 | { | ||
| 116 | .start = OMAP3430_ISP_CSI2A_REGS1_BASE, | ||
| 117 | .end = OMAP3430_ISP_CSI2A_REGS1_END, | ||
| 118 | .flags = IORESOURCE_MEM, | ||
| 119 | }, | ||
| 120 | { | ||
| 121 | .start = OMAP3430_ISP_CSIPHY2_BASE, | ||
| 122 | .end = OMAP3430_ISP_CSIPHY2_END, | ||
| 123 | .flags = IORESOURCE_MEM, | ||
| 124 | }, | ||
| 125 | { | ||
| 126 | .start = OMAP3630_ISP_CSI2A_REGS2_BASE, | ||
| 127 | .end = OMAP3630_ISP_CSI2A_REGS2_END, | ||
| 128 | .flags = IORESOURCE_MEM, | ||
| 129 | }, | ||
| 130 | { | ||
| 131 | .start = OMAP3630_ISP_CSI2C_REGS1_BASE, | ||
| 132 | .end = OMAP3630_ISP_CSI2C_REGS1_END, | ||
| 133 | .flags = IORESOURCE_MEM, | ||
| 134 | }, | ||
| 135 | { | ||
| 136 | .start = OMAP3630_ISP_CSIPHY1_BASE, | ||
| 137 | .end = OMAP3630_ISP_CSIPHY1_END, | ||
| 138 | .flags = IORESOURCE_MEM, | ||
| 139 | }, | ||
| 140 | { | ||
| 141 | .start = OMAP3630_ISP_CSI2C_REGS2_BASE, | ||
| 142 | .end = OMAP3630_ISP_CSI2C_REGS2_END, | ||
| 143 | .flags = IORESOURCE_MEM, | 83 | .flags = IORESOURCE_MEM, |
| 144 | }, | 84 | }, |
| 145 | { | 85 | { |
diff --git a/arch/arm/mach-omap2/omap34xx.h b/arch/arm/mach-omap2/omap34xx.h index c0d1b4b1653f..ed0024dda133 100644 --- a/arch/arm/mach-omap2/omap34xx.h +++ b/arch/arm/mach-omap2/omap34xx.h | |||
| @@ -46,39 +46,9 @@ | |||
| 46 | 46 | ||
| 47 | #define OMAP34XX_IC_BASE 0x48200000 | 47 | #define OMAP34XX_IC_BASE 0x48200000 |
| 48 | 48 | ||
| 49 | #define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000) | 49 | #define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000) |
| 50 | #define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100) | 50 | #define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400) |
| 51 | #define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400) | 51 | #define OMAP3430_ISP_BASE2 (OMAP3430_ISP_BASE + 0x1800) |
| 52 | #define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600) | ||
| 53 | #define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00) | ||
| 54 | #define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00) | ||
| 55 | #define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00) | ||
| 56 | #define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000) | ||
| 57 | #define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200) | ||
| 58 | #define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400) | ||
| 59 | #define OMAP3430_ISP_CSI2A_REGS1_BASE (OMAP3430_ISP_BASE + 0x1800) | ||
| 60 | #define OMAP3430_ISP_CSIPHY2_BASE (OMAP3430_ISP_BASE + 0x1970) | ||
| 61 | #define OMAP3630_ISP_CSI2A_REGS2_BASE (OMAP3430_ISP_BASE + 0x19C0) | ||
| 62 | #define OMAP3630_ISP_CSI2C_REGS1_BASE (OMAP3430_ISP_BASE + 0x1C00) | ||
| 63 | #define OMAP3630_ISP_CSIPHY1_BASE (OMAP3430_ISP_BASE + 0x1D70) | ||
| 64 | #define OMAP3630_ISP_CSI2C_REGS2_BASE (OMAP3430_ISP_BASE + 0x1DC0) | ||
| 65 | |||
| 66 | #define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F) | ||
| 67 | #define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077) | ||
| 68 | #define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF) | ||
| 69 | #define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7) | ||
| 70 | #define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047) | ||
| 71 | #define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F) | ||
| 72 | #define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F) | ||
| 73 | #define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB) | ||
| 74 | #define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB) | ||
| 75 | #define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F) | ||
| 76 | #define OMAP3430_ISP_CSI2A_REGS1_END (OMAP3430_ISP_CSI2A_REGS1_BASE + 0x16F) | ||
| 77 | #define OMAP3430_ISP_CSIPHY2_END (OMAP3430_ISP_CSIPHY2_BASE + 0x00B) | ||
| 78 | #define OMAP3630_ISP_CSI2A_REGS2_END (OMAP3630_ISP_CSI2A_REGS2_BASE + 0x3F) | ||
| 79 | #define OMAP3630_ISP_CSI2C_REGS1_END (OMAP3630_ISP_CSI2C_REGS1_BASE + 0x16F) | ||
| 80 | #define OMAP3630_ISP_CSIPHY1_END (OMAP3630_ISP_CSIPHY1_BASE + 0x00B) | ||
| 81 | #define OMAP3630_ISP_CSI2C_REGS2_END (OMAP3630_ISP_CSI2C_REGS2_BASE + 0x3F) | ||
| 82 | 52 | ||
| 83 | #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) | 53 | #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) |
| 84 | #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) | 54 | #define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000) |