diff options
author | Felipe Balbi <balbi@ti.com> | 2014-09-08 20:54:32 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2014-09-11 16:03:33 -0400 |
commit | 71be00c90aba446779ea35a9740973a9be594257 (patch) | |
tree | 3666ccee0c0a3385d231a629f2cf514fa508206a /arch/arm/mach-omap2 | |
parent | 33c7c7b7f2eb76520cd8ddcb7fe458383783e0f8 (diff) |
arm: omap: irq: start to remove irq_banks array
We have a single bank in that array, this patch
is in preparation to remove that array. It just
shifts everything to a new set of functions
for register IO while also removing old ones.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r-- | arch/arm/mach-omap2/irq.c | 64 |
1 files changed, 27 insertions, 37 deletions
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index bae03290cad4..652c15bff176 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c | |||
@@ -82,21 +82,20 @@ struct omap3_intc_regs { | |||
82 | }; | 82 | }; |
83 | 83 | ||
84 | /* INTC bank register get/set */ | 84 | /* INTC bank register get/set */ |
85 | 85 | static void intc_writel(u32 reg, u32 val) | |
86 | static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg) | ||
87 | { | 86 | { |
88 | writel_relaxed(val, bank->base_reg + reg); | 87 | writel_relaxed(val, omap_irq_base + reg); |
89 | } | 88 | } |
90 | 89 | ||
91 | static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg) | 90 | static u32 intc_readl(u32 reg) |
92 | { | 91 | { |
93 | return readl_relaxed(bank->base_reg + reg); | 92 | return readl_relaxed(omap_irq_base + reg); |
94 | } | 93 | } |
95 | 94 | ||
96 | /* XXX: FIQ and additional INTC support (only MPU at the moment) */ | 95 | /* XXX: FIQ and additional INTC support (only MPU at the moment) */ |
97 | static void omap_ack_irq(struct irq_data *d) | 96 | static void omap_ack_irq(struct irq_data *d) |
98 | { | 97 | { |
99 | intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL); | 98 | intc_writel(INTC_CONTROL, 0x1); |
100 | } | 99 | } |
101 | 100 | ||
102 | static void omap_mask_ack_irq(struct irq_data *d) | 101 | static void omap_mask_ack_irq(struct irq_data *d) |
@@ -109,19 +108,19 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank) | |||
109 | { | 108 | { |
110 | unsigned long tmp; | 109 | unsigned long tmp; |
111 | 110 | ||
112 | tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff; | 111 | tmp = intc_readl(INTC_REVISION) & 0xff; |
113 | pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", | 112 | pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", |
114 | bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); | 113 | bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); |
115 | 114 | ||
116 | tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG); | 115 | tmp = intc_readl(INTC_SYSCONFIG); |
117 | tmp |= 1 << 1; /* soft reset */ | 116 | tmp |= 1 << 1; /* soft reset */ |
118 | intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG); | 117 | intc_writel(INTC_SYSCONFIG, tmp); |
119 | 118 | ||
120 | while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1)) | 119 | while (!(intc_readl(INTC_SYSSTATUS) & 0x1)) |
121 | /* Wait for reset to complete */; | 120 | /* Wait for reset to complete */; |
122 | 121 | ||
123 | /* Enable autoidle */ | 122 | /* Enable autoidle */ |
124 | intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG); | 123 | intc_writel(INTC_SYSCONFIG, 1 << 0); |
125 | } | 124 | } |
126 | 125 | ||
127 | int omap_irq_pending(void) | 126 | int omap_irq_pending(void) |
@@ -133,7 +132,7 @@ int omap_irq_pending(void) | |||
133 | int irq; | 132 | int irq; |
134 | 133 | ||
135 | for (irq = 0; irq < bank->nr_irqs; irq += 32) | 134 | for (irq = 0; irq < bank->nr_irqs; irq += 32) |
136 | if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 + | 135 | if (intc_readl(INTC_PENDING_IRQ0 + |
137 | ((irq >> 5) << 5))) | 136 | ((irq >> 5) << 5))) |
138 | return 1; | 137 | return 1; |
139 | } | 138 | } |
@@ -307,22 +306,20 @@ void omap_intc_save_context(void) | |||
307 | { | 306 | { |
308 | int ind = 0, i = 0; | 307 | int ind = 0, i = 0; |
309 | for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) { | 308 | for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) { |
310 | struct omap_irq_bank *bank = irq_banks + ind; | ||
311 | intc_context[ind].sysconfig = | 309 | intc_context[ind].sysconfig = |
312 | intc_bank_read_reg(bank, INTC_SYSCONFIG); | 310 | intc_readl(INTC_SYSCONFIG); |
313 | intc_context[ind].protection = | 311 | intc_context[ind].protection = |
314 | intc_bank_read_reg(bank, INTC_PROTECTION); | 312 | intc_readl(INTC_PROTECTION); |
315 | intc_context[ind].idle = | 313 | intc_context[ind].idle = |
316 | intc_bank_read_reg(bank, INTC_IDLE); | 314 | intc_readl(INTC_IDLE); |
317 | intc_context[ind].threshold = | 315 | intc_context[ind].threshold = |
318 | intc_bank_read_reg(bank, INTC_THRESHOLD); | 316 | intc_readl(INTC_THRESHOLD); |
319 | for (i = 0; i < INTCPS_NR_IRQS; i++) | 317 | for (i = 0; i < INTCPS_NR_IRQS; i++) |
320 | intc_context[ind].ilr[i] = | 318 | intc_context[ind].ilr[i] = |
321 | intc_bank_read_reg(bank, (0x100 + 0x4*i)); | 319 | intc_readl((INTC_ILR0 + 0x4 * i)); |
322 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | 320 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) |
323 | intc_context[ind].mir[i] = | 321 | intc_context[ind].mir[i] = |
324 | intc_bank_read_reg(&irq_banks[0], INTC_MIR0 + | 322 | intc_readl(INTC_MIR0 + (0x20 * i)); |
325 | (0x20 * i)); | ||
326 | } | 323 | } |
327 | } | 324 | } |
328 | 325 | ||
@@ -331,23 +328,16 @@ void omap_intc_restore_context(void) | |||
331 | int ind = 0, i = 0; | 328 | int ind = 0, i = 0; |
332 | 329 | ||
333 | for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) { | 330 | for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) { |
334 | struct omap_irq_bank *bank = irq_banks + ind; | 331 | intc_writel(INTC_SYSCONFIG, intc_context[ind].sysconfig); |
335 | intc_bank_write_reg(intc_context[ind].sysconfig, | 332 | intc_writel(INTC_PROTECTION, intc_context[ind].protection); |
336 | bank, INTC_SYSCONFIG); | 333 | intc_writel(INTC_IDLE, intc_context[ind].idle); |
337 | intc_bank_write_reg(intc_context[ind].sysconfig, | 334 | intc_writel(INTC_THRESHOLD, intc_context[ind].threshold); |
338 | bank, INTC_SYSCONFIG); | ||
339 | intc_bank_write_reg(intc_context[ind].protection, | ||
340 | bank, INTC_PROTECTION); | ||
341 | intc_bank_write_reg(intc_context[ind].idle, | ||
342 | bank, INTC_IDLE); | ||
343 | intc_bank_write_reg(intc_context[ind].threshold, | ||
344 | bank, INTC_THRESHOLD); | ||
345 | for (i = 0; i < INTCPS_NR_IRQS; i++) | 335 | for (i = 0; i < INTCPS_NR_IRQS; i++) |
346 | intc_bank_write_reg(intc_context[ind].ilr[i], | 336 | intc_writel(INTC_ILR0 + 0x4 * i, |
347 | bank, (0x100 + 0x4*i)); | 337 | intc_context[ind].ilr[i]); |
348 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) | 338 | for (i = 0; i < INTCPS_NR_MIR_REGS; i++) |
349 | intc_bank_write_reg(intc_context[ind].mir[i], | 339 | intc_writel(INTC_MIR0 + 0x20 * i, |
350 | &irq_banks[0], INTC_MIR0 + (0x20 * i)); | 340 | intc_context[ind].mir[i]); |
351 | } | 341 | } |
352 | /* MIRs are saved and restore with other PRCM registers */ | 342 | /* MIRs are saved and restore with other PRCM registers */ |
353 | } | 343 | } |
@@ -364,13 +354,13 @@ void omap3_intc_prepare_idle(void) | |||
364 | * Disable autoidle as it can stall interrupt controller, | 354 | * Disable autoidle as it can stall interrupt controller, |
365 | * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) | 355 | * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) |
366 | */ | 356 | */ |
367 | intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG); | 357 | intc_writel(INTC_SYSCONFIG, 0); |
368 | } | 358 | } |
369 | 359 | ||
370 | void omap3_intc_resume_idle(void) | 360 | void omap3_intc_resume_idle(void) |
371 | { | 361 | { |
372 | /* Re-enable autoidle */ | 362 | /* Re-enable autoidle */ |
373 | intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG); | 363 | intc_writel(INTC_SYSCONFIG, 1); |
374 | } | 364 | } |
375 | 365 | ||
376 | asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs) | 366 | asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs) |