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authorAdrian Hunter <adrian.hunter@nokia.com>2009-06-23 06:30:24 -0400
committerTony Lindgren <tony@atomide.com>2009-06-23 06:30:24 -0400
commit6d453e84b587f38e4197bb2c6a37296c4a80cbac (patch)
tree0b9e47364aa85d08b09ccedfbd0a02ae96c6fd54 /arch/arm/mach-omap2
parentaecedb94b366d6fb5e2a17ca18a5dc78e593198e (diff)
OMAP2/3: gpmc-onenand: correct use of async timings
Use async timings when sync timings are not requested. Also ensure that OneNAND is in async mode when async timings are used. Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c21
1 files changed, 19 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 2fd22f9c5f0e..54fec53a48e7 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -31,6 +31,8 @@ static struct platform_device gpmc_onenand_device = {
31static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) 31static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
32{ 32{
33 struct gpmc_timings t; 33 struct gpmc_timings t;
34 u32 reg;
35 int err;
34 36
35 const int t_cer = 15; 37 const int t_cer = 15;
36 const int t_avdp = 12; 38 const int t_avdp = 12;
@@ -43,6 +45,11 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
43 const int t_wpl = 40; 45 const int t_wpl = 40;
44 const int t_wph = 30; 46 const int t_wph = 30;
45 47
48 /* Ensure sync read and sync write are disabled */
49 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
50 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
51 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
52
46 memset(&t, 0, sizeof(t)); 53 memset(&t, 0, sizeof(t));
47 t.sync_clk = 0; 54 t.sync_clk = 0;
48 t.cs_on = 0; 55 t.cs_on = 0;
@@ -74,7 +81,16 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
74 GPMC_CONFIG1_DEVICESIZE_16 | 81 GPMC_CONFIG1_DEVICESIZE_16 |
75 GPMC_CONFIG1_MUXADDDATA); 82 GPMC_CONFIG1_MUXADDDATA);
76 83
77 return gpmc_cs_set_timings(cs, &t); 84 err = gpmc_cs_set_timings(cs, &t);
85 if (err)
86 return err;
87
88 /* Ensure sync read and sync write are disabled */
89 reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
90 reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
91 writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
92
93 return 0;
78} 94}
79 95
80static void set_onenand_cfg(void __iomem *onenand_base, int latency, 96static void set_onenand_cfg(void __iomem *onenand_base, int latency,
@@ -124,7 +140,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
124 } else if (cfg->flags & ONENAND_SYNC_READWRITE) { 140 } else if (cfg->flags & ONENAND_SYNC_READWRITE) {
125 sync_read = 1; 141 sync_read = 1;
126 sync_write = 1; 142 sync_write = 1;
127 } 143 } else
144 return omap2_onenand_set_async_mode(cs, onenand_base);
128 145
129 if (!freq) { 146 if (!freq) {
130 /* Very first call freq is not known */ 147 /* Very first call freq is not known */