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authorOlof Johansson <olof@lixom.net>2013-02-12 18:32:50 -0500
committerOlof Johansson <olof@lixom.net>2013-02-12 18:32:50 -0500
commit379095930b0383e48be6da308e041aca8860c72d (patch)
tree429b26a02d9e931dc3760920e258149ac0f8bca1 /arch/arm/mach-omap2
parent0a0db4a1e4c6dfd93411a4425b9f068f0da752c1 (diff)
parent25e4d0f6df356ec7c2a09f6744c36a84b5537f33 (diff)
Merge tag 'omap-for-v3.9/pm-wfi-take2-signed-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into late/omap
From Tony Lindgren: omap pm wfi changes via Paul Walmsley <paul@pwsan.com>: On OMAP2+ devices, standardize and clean up WFI entry and WFI blocking. Basic test logs are available here: http://www.pwsan.com/omap/testlogs/wfi_devel_a_3.9/20130208085027/ Conflicts: arch/arm/mach-omap2/pm24xx.c Note that this is based on earlier omap-for-v3.9/pm-signed because of a non-trivial merge conflict. This branch also contains a fix for c1d1cd59 ("ARM: OMAP2+: omap_device: remove obsolete pm_lats and early_device code"). * tag 'omap-for-v3.9/pm-wfi-take2-signed-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (25 commits) ARM: OMAP2+: fix some omap_device_build() calls that aren't compiled by default ARM: OMAP AM3517/05: hwmod data: block WFI when EMAC active ARM: OMAP2420: hwmod data/PM: use hwmod to block WFI when I2C active ARM: OMAP2+: hwmod: add support for blocking WFI when a device is active ARM: OMAP2xxx: PM: enter WFI via inline asm if CORE stays active ARM: OMAP2+: powerdomain: fix whitespace, improve flag comments ARM: OMAP2+: clockdomain: convert existing atomic usecounts into spinlock-protected shorts/ints ARM: OMAP2+: clockdomain: work on wkdep/sleepdep functions ARM: OMAP2xxx: CM: remove autodep handling ARM: OMAP2+: powerdomain/clockdomain: add a per-powerdomain spinlock ARM: OMAP2+: PM/powerdomain: move omap_set_pwrdm_state() to powerdomain code ARM: OMAP2: PM/powerdomain: drop unnecessary pwrdm_wait_transition() ARM: OMAP2xxx: PM: clean up some crufty powerstate programming code ARM: OMAP2+: clockdomain: add pwrdm_state_switch() call to clkdm_sleep() ARM: OMAP2+: powerdomain: fix powerdomain trace integration ARM: OMAP4: MPUSS PM: remove unnecessary shim functions for powerdomain control ARM: OMAP3xxx: CPUIdle: optimize __omap3_enter_idle() ARM: OMAP2420: hwmod data/PM: use hwmod to block WFI when I2C active ARM: OMAP2+: hwmod: add support for blocking WFI when a device is active ARM: OMAP3xxx: CPUIdle: simplify the PER next-state code ...
Diffstat (limited to 'arch/arm/mach-omap2')
-rw-r--r--arch/arm/mach-omap2/am35xx-emac.c3
-rw-r--r--arch/arm/mach-omap2/cclock2420_data.c16
-rw-r--r--arch/arm/mach-omap2/cclock2430_data.c16
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c578
-rw-r--r--arch/arm/mach-omap2/clockdomain.c569
-rw-r--r--arch/arm/mach-omap2/clockdomain.h17
-rw-r--r--arch/arm/mach-omap2/cm2xxx.c33
-rw-r--r--arch/arm/mach-omap2/cm3xxx.c14
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c2
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c79
-rw-r--r--arch/arm/mach-omap2/devices.c25
-rw-r--r--arch/arm/mach-omap2/display.c2
-rw-r--r--arch/arm/mach-omap2/dma.c2
-rw-r--r--arch/arm/mach-omap2/drm.c3
-rw-r--r--arch/arm/mach-omap2/gpio.c3
-rw-r--r--arch/arm/mach-omap2/gpmc.c2
-rw-r--r--arch/arm/mach-omap2/hdq1w.c2
-rw-r--r--arch/arm/mach-omap2/hsmmc.c2
-rw-r--r--arch/arm/mach-omap2/hwspinlock.c3
-rw-r--r--arch/arm/mach-omap2/i2c.c3
-rw-r--r--arch/arm/mach-omap2/mcbsp.c2
-rw-r--r--arch/arm/mach-omap2/msdi.c2
-rw-r--r--arch/arm/mach-omap2/omap-iommu.c3
-rw-r--r--arch/arm/mach-omap2/omap-mpuss-lowpower.c44
-rw-r--r--arch/arm/mach-omap2/omap_device.c537
-rw-r--r--arch/arm/mach-omap2/omap_device.h79
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c8
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h9
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c7
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c7
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c99
-rw-r--r--arch/arm/mach-omap2/pm-debug.c6
-rw-r--r--arch/arm/mach-omap2/pm.c69
-rw-r--r--arch/arm/mach-omap2/pm.h1
-rw-r--r--arch/arm/mach-omap2/pm24xx.c53
-rw-r--r--arch/arm/mach-omap2/pmu.c3
-rw-r--r--arch/arm/mach-omap2/powerdomain.c232
-rw-r--r--arch/arm/mach-omap2/powerdomain.h52
-rw-r--r--arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c4
-rw-r--r--arch/arm/mach-omap2/powerdomains2xxx_data.c9
-rw-r--r--arch/arm/mach-omap2/powerdomains3xxx_data.c44
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.c3
-rw-r--r--arch/arm/mach-omap2/serial.c3
-rw-r--r--arch/arm/mach-omap2/sleep24xx.S19
-rw-r--r--arch/arm/mach-omap2/sr_device.c3
-rw-r--r--arch/arm/mach-omap2/timer.c3
-rw-r--r--arch/arm/mach-omap2/usb-host.c16
-rw-r--r--arch/arm/mach-omap2/usb-musb.c2
-rw-r--r--arch/arm/mach-omap2/wd_timer.c3
49 files changed, 1013 insertions, 1683 deletions
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index af11dcdb7e2c..25b79a297365 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -62,8 +62,7 @@ static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh,
62{ 62{
63 struct platform_device *pdev; 63 struct platform_device *pdev;
64 64
65 pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len, 65 pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len);
66 NULL, 0, false);
67 if (IS_ERR(pdev)) { 66 if (IS_ERR(pdev)) {
68 WARN(1, "Can't build omap_device for %s:%s.\n", 67 WARN(1, "Can't build omap_device for %s:%s.\n",
69 oh->class->name, oh->name); 68 oh->class->name, oh->name);
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
index ab7e952d2070..0f0a97c1fcc0 100644
--- a/arch/arm/mach-omap2/cclock2420_data.c
+++ b/arch/arm/mach-omap2/cclock2420_data.c
@@ -622,15 +622,10 @@ static struct clk_hw_omap gpios_fck_hw = {
622 622
623DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops); 623DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
624 624
625static struct clk wu_l4_ick;
626
627DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
628DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
629
630static struct clk gpios_ick; 625static struct clk gpios_ick;
631 626
632static const char *gpios_ick_parent_names[] = { 627static const char *gpios_ick_parent_names[] = {
633 "wu_l4_ick", 628 "sys_ck",
634}; 629};
635 630
636static struct clk_hw_omap gpios_ick_hw = { 631static struct clk_hw_omap gpios_ick_hw = {
@@ -1682,13 +1677,6 @@ static struct clk_hw_omap wdt1_ick_hw = {
1682 1677
1683DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); 1678DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
1684 1679
1685static struct clk wdt1_osc_ck;
1686
1687static const struct clk_ops wdt1_osc_ck_ops = {};
1688
1689DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
1690DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
1691
1692static struct clk wdt3_fck; 1680static struct clk wdt3_fck;
1693 1681
1694static struct clk_hw_omap wdt3_fck_hw = { 1682static struct clk_hw_omap wdt3_fck_hw = {
@@ -1767,7 +1755,6 @@ static struct omap_clk omap2420_clks[] = {
1767 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), 1755 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X),
1768 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), 1756 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X),
1769 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), 1757 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X),
1770 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_242X),
1771 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X), 1758 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_242X),
1772 CLK(NULL, "sys_clkout", &sys_clkout, CK_242X), 1759 CLK(NULL, "sys_clkout", &sys_clkout, CK_242X),
1773 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), 1760 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X),
@@ -1797,7 +1784,6 @@ static struct omap_clk omap2420_clks[] = {
1797 /* L4 domain clocks */ 1784 /* L4 domain clocks */
1798 CLK(NULL, "l4_ck", &l4_ck, CK_242X), 1785 CLK(NULL, "l4_ck", &l4_ck, CK_242X),
1799 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X), 1786 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_242X),
1800 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_242X),
1801 /* virtual meta-group clock */ 1787 /* virtual meta-group clock */
1802 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X), 1788 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_242X),
1803 /* general l4 interface ck, multi-parent functional clk */ 1789 /* general l4 interface ck, multi-parent functional clk */
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
index eb3dab68d536..aed8f74ca076 100644
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -601,15 +601,10 @@ static struct clk_hw_omap gpios_fck_hw = {
601 601
602DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops); 602DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops);
603 603
604static struct clk wu_l4_ick;
605
606DEFINE_STRUCT_CLK_HW_OMAP(wu_l4_ick, "wkup_clkdm");
607DEFINE_STRUCT_CLK(wu_l4_ick, dpll_ck_parent_names, core_ck_ops);
608
609static struct clk gpios_ick; 604static struct clk gpios_ick;
610 605
611static const char *gpios_ick_parent_names[] = { 606static const char *gpios_ick_parent_names[] = {
612 "wu_l4_ick", 607 "sys_ck",
613}; 608};
614 609
615static struct clk_hw_omap gpios_ick_hw = { 610static struct clk_hw_omap gpios_ick_hw = {
@@ -1811,13 +1806,6 @@ static struct clk_hw_omap wdt1_ick_hw = {
1811 1806
1812DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops); 1807DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
1813 1808
1814static struct clk wdt1_osc_ck;
1815
1816static const struct clk_ops wdt1_osc_ck_ops = {};
1817
1818DEFINE_STRUCT_CLK_HW_OMAP(wdt1_osc_ck, NULL);
1819DEFINE_STRUCT_CLK(wdt1_osc_ck, sys_ck_parent_names, wdt1_osc_ck_ops);
1820
1821static struct clk wdt4_fck; 1809static struct clk wdt4_fck;
1822 1810
1823static struct clk_hw_omap wdt4_fck_hw = { 1811static struct clk_hw_omap wdt4_fck_hw = {
@@ -1869,7 +1857,6 @@ static struct omap_clk omap2430_clks[] = {
1869 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), 1857 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
1870 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), 1858 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
1871 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), 1859 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
1872 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
1873 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X), 1860 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
1874 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X), 1861 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
1875 CLK(NULL, "emul_ck", &emul_ck, CK_243X), 1862 CLK(NULL, "emul_ck", &emul_ck, CK_243X),
@@ -1898,7 +1885,6 @@ static struct omap_clk omap2430_clks[] = {
1898 /* L4 domain clocks */ 1885 /* L4 domain clocks */
1899 CLK(NULL, "l4_ck", &l4_ck, CK_243X), 1886 CLK(NULL, "l4_ck", &l4_ck, CK_243X),
1900 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X), 1887 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
1901 CLK(NULL, "wu_l4_ick", &wu_l4_ick, CK_243X),
1902 /* virtual meta-group clock */ 1888 /* virtual meta-group clock */
1903 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X), 1889 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
1904 /* general l4 interface ck, multi-parent functional clk */ 1890 /* general l4 interface ck, multi-parent functional clk */
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index a2cc046b47f4..cebe2b31943e 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -16,6 +16,10 @@
16 * XXX Some of the ES1 clocks have been removed/changed; once support 16 * XXX Some of the ES1 clocks have been removed/changed; once support
17 * is added for discriminating clocks by ES level, these should be added back 17 * is added for discriminating clocks by ES level, these should be added back
18 * in. 18 * in.
19 *
20 * XXX All of the remaining MODULEMODE clock nodes should be removed
21 * once the drivers are updated to use pm_runtime or to use the appropriate
22 * upstream clock node for rate/parent selection.
19 */ 23 */
20 24
21#include <linux/kernel.h> 25#include <linux/kernel.h>
@@ -315,7 +319,7 @@ DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
315 OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, 319 OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
316 OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); 320 OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
317 321
318static const struct clk_ops dmic_fck_ops = { 322static const struct clk_ops dpll_hsd_ops = {
319 .enable = &omap2_dflt_clk_enable, 323 .enable = &omap2_dflt_clk_enable,
320 .disable = &omap2_dflt_clk_disable, 324 .disable = &omap2_dflt_clk_disable,
321 .is_enabled = &omap2_dflt_clk_is_enabled, 325 .is_enabled = &omap2_dflt_clk_is_enabled,
@@ -325,6 +329,12 @@ static const struct clk_ops dmic_fck_ops = {
325 .init = &omap2_init_clk_clkdm, 329 .init = &omap2_init_clk_clkdm,
326}; 330};
327 331
332static const struct clk_ops func_dmic_abe_gfclk_ops = {
333 .recalc_rate = &omap2_clksel_recalc,
334 .get_parent = &omap2_clksel_find_parent_index,
335 .set_parent = &omap2_clksel_set_parent,
336};
337
328static const char *dpll_core_m3x2_ck_parents[] = { 338static const char *dpll_core_m3x2_ck_parents[] = {
329 "dpll_core_x2_ck", 339 "dpll_core_x2_ck",
330}; 340};
@@ -340,7 +350,7 @@ DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
340 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 350 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
341 OMAP4430_CM_DIV_M3_DPLL_CORE, 351 OMAP4430_CM_DIV_M3_DPLL_CORE,
342 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, 352 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
343 dpll_core_m3x2_ck_parents, dmic_fck_ops); 353 dpll_core_m3x2_ck_parents, dpll_hsd_ops);
344 354
345DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck", 355DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
346 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE, 356 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
@@ -547,7 +557,7 @@ DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
547 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 557 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
548 OMAP4430_CM_DIV_M3_DPLL_PER, 558 OMAP4430_CM_DIV_M3_DPLL_PER,
549 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, 559 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
550 dpll_per_m3x2_ck_parents, dmic_fck_ops); 560 dpll_per_m3x2_ck_parents, dpll_hsd_ops);
551 561
552DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 562DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
553 0x0, OMAP4430_CM_DIV_M4_DPLL_PER, 563 0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
@@ -749,10 +759,6 @@ DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
749 OMAP4430_CM_L4SEC_AES2_CLKCTRL, 759 OMAP4430_CM_L4SEC_AES2_CLKCTRL,
750 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 760 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
751 761
752DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0,
753 OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
754 0x0, NULL);
755
756DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0, 762DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
757 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, 763 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
758 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL); 764 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
@@ -774,11 +780,6 @@ DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
774 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, 780 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
775 0x0, NULL); 781 0x0, NULL);
776 782
777DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0,
778 OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
779 OMAP4430_MODULEMODE_SWCTRL_SHIFT,
780 0x0, NULL);
781
782static const char *dmic_sync_mux_ck_parents[] = { 783static const char *dmic_sync_mux_ck_parents[] = {
783 "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk", 784 "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
784}; 785};
@@ -795,23 +796,13 @@ static const struct clksel func_dmic_abe_gfclk_sel[] = {
795 { .parent = NULL }, 796 { .parent = NULL },
796}; 797};
797 798
798static const char *dmic_fck_parents[] = { 799static const char *func_dmic_abe_gfclk_parents[] = {
799 "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk", 800 "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
800}; 801};
801 802
802/* Merged func_dmic_abe_gfclk into dmic */ 803DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
803static struct clk dmic_fck; 804 OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
804 805 func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
805DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel,
806 OMAP4430_CM1_ABE_DMIC_CLKCTRL,
807 OMAP4430_CLKSEL_SOURCE_MASK,
808 OMAP4430_CM1_ABE_DMIC_CLKCTRL,
809 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
810 dmic_fck_parents, dmic_fck_ops);
811
812DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0,
813 OMAP4430_CM_TESLA_TESLA_CLKCTRL,
814 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
815 806
816DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0, 807DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
817 OMAP4430_CM_DSS_DSS_CLKCTRL, 808 OMAP4430_CM_DSS_DSS_CLKCTRL,
@@ -833,177 +824,57 @@ DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
833 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, 824 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
834 0x0, NULL); 825 0x0, NULL);
835 826
836DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
837 OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
838 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
839
840DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
841 OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
842 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
843
844DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
845 OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
846 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
847
848DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, 827DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
849 OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT, 828 OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
850 OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); 829 OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
851 830
852DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0,
853 OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
854 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
855
856DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 831DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
857 OMAP4430_CM_WKUP_GPIO1_CLKCTRL, 832 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
858 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); 833 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
859 834
860DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0,
861 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
862 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
863
864DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 835DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
865 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 836 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
866 0x0, NULL); 837 0x0, NULL);
867 838
868DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0,
869 OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
870 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
871
872DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 839DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
873 OMAP4430_CM_L4PER_GPIO3_CLKCTRL, 840 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
874 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); 841 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
875 842
876DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0,
877 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
878 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
879
880DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 843DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
881 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 844 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
882 0x0, NULL); 845 0x0, NULL);
883 846
884DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0,
885 OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
886 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
887
888DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 847DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
889 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 848 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
890 0x0, NULL); 849 0x0, NULL);
891 850
892DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0,
893 OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
894 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
895
896DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 851DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
897 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 852 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
898 0x0, NULL); 853 0x0, NULL);
899 854
900DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0,
901 OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
902 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
903
904DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0,
905 OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
906 0x0, NULL);
907
908static const struct clksel sgx_clk_mux_sel[] = { 855static const struct clksel sgx_clk_mux_sel[] = {
909 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, 856 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
910 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, 857 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
911 { .parent = NULL }, 858 { .parent = NULL },
912}; 859};
913 860
914static const char *gpu_fck_parents[] = { 861static const char *sgx_clk_mux_parents[] = {
915 "dpll_core_m7x2_ck", "dpll_per_m7x2_ck", 862 "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
916}; 863};
917 864
918/* Merged sgx_clk_mux into gpu */ 865DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
919DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel, 866 OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
920 OMAP4430_CM_GFX_GFX_CLKCTRL, 867 sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
921 OMAP4430_CLKSEL_SGX_FCLK_MASK,
922 OMAP4430_CM_GFX_GFX_CLKCTRL,
923 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
924 gpu_fck_parents, dmic_fck_ops);
925
926DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0,
927 OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
928 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
929 868
930DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, 869DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
931 OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT, 870 OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
932 OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO, 871 OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
933 NULL); 872 NULL);
934 873
935DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
936 OMAP4430_CM_L4PER_I2C1_CLKCTRL,
937 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
938
939DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
940 OMAP4430_CM_L4PER_I2C2_CLKCTRL,
941 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
942
943DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
944 OMAP4430_CM_L4PER_I2C3_CLKCTRL,
945 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
946
947DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
948 OMAP4430_CM_L4PER_I2C4_CLKCTRL,
949 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
950
951DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
952 OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
953 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
954
955DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0, 874DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
956 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, 875 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
957 0x0, NULL); 876 0x0, NULL);
958 877
959DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
960 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
961 0x0, NULL);
962
963DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
964 OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
965 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
966
967DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
968 OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
969 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
970
971static struct clk l3_instr_ick;
972
973static const char *l3_instr_ick_parent_names[] = {
974 "l3_div_ck",
975};
976
977static const struct clk_ops l3_instr_ick_ops = {
978 .enable = &omap2_dflt_clk_enable,
979 .disable = &omap2_dflt_clk_disable,
980 .is_enabled = &omap2_dflt_clk_is_enabled,
981 .init = &omap2_init_clk_clkdm,
982};
983
984static struct clk_hw_omap l3_instr_ick_hw = {
985 .hw = {
986 .clk = &l3_instr_ick,
987 },
988 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
989 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
990 .clkdm_name = "l3_instr_clkdm",
991};
992
993DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
994
995static struct clk l3_main_3_ick;
996static struct clk_hw_omap l3_main_3_ick_hw = {
997 .hw = {
998 .clk = &l3_main_3_ick,
999 },
1000 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1001 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1002 .clkdm_name = "l3_instr_clkdm",
1003};
1004
1005DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
1006
1007DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, 878DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1008 OMAP4430_CM1_ABE_MCASP_CLKCTRL, 879 OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1009 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, 880 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
@@ -1016,17 +887,13 @@ static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1016 { .parent = NULL }, 887 { .parent = NULL },
1017}; 888};
1018 889
1019static const char *mcasp_fck_parents[] = { 890static const char *func_mcasp_abe_gfclk_parents[] = {
1020 "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk", 891 "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1021}; 892};
1022 893
1023/* Merged func_mcasp_abe_gfclk into mcasp */ 894DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
1024DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel, 895 OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
1025 OMAP4430_CM1_ABE_MCASP_CLKCTRL, 896 func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
1026 OMAP4430_CLKSEL_SOURCE_MASK,
1027 OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1028 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1029 mcasp_fck_parents, dmic_fck_ops);
1030 897
1031DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, 898DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1032 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, 899 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
@@ -1040,17 +907,14 @@ static const struct clksel func_mcbsp1_gfclk_sel[] = {
1040 { .parent = NULL }, 907 { .parent = NULL },
1041}; 908};
1042 909
1043static const char *mcbsp1_fck_parents[] = { 910static const char *func_mcbsp1_gfclk_parents[] = {
1044 "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk", 911 "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1045}; 912};
1046 913
1047/* Merged func_mcbsp1_gfclk into mcbsp1 */ 914DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
1048DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel, 915 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1049 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, 916 OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
1050 OMAP4430_CLKSEL_SOURCE_MASK, 917 func_dmic_abe_gfclk_ops);
1051 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1052 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1053 mcbsp1_fck_parents, dmic_fck_ops);
1054 918
1055DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, 919DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1056 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, 920 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
@@ -1064,17 +928,14 @@ static const struct clksel func_mcbsp2_gfclk_sel[] = {
1064 { .parent = NULL }, 928 { .parent = NULL },
1065}; 929};
1066 930
1067static const char *mcbsp2_fck_parents[] = { 931static const char *func_mcbsp2_gfclk_parents[] = {
1068 "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk", 932 "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1069}; 933};
1070 934
1071/* Merged func_mcbsp2_gfclk into mcbsp2 */ 935DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
1072DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel, 936 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1073 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, 937 OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
1074 OMAP4430_CLKSEL_SOURCE_MASK, 938 func_dmic_abe_gfclk_ops);
1075 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1076 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1077 mcbsp2_fck_parents, dmic_fck_ops);
1078 939
1079DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, 940DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1080 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, 941 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
@@ -1088,17 +949,14 @@ static const struct clksel func_mcbsp3_gfclk_sel[] = {
1088 { .parent = NULL }, 949 { .parent = NULL },
1089}; 950};
1090 951
1091static const char *mcbsp3_fck_parents[] = { 952static const char *func_mcbsp3_gfclk_parents[] = {
1092 "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk", 953 "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1093}; 954};
1094 955
1095/* Merged func_mcbsp3_gfclk into mcbsp3 */ 956DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
1096DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel, 957 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1097 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, 958 OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
1098 OMAP4430_CLKSEL_SOURCE_MASK, 959 func_dmic_abe_gfclk_ops);
1099 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1100 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1101 mcbsp3_fck_parents, dmic_fck_ops);
1102 960
1103static const char *mcbsp4_sync_mux_ck_parents[] = { 961static const char *mcbsp4_sync_mux_ck_parents[] = {
1104 "func_96m_fclk", "per_abe_nc_fclk", 962 "func_96m_fclk", "per_abe_nc_fclk",
@@ -1115,37 +973,14 @@ static const struct clksel per_mcbsp4_gfclk_sel[] = {
1115 { .parent = NULL }, 973 { .parent = NULL },
1116}; 974};
1117 975
1118static const char *mcbsp4_fck_parents[] = { 976static const char *per_mcbsp4_gfclk_parents[] = {
1119 "mcbsp4_sync_mux_ck", "pad_clks_ck", 977 "mcbsp4_sync_mux_ck", "pad_clks_ck",
1120}; 978};
1121 979
1122/* Merged per_mcbsp4_gfclk into mcbsp4 */ 980DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
1123DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel, 981 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1124 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, 982 OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
1125 OMAP4430_CLKSEL_SOURCE_24_24_MASK, 983 func_dmic_abe_gfclk_ops);
1126 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1127 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1128 mcbsp4_fck_parents, dmic_fck_ops);
1129
1130DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0,
1131 OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1132 0x0, NULL);
1133
1134DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1135 OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1136 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1137
1138DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1139 OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1140 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1141
1142DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1143 OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1144 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1145
1146DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1147 OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
1148 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1149 984
1150static const struct clksel hsmmc1_fclk_sel[] = { 985static const struct clksel hsmmc1_fclk_sel[] = {
1151 { .parent = &func_64m_fclk, .rates = div_1_0_rates }, 986 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
@@ -1153,69 +988,22 @@ static const struct clksel hsmmc1_fclk_sel[] = {
1153 { .parent = NULL }, 988 { .parent = NULL },
1154}; 989};
1155 990
1156static const char *mmc1_fck_parents[] = { 991static const char *hsmmc1_fclk_parents[] = {
1157 "func_64m_fclk", "func_96m_fclk", 992 "func_64m_fclk", "func_96m_fclk",
1158}; 993};
1159 994
1160/* Merged hsmmc1_fclk into mmc1 */ 995DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
1161DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel, 996 OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1162 OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK, 997 hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
1163 OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
1164 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1165 mmc1_fck_parents, dmic_fck_ops);
1166
1167/* Merged hsmmc2_fclk into mmc2 */
1168DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
1169 OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1170 OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
1171 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1172 mmc1_fck_parents, dmic_fck_ops);
1173
1174DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1175 OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
1176 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1177
1178DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1179 OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
1180 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1181
1182DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1183 OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
1184 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1185
1186DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
1187 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1188 OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
1189
1190DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0,
1191 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1192 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1193
1194static struct clk ocp_wp_noc_ick;
1195
1196static struct clk_hw_omap ocp_wp_noc_ick_hw = {
1197 .hw = {
1198 .clk = &ocp_wp_noc_ick,
1199 },
1200 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
1201 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1202 .clkdm_name = "l3_instr_clkdm",
1203};
1204
1205DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
1206 998
1207DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0, 999DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
1208 OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, 1000 OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1209 0x0, NULL); 1001 hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
1210 1002
1211DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, 1003DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
1212 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, 1004 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
1213 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1005 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1214 1006
1215DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
1216 OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1217 0x0, NULL);
1218
1219DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0, 1007DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
1220 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, 1008 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1221 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL); 1009 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
@@ -1232,10 +1020,6 @@ DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
1232 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, 1020 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1233 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL); 1021 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
1234 1022
1235DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0,
1236 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1237 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1238
1239DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0, 1023DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
1240 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, 1024 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1241 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL); 1025 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
@@ -1249,10 +1033,6 @@ DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
1249 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, 1033 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1250 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL); 1034 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
1251 1035
1252DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0,
1253 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1254 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1255
1256DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 1036DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1257 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, 1037 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1258 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1038 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
@@ -1271,52 +1051,35 @@ static const struct clksel dmt1_clk_mux_sel[] = {
1271 { .parent = NULL }, 1051 { .parent = NULL },
1272}; 1052};
1273 1053
1274/* Merged dmt1_clk_mux into timer1 */ 1054DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
1275DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel, 1055 OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1276 OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK, 1056 abe_dpll_bypass_clk_mux_ck_parents,
1277 OMAP4430_CM_WKUP_TIMER1_CLKCTRL, 1057 func_dmic_abe_gfclk_ops);
1278 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, 1058
1279 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); 1059DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1280 1060 OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
1281/* Merged cm2_dm10_mux into timer10 */ 1061 abe_dpll_bypass_clk_mux_ck_parents,
1282DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel, 1062 func_dmic_abe_gfclk_ops);
1283 OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, 1063
1284 OMAP4430_CLKSEL_MASK, 1064DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1285 OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, 1065 OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
1286 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, 1066 abe_dpll_bypass_clk_mux_ck_parents,
1287 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); 1067 func_dmic_abe_gfclk_ops);
1288 1068
1289/* Merged cm2_dm11_mux into timer11 */ 1069DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1290DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel, 1070 OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1291 OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, 1071 abe_dpll_bypass_clk_mux_ck_parents,
1292 OMAP4430_CLKSEL_MASK, 1072 func_dmic_abe_gfclk_ops);
1293 OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, 1073
1294 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, 1074DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1295 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); 1075 OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
1296 1076 abe_dpll_bypass_clk_mux_ck_parents,
1297/* Merged cm2_dm2_mux into timer2 */ 1077 func_dmic_abe_gfclk_ops);
1298DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel, 1078
1299 OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, 1079DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1300 OMAP4430_CLKSEL_MASK, 1080 OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
1301 OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, 1081 abe_dpll_bypass_clk_mux_ck_parents,
1302 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, 1082 func_dmic_abe_gfclk_ops);
1303 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1304
1305/* Merged cm2_dm3_mux into timer3 */
1306DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1307 OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1308 OMAP4430_CLKSEL_MASK,
1309 OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1310 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1311 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1312
1313/* Merged cm2_dm4_mux into timer4 */
1314DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1315 OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1316 OMAP4430_CLKSEL_MASK,
1317 OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1318 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1319 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1320 1083
1321static const struct clksel timer5_sync_mux_sel[] = { 1084static const struct clksel timer5_sync_mux_sel[] = {
1322 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, 1085 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
@@ -1324,61 +1087,30 @@ static const struct clksel timer5_sync_mux_sel[] = {
1324 { .parent = NULL }, 1087 { .parent = NULL },
1325}; 1088};
1326 1089
1327static const char *timer5_fck_parents[] = { 1090static const char *timer5_sync_mux_parents[] = {
1328 "syc_clk_div_ck", "sys_32k_ck", 1091 "syc_clk_div_ck", "sys_32k_ck",
1329}; 1092};
1330 1093
1331/* Merged timer5_sync_mux into timer5 */ 1094DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1332DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel, 1095 OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
1333 OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK, 1096 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1334 OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1335 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1336 timer5_fck_parents, dmic_fck_ops);
1337
1338/* Merged timer6_sync_mux into timer6 */
1339DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel,
1340 OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
1341 OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1342 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1343 timer5_fck_parents, dmic_fck_ops);
1344
1345/* Merged timer7_sync_mux into timer7 */
1346DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel,
1347 OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
1348 OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1349 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1350 timer5_fck_parents, dmic_fck_ops);
1351
1352/* Merged timer8_sync_mux into timer8 */
1353DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel,
1354 OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
1355 OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1356 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1357 timer5_fck_parents, dmic_fck_ops);
1358
1359/* Merged cm2_dm9_mux into timer9 */
1360DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1361 OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1362 OMAP4430_CLKSEL_MASK,
1363 OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1364 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1365 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1366
1367DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1368 OMAP4430_CM_L4PER_UART1_CLKCTRL,
1369 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1370 1097
1371DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, 1098DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1372 OMAP4430_CM_L4PER_UART2_CLKCTRL, 1099 OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
1373 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1100 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1374 1101
1375DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, 1102DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1376 OMAP4430_CM_L4PER_UART3_CLKCTRL, 1103 OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
1377 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1104 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1378 1105
1379DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, 1106DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1380 OMAP4430_CM_L4PER_UART4_CLKCTRL, 1107 OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
1381 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1108 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1109
1110DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1111 OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
1112 abe_dpll_bypass_clk_mux_ck_parents,
1113 func_dmic_abe_gfclk_ops);
1382 1114
1383static struct clk usb_host_fs_fck; 1115static struct clk usb_host_fs_fck;
1384 1116
@@ -1512,18 +1244,6 @@ DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
1512 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT, 1244 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
1513 0x0, NULL); 1245 0x0, NULL);
1514 1246
1515DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1516 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1517 0x0, NULL);
1518
1519DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1520 OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1521 0x0, NULL);
1522
1523DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1524 OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1525 0x0, NULL);
1526
1527/* Remaining optional clocks */ 1247/* Remaining optional clocks */
1528static const char *pmd_stm_clock_mux_ck_parents[] = { 1248static const char *pmd_stm_clock_mux_ck_parents[] = {
1529 "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck", 1249 "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
@@ -1774,106 +1494,61 @@ static struct omap_clk omap44xx_clks[] = {
1774 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), 1494 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
1775 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), 1495 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
1776 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), 1496 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
1777 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
1778 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), 1497 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
1779 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), 1498 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
1780 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), 1499 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
1781 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
1782 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 1500 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
1783 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), 1501 CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk, CK_443X),
1784 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
1785 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), 1502 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
1786 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), 1503 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
1787 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), 1504 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
1788 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), 1505 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
1789 CLK(NULL, "dss_fck", &dss_fck, CK_443X), 1506 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
1790 CLK("omapdss_dss", "ick", &dss_fck, CK_443X), 1507 CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
1791 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
1792 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
1793 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
1794 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), 1508 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
1795 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
1796 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), 1509 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
1797 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
1798 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), 1510 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
1799 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
1800 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), 1511 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
1801 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
1802 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), 1512 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
1803 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
1804 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), 1513 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
1805 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
1806 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), 1514 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
1807 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), 1515 CLK(NULL, "sgx_clk_mux", &sgx_clk_mux, CK_443X),
1808 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
1809 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
1810 CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
1811 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), 1516 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
1812 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
1813 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
1814 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
1815 CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
1816 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
1817 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), 1517 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
1818 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
1819 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
1820 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
1821 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
1822 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
1823 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), 1518 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
1824 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), 1519 CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk, CK_443X),
1825 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), 1520 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
1826 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X), 1521 CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk, CK_443X),
1827 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), 1522 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
1828 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X), 1523 CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk, CK_443X),
1829 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), 1524 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
1830 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), 1525 CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk, CK_443X),
1831 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), 1526 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
1832 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), 1527 CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X),
1833 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), 1528 CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X),
1834 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X), 1529 CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X),
1835 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
1836 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
1837 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
1838 CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
1839 CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
1840 CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
1841 CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
1842 CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
1843 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
1844 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
1845 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
1846 CLK(NULL, "rng_ick", &rng_ick, CK_443X),
1847 CLK("omap_rng", "ick", &rng_ick, CK_443X),
1848 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), 1530 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
1849 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
1850 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), 1531 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
1851 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), 1532 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
1852 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), 1533 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
1853 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), 1534 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
1854 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
1855 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), 1535 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
1856 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), 1536 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
1857 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), 1537 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
1858 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
1859 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), 1538 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
1860 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), 1539 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
1861 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), 1540 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
1862 CLK(NULL, "timer1_fck", &timer1_fck, CK_443X), 1541 CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux, CK_443X),
1863 CLK(NULL, "timer10_fck", &timer10_fck, CK_443X), 1542 CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux, CK_443X),
1864 CLK(NULL, "timer11_fck", &timer11_fck, CK_443X), 1543 CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux, CK_443X),
1865 CLK(NULL, "timer2_fck", &timer2_fck, CK_443X), 1544 CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux, CK_443X),
1866 CLK(NULL, "timer3_fck", &timer3_fck, CK_443X), 1545 CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux, CK_443X),
1867 CLK(NULL, "timer4_fck", &timer4_fck, CK_443X), 1546 CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux, CK_443X),
1868 CLK(NULL, "timer5_fck", &timer5_fck, CK_443X), 1547 CLK(NULL, "timer5_sync_mux", &timer5_sync_mux, CK_443X),
1869 CLK(NULL, "timer6_fck", &timer6_fck, CK_443X), 1548 CLK(NULL, "timer6_sync_mux", &timer6_sync_mux, CK_443X),
1870 CLK(NULL, "timer7_fck", &timer7_fck, CK_443X), 1549 CLK(NULL, "timer7_sync_mux", &timer7_sync_mux, CK_443X),
1871 CLK(NULL, "timer8_fck", &timer8_fck, CK_443X), 1550 CLK(NULL, "timer8_sync_mux", &timer8_sync_mux, CK_443X),
1872 CLK(NULL, "timer9_fck", &timer9_fck, CK_443X), 1551 CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux, CK_443X),
1873 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
1874 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
1875 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
1876 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
1877 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), 1552 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
1878 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), 1553 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
1879 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), 1554 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
@@ -1901,9 +1576,6 @@ static struct omap_clk omap44xx_clks[] = {
1901 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), 1576 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
1902 CLK(NULL, "usim_ck", &usim_ck, CK_443X), 1577 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
1903 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), 1578 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
1904 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
1905 CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
1906 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
1907 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), 1579 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
1908 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), 1580 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
1909 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 1581 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
@@ -1980,15 +1652,6 @@ static struct omap_clk omap44xx_clks[] = {
1980 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), 1652 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
1981}; 1653};
1982 1654
1983static const char *enable_init_clks[] = {
1984 "emif1_fck",
1985 "emif2_fck",
1986 "gpmc_ick",
1987 "l3_instr_ick",
1988 "l3_main_3_ick",
1989 "ocp_wp_noc_ick",
1990};
1991
1992int __init omap4xxx_clk_init(void) 1655int __init omap4xxx_clk_init(void)
1993{ 1656{
1994 u32 cpu_clkflg; 1657 u32 cpu_clkflg;
@@ -2019,9 +1682,6 @@ int __init omap4xxx_clk_init(void)
2019 1682
2020 omap2_clk_disable_autoidle_all(); 1683 omap2_clk_disable_autoidle_all();
2021 1684
2022 omap2_clk_enable_init_clocks(enable_init_clks,
2023 ARRAY_SIZE(enable_init_clks));
2024
2025 /* 1685 /*
2026 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power 1686 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
2027 * state when turning the ABE clock domain. Workaround this by 1687 * state when turning the ABE clock domain. Workaround this by
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 7faf82d4e85c..2da3b5ec010c 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -92,8 +92,6 @@ static int _clkdm_register(struct clockdomain *clkdm)
92 92
93 pwrdm_add_clkdm(pwrdm, clkdm); 93 pwrdm_add_clkdm(pwrdm, clkdm);
94 94
95 spin_lock_init(&clkdm->lock);
96
97 pr_debug("clockdomain: registered %s\n", clkdm->name); 95 pr_debug("clockdomain: registered %s\n", clkdm->name);
98 96
99 return 0; 97 return 0;
@@ -122,7 +120,7 @@ static struct clkdm_dep *_clkdm_deps_lookup(struct clockdomain *clkdm,
122 return cd; 120 return cd;
123} 121}
124 122
125/* 123/**
126 * _autodep_lookup - resolve autodep clkdm names to clkdm pointers; store 124 * _autodep_lookup - resolve autodep clkdm names to clkdm pointers; store
127 * @autodep: struct clkdm_autodep * to resolve 125 * @autodep: struct clkdm_autodep * to resolve
128 * 126 *
@@ -154,88 +152,206 @@ static void _autodep_lookup(struct clkdm_autodep *autodep)
154 autodep->clkdm.ptr = clkdm; 152 autodep->clkdm.ptr = clkdm;
155} 153}
156 154
157/* 155/**
158 * _clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable 156 * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms
159 * @clkdm: struct clockdomain * 157 * @clkdm: clockdomain that we are resolving dependencies for
158 * @clkdm_deps: ptr to array of struct clkdm_deps to resolve
160 * 159 *
161 * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm' 160 * Iterates through @clkdm_deps, looking up the struct clockdomain named by
162 * in hardware-supervised mode. Meant to be called from clock framework 161 * clkdm_name and storing the clockdomain pointer in the struct clkdm_dep.
163 * when a clock inside clockdomain 'clkdm' is enabled. No return value. 162 * No return value.
163 */
164static void _resolve_clkdm_deps(struct clockdomain *clkdm,
165 struct clkdm_dep *clkdm_deps)
166{
167 struct clkdm_dep *cd;
168
169 for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) {
170 if (cd->clkdm)
171 continue;
172 cd->clkdm = _clkdm_lookup(cd->clkdm_name);
173
174 WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen",
175 clkdm->name, cd->clkdm_name);
176 }
177}
178
179/**
180 * _clkdm_add_wkdep - add a wakeup dependency from clkdm2 to clkdm1 (lockless)
181 * @clkdm1: wake this struct clockdomain * up (dependent)
182 * @clkdm2: when this struct clockdomain * wakes up (source)
164 * 183 *
165 * XXX autodeps are deprecated and should be removed at the earliest 184 * When the clockdomain represented by @clkdm2 wakes up, wake up
166 * opportunity 185 * @clkdm1. Implemented in hardware on the OMAP, this feature is
186 * designed to reduce wakeup latency of the dependent clockdomain @clkdm1.
187 * Returns -EINVAL if presented with invalid clockdomain pointers,
188 * -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or 0 upon
189 * success.
167 */ 190 */
168void _clkdm_add_autodeps(struct clockdomain *clkdm) 191static int _clkdm_add_wkdep(struct clockdomain *clkdm1,
192 struct clockdomain *clkdm2)
169{ 193{
170 struct clkdm_autodep *autodep; 194 struct clkdm_dep *cd;
195 int ret = 0;
171 196
172 if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS) 197 if (!clkdm1 || !clkdm2)
173 return; 198 return -EINVAL;
174 199
175 for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { 200 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
176 if (IS_ERR(autodep->clkdm.ptr)) 201 if (IS_ERR(cd))
177 continue; 202 ret = PTR_ERR(cd);
178 203
179 pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n", 204 if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep)
180 clkdm->name, autodep->clkdm.ptr->name); 205 ret = -EINVAL;
206
207 if (ret) {
208 pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
209 clkdm1->name, clkdm2->name);
210 return ret;
211 }
212
213 cd->wkdep_usecount++;
214 if (cd->wkdep_usecount == 1) {
215 pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n",
216 clkdm1->name, clkdm2->name);
181 217
182 clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr); 218 ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
183 clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
184 } 219 }
220
221 return ret;
185} 222}
186 223
187/* 224/**
188 * _clkdm_add_autodeps - remove auto sleepdeps/wkdeps from clkdm 225 * _clkdm_del_wkdep - remove a wakeup dep from clkdm2 to clkdm1 (lockless)
189 * @clkdm: struct clockdomain * 226 * @clkdm1: wake this struct clockdomain * up (dependent)
227 * @clkdm2: when this struct clockdomain * wakes up (source)
190 * 228 *
191 * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm' 229 * Remove a wakeup dependency causing @clkdm1 to wake up when @clkdm2
192 * in hardware-supervised mode. Meant to be called from clock framework 230 * wakes up. Returns -EINVAL if presented with invalid clockdomain
193 * when a clock inside clockdomain 'clkdm' is disabled. No return value. 231 * pointers, -ENOENT if @clkdm2 cannot wake up clkdm1 in hardware, or
232 * 0 upon success.
233 */
234static int _clkdm_del_wkdep(struct clockdomain *clkdm1,
235 struct clockdomain *clkdm2)
236{
237 struct clkdm_dep *cd;
238 int ret = 0;
239
240 if (!clkdm1 || !clkdm2)
241 return -EINVAL;
242
243 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
244 if (IS_ERR(cd))
245 ret = PTR_ERR(cd);
246
247 if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep)
248 ret = -EINVAL;
249
250 if (ret) {
251 pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
252 clkdm1->name, clkdm2->name);
253 return ret;
254 }
255
256 cd->wkdep_usecount--;
257 if (cd->wkdep_usecount == 0) {
258 pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n",
259 clkdm1->name, clkdm2->name);
260
261 ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
262 }
263
264 return ret;
265}
266
267/**
268 * _clkdm_add_sleepdep - add a sleep dependency from clkdm2 to clkdm1 (lockless)
269 * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
270 * @clkdm2: when this struct clockdomain * is active (source)
194 * 271 *
195 * XXX autodeps are deprecated and should be removed at the earliest 272 * Prevent @clkdm1 from automatically going inactive (and then to
196 * opportunity 273 * retention or off) if @clkdm2 is active. Returns -EINVAL if
274 * presented with invalid clockdomain pointers or called on a machine
275 * that does not support software-configurable hardware sleep
276 * dependencies, -ENOENT if the specified dependency cannot be set in
277 * hardware, or 0 upon success.
197 */ 278 */
198void _clkdm_del_autodeps(struct clockdomain *clkdm) 279static int _clkdm_add_sleepdep(struct clockdomain *clkdm1,
280 struct clockdomain *clkdm2)
199{ 281{
200 struct clkdm_autodep *autodep; 282 struct clkdm_dep *cd;
283 int ret = 0;
201 284
202 if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS) 285 if (!clkdm1 || !clkdm2)
203 return; 286 return -EINVAL;
204 287
205 for (autodep = autodeps; autodep->clkdm.ptr; autodep++) { 288 cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
206 if (IS_ERR(autodep->clkdm.ptr)) 289 if (IS_ERR(cd))
207 continue; 290 ret = PTR_ERR(cd);
208 291
209 pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n", 292 if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep)
210 clkdm->name, autodep->clkdm.ptr->name); 293 ret = -EINVAL;
211 294
212 clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr); 295 if (ret) {
213 clkdm_del_wkdep(clkdm, autodep->clkdm.ptr); 296 pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
297 clkdm1->name, clkdm2->name);
298 return ret;
299 }
300
301 cd->sleepdep_usecount++;
302 if (cd->sleepdep_usecount == 1) {
303 pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n",
304 clkdm1->name, clkdm2->name);
305
306 ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
214 } 307 }
308
309 return ret;
215} 310}
216 311
217/** 312/**
218 * _resolve_clkdm_deps() - resolve clkdm_names in @clkdm_deps to clkdms 313 * _clkdm_del_sleepdep - remove a sleep dep from clkdm2 to clkdm1 (lockless)
219 * @clkdm: clockdomain that we are resolving dependencies for 314 * @clkdm1: prevent this struct clockdomain * from sleeping (dependent)
220 * @clkdm_deps: ptr to array of struct clkdm_deps to resolve 315 * @clkdm2: when this struct clockdomain * is active (source)
221 * 316 *
222 * Iterates through @clkdm_deps, looking up the struct clockdomain named by 317 * Allow @clkdm1 to automatically go inactive (and then to retention or
223 * clkdm_name and storing the clockdomain pointer in the struct clkdm_dep. 318 * off), independent of the activity state of @clkdm2. Returns -EINVAL
224 * No return value. 319 * if presented with invalid clockdomain pointers or called on a machine
320 * that does not support software-configurable hardware sleep dependencies,
321 * -ENOENT if the specified dependency cannot be cleared in hardware, or
322 * 0 upon success.
225 */ 323 */
226static void _resolve_clkdm_deps(struct clockdomain *clkdm, 324static int _clkdm_del_sleepdep(struct clockdomain *clkdm1,
227 struct clkdm_dep *clkdm_deps) 325 struct clockdomain *clkdm2)
228{ 326{
229 struct clkdm_dep *cd; 327 struct clkdm_dep *cd;
328 int ret = 0;
230 329
231 for (cd = clkdm_deps; cd && cd->clkdm_name; cd++) { 330 if (!clkdm1 || !clkdm2)
232 if (cd->clkdm) 331 return -EINVAL;
233 continue;
234 cd->clkdm = _clkdm_lookup(cd->clkdm_name);
235 332
236 WARN(!cd->clkdm, "clockdomain: %s: could not find clkdm %s while resolving dependencies - should never happen", 333 cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs);
237 clkdm->name, cd->clkdm_name); 334 if (IS_ERR(cd))
335 ret = PTR_ERR(cd);
336
337 if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep)
338 ret = -EINVAL;
339
340 if (ret) {
341 pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
342 clkdm1->name, clkdm2->name);
343 return ret;
238 } 344 }
345
346 cd->sleepdep_usecount--;
347 if (cd->sleepdep_usecount == 0) {
348 pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n",
349 clkdm1->name, clkdm2->name);
350
351 ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
352 }
353
354 return ret;
239} 355}
240 356
241/* Public functions */ 357/* Public functions */
@@ -456,30 +572,18 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm)
456int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 572int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
457{ 573{
458 struct clkdm_dep *cd; 574 struct clkdm_dep *cd;
459 int ret = 0; 575 int ret;
460 576
461 if (!clkdm1 || !clkdm2) 577 if (!clkdm1 || !clkdm2)
462 return -EINVAL; 578 return -EINVAL;
463 579
464 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); 580 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
465 if (IS_ERR(cd)) 581 if (IS_ERR(cd))
466 ret = PTR_ERR(cd); 582 return PTR_ERR(cd);
467 583
468 if (!arch_clkdm || !arch_clkdm->clkdm_add_wkdep) 584 pwrdm_lock(cd->clkdm->pwrdm.ptr);
469 ret = -EINVAL; 585 ret = _clkdm_add_wkdep(clkdm1, clkdm2);
470 586 pwrdm_unlock(cd->clkdm->pwrdm.ptr);
471 if (ret) {
472 pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
473 clkdm1->name, clkdm2->name);
474 return ret;
475 }
476
477 if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
478 pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n",
479 clkdm1->name, clkdm2->name);
480
481 ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
482 }
483 587
484 return ret; 588 return ret;
485} 589}
@@ -497,30 +601,18 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
497int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 601int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
498{ 602{
499 struct clkdm_dep *cd; 603 struct clkdm_dep *cd;
500 int ret = 0; 604 int ret;
501 605
502 if (!clkdm1 || !clkdm2) 606 if (!clkdm1 || !clkdm2)
503 return -EINVAL; 607 return -EINVAL;
504 608
505 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs); 609 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
506 if (IS_ERR(cd)) 610 if (IS_ERR(cd))
507 ret = PTR_ERR(cd); 611 return PTR_ERR(cd);
508 612
509 if (!arch_clkdm || !arch_clkdm->clkdm_del_wkdep) 613 pwrdm_lock(cd->clkdm->pwrdm.ptr);
510 ret = -EINVAL; 614 ret = _clkdm_del_wkdep(clkdm1, clkdm2);
511 615 pwrdm_unlock(cd->clkdm->pwrdm.ptr);
512 if (ret) {
513 pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
514 clkdm1->name, clkdm2->name);
515 return ret;
516 }
517
518 if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
519 pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n",
520 clkdm1->name, clkdm2->name);
521
522 ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
523 }
524 616
525 return ret; 617 return ret;
526} 618}
@@ -560,7 +652,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
560 return ret; 652 return ret;
561 } 653 }
562 654
563 /* XXX It's faster to return the atomic wkdep_usecount */ 655 /* XXX It's faster to return the wkdep_usecount */
564 return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2); 656 return arch_clkdm->clkdm_read_wkdep(clkdm1, clkdm2);
565} 657}
566 658
@@ -600,30 +692,18 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
600int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 692int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
601{ 693{
602 struct clkdm_dep *cd; 694 struct clkdm_dep *cd;
603 int ret = 0; 695 int ret;
604 696
605 if (!clkdm1 || !clkdm2) 697 if (!clkdm1 || !clkdm2)
606 return -EINVAL; 698 return -EINVAL;
607 699
608 cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); 700 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
609 if (IS_ERR(cd)) 701 if (IS_ERR(cd))
610 ret = PTR_ERR(cd); 702 return PTR_ERR(cd);
611 703
612 if (!arch_clkdm || !arch_clkdm->clkdm_add_sleepdep) 704 pwrdm_lock(cd->clkdm->pwrdm.ptr);
613 ret = -EINVAL; 705 ret = _clkdm_add_sleepdep(clkdm1, clkdm2);
614 706 pwrdm_unlock(cd->clkdm->pwrdm.ptr);
615 if (ret) {
616 pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
617 clkdm1->name, clkdm2->name);
618 return ret;
619 }
620
621 if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
622 pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n",
623 clkdm1->name, clkdm2->name);
624
625 ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
626 }
627 707
628 return ret; 708 return ret;
629} 709}
@@ -643,30 +723,18 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
643int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) 723int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
644{ 724{
645 struct clkdm_dep *cd; 725 struct clkdm_dep *cd;
646 int ret = 0; 726 int ret;
647 727
648 if (!clkdm1 || !clkdm2) 728 if (!clkdm1 || !clkdm2)
649 return -EINVAL; 729 return -EINVAL;
650 730
651 cd = _clkdm_deps_lookup(clkdm2, clkdm1->sleepdep_srcs); 731 cd = _clkdm_deps_lookup(clkdm2, clkdm1->wkdep_srcs);
652 if (IS_ERR(cd)) 732 if (IS_ERR(cd))
653 ret = PTR_ERR(cd); 733 return PTR_ERR(cd);
654 734
655 if (!arch_clkdm || !arch_clkdm->clkdm_del_sleepdep) 735 pwrdm_lock(cd->clkdm->pwrdm.ptr);
656 ret = -EINVAL; 736 ret = _clkdm_del_sleepdep(clkdm1, clkdm2);
657 737 pwrdm_unlock(cd->clkdm->pwrdm.ptr);
658 if (ret) {
659 pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
660 clkdm1->name, clkdm2->name);
661 return ret;
662 }
663
664 if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
665 pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n",
666 clkdm1->name, clkdm2->name);
667
668 ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
669 }
670 738
671 return ret; 739 return ret;
672} 740}
@@ -708,7 +776,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2)
708 return ret; 776 return ret;
709 } 777 }
710 778
711 /* XXX It's faster to return the atomic sleepdep_usecount */ 779 /* XXX It's faster to return the sleepdep_usecount */
712 return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2); 780 return arch_clkdm->clkdm_read_sleepdep(clkdm1, clkdm2);
713} 781}
714 782
@@ -734,18 +802,17 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
734} 802}
735 803
736/** 804/**
737 * clkdm_sleep - force clockdomain sleep transition 805 * clkdm_sleep_nolock - force clockdomain sleep transition (lockless)
738 * @clkdm: struct clockdomain * 806 * @clkdm: struct clockdomain *
739 * 807 *
740 * Instruct the CM to force a sleep transition on the specified 808 * Instruct the CM to force a sleep transition on the specified
741 * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if 809 * clockdomain @clkdm. Only for use by the powerdomain code. Returns
742 * clockdomain does not support software-initiated sleep; 0 upon 810 * -EINVAL if @clkdm is NULL or if clockdomain does not support
743 * success. 811 * software-initiated sleep; 0 upon success.
744 */ 812 */
745int clkdm_sleep(struct clockdomain *clkdm) 813int clkdm_sleep_nolock(struct clockdomain *clkdm)
746{ 814{
747 int ret; 815 int ret;
748 unsigned long flags;
749 816
750 if (!clkdm) 817 if (!clkdm)
751 return -EINVAL; 818 return -EINVAL;
@@ -761,26 +828,45 @@ int clkdm_sleep(struct clockdomain *clkdm)
761 828
762 pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name); 829 pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
763 830
764 spin_lock_irqsave(&clkdm->lock, flags);
765 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; 831 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
766 ret = arch_clkdm->clkdm_sleep(clkdm); 832 ret = arch_clkdm->clkdm_sleep(clkdm);
767 spin_unlock_irqrestore(&clkdm->lock, flags); 833 ret |= pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
834
768 return ret; 835 return ret;
769} 836}
770 837
771/** 838/**
772 * clkdm_wakeup - force clockdomain wakeup transition 839 * clkdm_sleep - force clockdomain sleep transition
773 * @clkdm: struct clockdomain * 840 * @clkdm: struct clockdomain *
774 * 841 *
775 * Instruct the CM to force a wakeup transition on the specified 842 * Instruct the CM to force a sleep transition on the specified
776 * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if the 843 * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if
777 * clockdomain does not support software-controlled wakeup; 0 upon 844 * clockdomain does not support software-initiated sleep; 0 upon
778 * success. 845 * success.
779 */ 846 */
780int clkdm_wakeup(struct clockdomain *clkdm) 847int clkdm_sleep(struct clockdomain *clkdm)
848{
849 int ret;
850
851 pwrdm_lock(clkdm->pwrdm.ptr);
852 ret = clkdm_sleep_nolock(clkdm);
853 pwrdm_unlock(clkdm->pwrdm.ptr);
854
855 return ret;
856}
857
858/**
859 * clkdm_wakeup_nolock - force clockdomain wakeup transition (lockless)
860 * @clkdm: struct clockdomain *
861 *
862 * Instruct the CM to force a wakeup transition on the specified
863 * clockdomain @clkdm. Only for use by the powerdomain code. Returns
864 * -EINVAL if @clkdm is NULL or if the clockdomain does not support
865 * software-controlled wakeup; 0 upon success.
866 */
867int clkdm_wakeup_nolock(struct clockdomain *clkdm)
781{ 868{
782 int ret; 869 int ret;
783 unsigned long flags;
784 870
785 if (!clkdm) 871 if (!clkdm)
786 return -EINVAL; 872 return -EINVAL;
@@ -796,28 +882,46 @@ int clkdm_wakeup(struct clockdomain *clkdm)
796 882
797 pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name); 883 pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
798 884
799 spin_lock_irqsave(&clkdm->lock, flags);
800 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; 885 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
801 ret = arch_clkdm->clkdm_wakeup(clkdm); 886 ret = arch_clkdm->clkdm_wakeup(clkdm);
802 ret |= pwrdm_state_switch(clkdm->pwrdm.ptr); 887 ret |= pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
803 spin_unlock_irqrestore(&clkdm->lock, flags); 888
804 return ret; 889 return ret;
805} 890}
806 891
807/** 892/**
808 * clkdm_allow_idle - enable hwsup idle transitions for clkdm 893 * clkdm_wakeup - force clockdomain wakeup transition
809 * @clkdm: struct clockdomain * 894 * @clkdm: struct clockdomain *
810 * 895 *
811 * Allow the hardware to automatically switch the clockdomain @clkdm into 896 * Instruct the CM to force a wakeup transition on the specified
812 * active or idle states, as needed by downstream clocks. If the 897 * clockdomain @clkdm. Returns -EINVAL if @clkdm is NULL or if the
898 * clockdomain does not support software-controlled wakeup; 0 upon
899 * success.
900 */
901int clkdm_wakeup(struct clockdomain *clkdm)
902{
903 int ret;
904
905 pwrdm_lock(clkdm->pwrdm.ptr);
906 ret = clkdm_wakeup_nolock(clkdm);
907 pwrdm_unlock(clkdm->pwrdm.ptr);
908
909 return ret;
910}
911
912/**
913 * clkdm_allow_idle_nolock - enable hwsup idle transitions for clkdm
914 * @clkdm: struct clockdomain *
915 *
916 * Allow the hardware to automatically switch the clockdomain @clkdm
917 * into active or idle states, as needed by downstream clocks. If the
813 * clockdomain has any downstream clocks enabled in the clock 918 * clockdomain has any downstream clocks enabled in the clock
814 * framework, wkdep/sleepdep autodependencies are added; this is so 919 * framework, wkdep/sleepdep autodependencies are added; this is so
815 * device drivers can read and write to the device. No return value. 920 * device drivers can read and write to the device. Only for use by
921 * the powerdomain code. No return value.
816 */ 922 */
817void clkdm_allow_idle(struct clockdomain *clkdm) 923void clkdm_allow_idle_nolock(struct clockdomain *clkdm)
818{ 924{
819 unsigned long flags;
820
821 if (!clkdm) 925 if (!clkdm)
822 return; 926 return;
823 927
@@ -833,11 +937,26 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
833 pr_debug("clockdomain: enabling automatic idle transitions for %s\n", 937 pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
834 clkdm->name); 938 clkdm->name);
835 939
836 spin_lock_irqsave(&clkdm->lock, flags);
837 clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED; 940 clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
838 arch_clkdm->clkdm_allow_idle(clkdm); 941 arch_clkdm->clkdm_allow_idle(clkdm);
839 pwrdm_state_switch(clkdm->pwrdm.ptr); 942 pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
840 spin_unlock_irqrestore(&clkdm->lock, flags); 943}
944
945/**
946 * clkdm_allow_idle - enable hwsup idle transitions for clkdm
947 * @clkdm: struct clockdomain *
948 *
949 * Allow the hardware to automatically switch the clockdomain @clkdm into
950 * active or idle states, as needed by downstream clocks. If the
951 * clockdomain has any downstream clocks enabled in the clock
952 * framework, wkdep/sleepdep autodependencies are added; this is so
953 * device drivers can read and write to the device. No return value.
954 */
955void clkdm_allow_idle(struct clockdomain *clkdm)
956{
957 pwrdm_lock(clkdm->pwrdm.ptr);
958 clkdm_allow_idle_nolock(clkdm);
959 pwrdm_unlock(clkdm->pwrdm.ptr);
841} 960}
842 961
843/** 962/**
@@ -847,12 +966,11 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
847 * Prevent the hardware from automatically switching the clockdomain 966 * Prevent the hardware from automatically switching the clockdomain
848 * @clkdm into inactive or idle states. If the clockdomain has 967 * @clkdm into inactive or idle states. If the clockdomain has
849 * downstream clocks enabled in the clock framework, wkdep/sleepdep 968 * downstream clocks enabled in the clock framework, wkdep/sleepdep
850 * autodependencies are removed. No return value. 969 * autodependencies are removed. Only for use by the powerdomain
970 * code. No return value.
851 */ 971 */
852void clkdm_deny_idle(struct clockdomain *clkdm) 972void clkdm_deny_idle_nolock(struct clockdomain *clkdm)
853{ 973{
854 unsigned long flags;
855
856 if (!clkdm) 974 if (!clkdm)
857 return; 975 return;
858 976
@@ -868,11 +986,25 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
868 pr_debug("clockdomain: disabling automatic idle transitions for %s\n", 986 pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
869 clkdm->name); 987 clkdm->name);
870 988
871 spin_lock_irqsave(&clkdm->lock, flags);
872 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED; 989 clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
873 arch_clkdm->clkdm_deny_idle(clkdm); 990 arch_clkdm->clkdm_deny_idle(clkdm);
874 pwrdm_state_switch(clkdm->pwrdm.ptr); 991 pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
875 spin_unlock_irqrestore(&clkdm->lock, flags); 992}
993
994/**
995 * clkdm_deny_idle - disable hwsup idle transitions for clkdm
996 * @clkdm: struct clockdomain *
997 *
998 * Prevent the hardware from automatically switching the clockdomain
999 * @clkdm into inactive or idle states. If the clockdomain has
1000 * downstream clocks enabled in the clock framework, wkdep/sleepdep
1001 * autodependencies are removed. No return value.
1002 */
1003void clkdm_deny_idle(struct clockdomain *clkdm)
1004{
1005 pwrdm_lock(clkdm->pwrdm.ptr);
1006 clkdm_deny_idle_nolock(clkdm);
1007 pwrdm_unlock(clkdm->pwrdm.ptr);
876} 1008}
877 1009
878/** 1010/**
@@ -889,14 +1021,11 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
889bool clkdm_in_hwsup(struct clockdomain *clkdm) 1021bool clkdm_in_hwsup(struct clockdomain *clkdm)
890{ 1022{
891 bool ret; 1023 bool ret;
892 unsigned long flags;
893 1024
894 if (!clkdm) 1025 if (!clkdm)
895 return false; 1026 return false;
896 1027
897 spin_lock_irqsave(&clkdm->lock, flags);
898 ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false; 1028 ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
899 spin_unlock_irqrestore(&clkdm->lock, flags);
900 1029
901 return ret; 1030 return ret;
902} 1031}
@@ -918,30 +1047,91 @@ bool clkdm_missing_idle_reporting(struct clockdomain *clkdm)
918 return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false; 1047 return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false;
919} 1048}
920 1049
1050/* Public autodep handling functions (deprecated) */
1051
1052/**
1053 * clkdm_add_autodeps - add auto sleepdeps/wkdeps to clkdm upon clock enable
1054 * @clkdm: struct clockdomain *
1055 *
1056 * Add the "autodep" sleep & wakeup dependencies to clockdomain 'clkdm'
1057 * in hardware-supervised mode. Meant to be called from clock framework
1058 * when a clock inside clockdomain 'clkdm' is enabled. No return value.
1059 *
1060 * XXX autodeps are deprecated and should be removed at the earliest
1061 * opportunity
1062 */
1063void clkdm_add_autodeps(struct clockdomain *clkdm)
1064{
1065 struct clkdm_autodep *autodep;
1066
1067 if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
1068 return;
1069
1070 for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
1071 if (IS_ERR(autodep->clkdm.ptr))
1072 continue;
1073
1074 pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n",
1075 clkdm->name, autodep->clkdm.ptr->name);
1076
1077 _clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
1078 _clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
1079 }
1080}
1081
1082/**
1083 * clkdm_del_autodeps - remove auto sleepdeps/wkdeps from clkdm
1084 * @clkdm: struct clockdomain *
1085 *
1086 * Remove the "autodep" sleep & wakeup dependencies from clockdomain 'clkdm'
1087 * in hardware-supervised mode. Meant to be called from clock framework
1088 * when a clock inside clockdomain 'clkdm' is disabled. No return value.
1089 *
1090 * XXX autodeps are deprecated and should be removed at the earliest
1091 * opportunity
1092 */
1093void clkdm_del_autodeps(struct clockdomain *clkdm)
1094{
1095 struct clkdm_autodep *autodep;
1096
1097 if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
1098 return;
1099
1100 for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
1101 if (IS_ERR(autodep->clkdm.ptr))
1102 continue;
1103
1104 pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n",
1105 clkdm->name, autodep->clkdm.ptr->name);
1106
1107 _clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
1108 _clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
1109 }
1110}
1111
921/* Clockdomain-to-clock/hwmod framework interface code */ 1112/* Clockdomain-to-clock/hwmod framework interface code */
922 1113
923static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm) 1114static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
924{ 1115{
925 unsigned long flags;
926
927 if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable) 1116 if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
928 return -EINVAL; 1117 return -EINVAL;
929 1118
930 spin_lock_irqsave(&clkdm->lock, flags); 1119 pwrdm_lock(clkdm->pwrdm.ptr);
931 1120
932 /* 1121 /*
933 * For arch's with no autodeps, clkcm_clk_enable 1122 * For arch's with no autodeps, clkcm_clk_enable
934 * should be called for every clock instance or hwmod that is 1123 * should be called for every clock instance or hwmod that is
935 * enabled, so the clkdm can be force woken up. 1124 * enabled, so the clkdm can be force woken up.
936 */ 1125 */
937 if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps) { 1126 clkdm->usecount++;
938 spin_unlock_irqrestore(&clkdm->lock, flags); 1127 if (clkdm->usecount > 1 && autodeps) {
1128 pwrdm_unlock(clkdm->pwrdm.ptr);
939 return 0; 1129 return 0;
940 } 1130 }
941 1131
942 arch_clkdm->clkdm_clk_enable(clkdm); 1132 arch_clkdm->clkdm_clk_enable(clkdm);
943 pwrdm_state_switch(clkdm->pwrdm.ptr); 1133 pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
944 spin_unlock_irqrestore(&clkdm->lock, flags); 1134 pwrdm_unlock(clkdm->pwrdm.ptr);
945 1135
946 pr_debug("clockdomain: %s: enabled\n", clkdm->name); 1136 pr_debug("clockdomain: %s: enabled\n", clkdm->name);
947 1137
@@ -990,36 +1180,34 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
990 */ 1180 */
991int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) 1181int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
992{ 1182{
993 unsigned long flags;
994
995 if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) 1183 if (!clkdm || !clk || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
996 return -EINVAL; 1184 return -EINVAL;
997 1185
998 spin_lock_irqsave(&clkdm->lock, flags); 1186 pwrdm_lock(clkdm->pwrdm.ptr);
999 1187
1000 /* corner case: disabling unused clocks */ 1188 /* corner case: disabling unused clocks */
1001 if ((__clk_get_enable_count(clk) == 0) && 1189 if ((__clk_get_enable_count(clk) == 0) && clkdm->usecount == 0)
1002 (atomic_read(&clkdm->usecount) == 0))
1003 goto ccd_exit; 1190 goto ccd_exit;
1004 1191
1005 if (atomic_read(&clkdm->usecount) == 0) { 1192 if (clkdm->usecount == 0) {
1006 spin_unlock_irqrestore(&clkdm->lock, flags); 1193 pwrdm_unlock(clkdm->pwrdm.ptr);
1007 WARN_ON(1); /* underflow */ 1194 WARN_ON(1); /* underflow */
1008 return -ERANGE; 1195 return -ERANGE;
1009 } 1196 }
1010 1197
1011 if (atomic_dec_return(&clkdm->usecount) > 0) { 1198 clkdm->usecount--;
1012 spin_unlock_irqrestore(&clkdm->lock, flags); 1199 if (clkdm->usecount > 0) {
1200 pwrdm_unlock(clkdm->pwrdm.ptr);
1013 return 0; 1201 return 0;
1014 } 1202 }
1015 1203
1016 arch_clkdm->clkdm_clk_disable(clkdm); 1204 arch_clkdm->clkdm_clk_disable(clkdm);
1017 pwrdm_state_switch(clkdm->pwrdm.ptr); 1205 pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
1018 1206
1019 pr_debug("clockdomain: %s: disabled\n", clkdm->name); 1207 pr_debug("clockdomain: %s: disabled\n", clkdm->name);
1020 1208
1021ccd_exit: 1209ccd_exit:
1022 spin_unlock_irqrestore(&clkdm->lock, flags); 1210 pwrdm_unlock(clkdm->pwrdm.ptr);
1023 1211
1024 return 0; 1212 return 0;
1025} 1213}
@@ -1072,8 +1260,6 @@ int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
1072 */ 1260 */
1073int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh) 1261int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
1074{ 1262{
1075 unsigned long flags;
1076
1077 /* The clkdm attribute does not exist yet prior OMAP4 */ 1263 /* The clkdm attribute does not exist yet prior OMAP4 */
1078 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 1264 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1079 return 0; 1265 return 0;
@@ -1086,22 +1272,23 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
1086 if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable) 1272 if (!clkdm || !oh || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
1087 return -EINVAL; 1273 return -EINVAL;
1088 1274
1089 spin_lock_irqsave(&clkdm->lock, flags); 1275 pwrdm_lock(clkdm->pwrdm.ptr);
1090 1276
1091 if (atomic_read(&clkdm->usecount) == 0) { 1277 if (clkdm->usecount == 0) {
1092 spin_unlock_irqrestore(&clkdm->lock, flags); 1278 pwrdm_unlock(clkdm->pwrdm.ptr);
1093 WARN_ON(1); /* underflow */ 1279 WARN_ON(1); /* underflow */
1094 return -ERANGE; 1280 return -ERANGE;
1095 } 1281 }
1096 1282
1097 if (atomic_dec_return(&clkdm->usecount) > 0) { 1283 clkdm->usecount--;
1098 spin_unlock_irqrestore(&clkdm->lock, flags); 1284 if (clkdm->usecount > 0) {
1285 pwrdm_unlock(clkdm->pwrdm.ptr);
1099 return 0; 1286 return 0;
1100 } 1287 }
1101 1288
1102 arch_clkdm->clkdm_clk_disable(clkdm); 1289 arch_clkdm->clkdm_clk_disable(clkdm);
1103 pwrdm_state_switch(clkdm->pwrdm.ptr); 1290 pwrdm_state_switch_nolock(clkdm->pwrdm.ptr);
1104 spin_unlock_irqrestore(&clkdm->lock, flags); 1291 pwrdm_unlock(clkdm->pwrdm.ptr);
1105 1292
1106 pr_debug("clockdomain: %s: disabled\n", clkdm->name); 1293 pr_debug("clockdomain: %s: disabled\n", clkdm->name);
1107 1294
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index bc42446e23ab..2da37656a693 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -15,7 +15,6 @@
15#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H 15#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
16 16
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/spinlock.h>
19 18
20#include "powerdomain.h" 19#include "powerdomain.h"
21#include "clock.h" 20#include "clock.h"
@@ -92,8 +91,8 @@ struct clkdm_autodep {
92struct clkdm_dep { 91struct clkdm_dep {
93 const char *clkdm_name; 92 const char *clkdm_name;
94 struct clockdomain *clkdm; 93 struct clockdomain *clkdm;
95 atomic_t wkdep_usecount; 94 s16 wkdep_usecount;
96 atomic_t sleepdep_usecount; 95 s16 sleepdep_usecount;
97}; 96};
98 97
99/* Possible flags for struct clockdomain._flags */ 98/* Possible flags for struct clockdomain._flags */
@@ -137,9 +136,8 @@ struct clockdomain {
137 const u16 clkdm_offs; 136 const u16 clkdm_offs;
138 struct clkdm_dep *wkdep_srcs; 137 struct clkdm_dep *wkdep_srcs;
139 struct clkdm_dep *sleepdep_srcs; 138 struct clkdm_dep *sleepdep_srcs;
140 atomic_t usecount; 139 int usecount;
141 struct list_head node; 140 struct list_head node;
142 spinlock_t lock;
143}; 141};
144 142
145/** 143/**
@@ -196,12 +194,16 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
196int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); 194int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2);
197int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); 195int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
198 196
197void clkdm_allow_idle_nolock(struct clockdomain *clkdm);
199void clkdm_allow_idle(struct clockdomain *clkdm); 198void clkdm_allow_idle(struct clockdomain *clkdm);
199void clkdm_deny_idle_nolock(struct clockdomain *clkdm);
200void clkdm_deny_idle(struct clockdomain *clkdm); 200void clkdm_deny_idle(struct clockdomain *clkdm);
201bool clkdm_in_hwsup(struct clockdomain *clkdm); 201bool clkdm_in_hwsup(struct clockdomain *clkdm);
202bool clkdm_missing_idle_reporting(struct clockdomain *clkdm); 202bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
203 203
204int clkdm_wakeup_nolock(struct clockdomain *clkdm);
204int clkdm_wakeup(struct clockdomain *clkdm); 205int clkdm_wakeup(struct clockdomain *clkdm);
206int clkdm_sleep_nolock(struct clockdomain *clkdm);
205int clkdm_sleep(struct clockdomain *clkdm); 207int clkdm_sleep(struct clockdomain *clkdm);
206 208
207int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); 209int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
@@ -214,8 +216,9 @@ extern void __init omap243x_clockdomains_init(void);
214extern void __init omap3xxx_clockdomains_init(void); 216extern void __init omap3xxx_clockdomains_init(void);
215extern void __init am33xx_clockdomains_init(void); 217extern void __init am33xx_clockdomains_init(void);
216extern void __init omap44xx_clockdomains_init(void); 218extern void __init omap44xx_clockdomains_init(void);
217extern void _clkdm_add_autodeps(struct clockdomain *clkdm); 219
218extern void _clkdm_del_autodeps(struct clockdomain *clkdm); 220extern void clkdm_add_autodeps(struct clockdomain *clkdm);
221extern void clkdm_del_autodeps(struct clockdomain *clkdm);
219 222
220extern struct clkdm_ops omap2_clkdm_operations; 223extern struct clkdm_ops omap2_clkdm_operations;
221extern struct clkdm_ops omap3_clkdm_operations; 224extern struct clkdm_ops omap3_clkdm_operations;
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index db650690e9d0..6774a53a3874 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -273,9 +273,6 @@ int omap2xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
273 273
274static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm) 274static void omap2xxx_clkdm_allow_idle(struct clockdomain *clkdm)
275{ 275{
276 if (atomic_read(&clkdm->usecount) > 0)
277 _clkdm_add_autodeps(clkdm);
278
279 omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, 276 omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
280 clkdm->clktrctrl_mask); 277 clkdm->clktrctrl_mask);
281} 278}
@@ -284,9 +281,6 @@ static void omap2xxx_clkdm_deny_idle(struct clockdomain *clkdm)
284{ 281{
285 omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, 282 omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
286 clkdm->clktrctrl_mask); 283 clkdm->clktrctrl_mask);
287
288 if (atomic_read(&clkdm->usecount) > 0)
289 _clkdm_del_autodeps(clkdm);
290} 284}
291 285
292static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm) 286static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
@@ -298,18 +292,8 @@ static int omap2xxx_clkdm_clk_enable(struct clockdomain *clkdm)
298 292
299 hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, 293 hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
300 clkdm->clktrctrl_mask); 294 clkdm->clktrctrl_mask);
301 295 if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
302 if (hwsup) { 296 omap2xxx_clkdm_wakeup(clkdm);
303 /* Disable HW transitions when we are changing deps */
304 omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
305 clkdm->clktrctrl_mask);
306 _clkdm_add_autodeps(clkdm);
307 omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
308 clkdm->clktrctrl_mask);
309 } else {
310 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
311 omap2xxx_clkdm_wakeup(clkdm);
312 }
313 297
314 return 0; 298 return 0;
315} 299}
@@ -324,17 +308,8 @@ static int omap2xxx_clkdm_clk_disable(struct clockdomain *clkdm)
324 hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, 308 hwsup = omap2xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
325 clkdm->clktrctrl_mask); 309 clkdm->clktrctrl_mask);
326 310
327 if (hwsup) { 311 if (!hwsup && clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
328 /* Disable HW transitions when we are changing deps */ 312 omap2xxx_clkdm_sleep(clkdm);
329 omap2xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
330 clkdm->clktrctrl_mask);
331 _clkdm_del_autodeps(clkdm);
332 omap2xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
333 clkdm->clktrctrl_mask);
334 } else {
335 if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
336 omap2xxx_clkdm_sleep(clkdm);
337 }
338 313
339 return 0; 314 return 0;
340} 315}
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index c2086f2e86b6..9061c307d915 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -186,7 +186,7 @@ static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
186 continue; /* only happens if data is erroneous */ 186 continue; /* only happens if data is erroneous */
187 187
188 mask |= 1 << cd->clkdm->dep_bit; 188 mask |= 1 << cd->clkdm->dep_bit;
189 atomic_set(&cd->sleepdep_usecount, 0); 189 cd->sleepdep_usecount = 0;
190 } 190 }
191 omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, 191 omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
192 OMAP3430_CM_SLEEPDEP); 192 OMAP3430_CM_SLEEPDEP);
@@ -209,8 +209,8 @@ static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm)
209 209
210static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm) 210static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
211{ 211{
212 if (atomic_read(&clkdm->usecount) > 0) 212 if (clkdm->usecount > 0)
213 _clkdm_add_autodeps(clkdm); 213 clkdm_add_autodeps(clkdm);
214 214
215 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, 215 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
216 clkdm->clktrctrl_mask); 216 clkdm->clktrctrl_mask);
@@ -221,8 +221,8 @@ static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm)
221 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, 221 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
222 clkdm->clktrctrl_mask); 222 clkdm->clktrctrl_mask);
223 223
224 if (atomic_read(&clkdm->usecount) > 0) 224 if (clkdm->usecount > 0)
225 _clkdm_del_autodeps(clkdm); 225 clkdm_del_autodeps(clkdm);
226} 226}
227 227
228static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm) 228static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
@@ -250,7 +250,7 @@ static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
250 /* Disable HW transitions when we are changing deps */ 250 /* Disable HW transitions when we are changing deps */
251 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, 251 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
252 clkdm->clktrctrl_mask); 252 clkdm->clktrctrl_mask);
253 _clkdm_add_autodeps(clkdm); 253 clkdm_add_autodeps(clkdm);
254 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, 254 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
255 clkdm->clktrctrl_mask); 255 clkdm->clktrctrl_mask);
256 } else { 256 } else {
@@ -287,7 +287,7 @@ static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
287 /* Disable HW transitions when we are changing deps */ 287 /* Disable HW transitions when we are changing deps */
288 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, 288 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
289 clkdm->clktrctrl_mask); 289 clkdm->clktrctrl_mask);
290 _clkdm_del_autodeps(clkdm); 290 clkdm_del_autodeps(clkdm);
291 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, 291 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
292 clkdm->clktrctrl_mask); 292 clkdm->clktrctrl_mask);
293 } else { 293 } else {
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 7f9a464f01e9..f0290f5566fe 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -393,7 +393,7 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
393 continue; /* only happens if data is erroneous */ 393 continue; /* only happens if data is erroneous */
394 394
395 mask |= 1 << cd->clkdm->dep_bit; 395 mask |= 1 << cd->clkdm->dep_bit;
396 atomic_set(&cd->wkdep_usecount, 0); 396 cd->wkdep_usecount = 0;
397 } 397 }
398 398
399 omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition, 399 omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 22590dbe8f14..80392fca86c6 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -36,40 +36,66 @@
36 36
37/* Mach specific information to be recorded in the C-state driver_data */ 37/* Mach specific information to be recorded in the C-state driver_data */
38struct omap3_idle_statedata { 38struct omap3_idle_statedata {
39 u32 mpu_state; 39 u8 mpu_state;
40 u32 core_state; 40 u8 core_state;
41 u8 per_min_state;
42 u8 flags;
41}; 43};
42 44
43static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; 45static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
44 46
47/*
48 * Possible flag bits for struct omap3_idle_statedata.flags:
49 *
50 * OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go
51 * inactive. This in turn prevents the MPU DPLL from entering autoidle
52 * mode, so wakeup latency is greatly reduced, at the cost of additional
53 * energy consumption. This also prevents the CORE clockdomain from
54 * entering idle.
55 */
56#define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE BIT(0)
57
58/*
59 * Prevent PER OFF if CORE is not in RETention or OFF as this would
60 * disable PER wakeups completely.
61 */
45static struct omap3_idle_statedata omap3_idle_data[] = { 62static struct omap3_idle_statedata omap3_idle_data[] = {
46 { 63 {
47 .mpu_state = PWRDM_POWER_ON, 64 .mpu_state = PWRDM_POWER_ON,
48 .core_state = PWRDM_POWER_ON, 65 .core_state = PWRDM_POWER_ON,
66 /* In C1 do not allow PER state lower than CORE state */
67 .per_min_state = PWRDM_POWER_ON,
68 .flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE,
49 }, 69 },
50 { 70 {
51 .mpu_state = PWRDM_POWER_ON, 71 .mpu_state = PWRDM_POWER_ON,
52 .core_state = PWRDM_POWER_ON, 72 .core_state = PWRDM_POWER_ON,
73 .per_min_state = PWRDM_POWER_RET,
53 }, 74 },
54 { 75 {
55 .mpu_state = PWRDM_POWER_RET, 76 .mpu_state = PWRDM_POWER_RET,
56 .core_state = PWRDM_POWER_ON, 77 .core_state = PWRDM_POWER_ON,
78 .per_min_state = PWRDM_POWER_RET,
57 }, 79 },
58 { 80 {
59 .mpu_state = PWRDM_POWER_OFF, 81 .mpu_state = PWRDM_POWER_OFF,
60 .core_state = PWRDM_POWER_ON, 82 .core_state = PWRDM_POWER_ON,
83 .per_min_state = PWRDM_POWER_RET,
61 }, 84 },
62 { 85 {
63 .mpu_state = PWRDM_POWER_RET, 86 .mpu_state = PWRDM_POWER_RET,
64 .core_state = PWRDM_POWER_RET, 87 .core_state = PWRDM_POWER_RET,
88 .per_min_state = PWRDM_POWER_OFF,
65 }, 89 },
66 { 90 {
67 .mpu_state = PWRDM_POWER_OFF, 91 .mpu_state = PWRDM_POWER_OFF,
68 .core_state = PWRDM_POWER_RET, 92 .core_state = PWRDM_POWER_RET,
93 .per_min_state = PWRDM_POWER_OFF,
69 }, 94 },
70 { 95 {
71 .mpu_state = PWRDM_POWER_OFF, 96 .mpu_state = PWRDM_POWER_OFF,
72 .core_state = PWRDM_POWER_OFF, 97 .core_state = PWRDM_POWER_OFF,
98 .per_min_state = PWRDM_POWER_OFF,
73 }, 99 },
74}; 100};
75 101
@@ -80,27 +106,25 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
80 int index) 106 int index)
81{ 107{
82 struct omap3_idle_statedata *cx = &omap3_idle_data[index]; 108 struct omap3_idle_statedata *cx = &omap3_idle_data[index];
83 u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
84 109
85 local_fiq_disable(); 110 local_fiq_disable();
86 111
87 pwrdm_set_next_pwrst(mpu_pd, mpu_state);
88 pwrdm_set_next_pwrst(core_pd, core_state);
89
90 if (omap_irq_pending() || need_resched()) 112 if (omap_irq_pending() || need_resched())
91 goto return_sleep_time; 113 goto return_sleep_time;
92 114
93 /* Deny idle for C1 */ 115 /* Deny idle for C1 */
94 if (index == 0) { 116 if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) {
95 clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]); 117 clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
96 clkdm_deny_idle(core_pd->pwrdm_clkdms[0]); 118 } else {
119 pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
120 pwrdm_set_next_pwrst(core_pd, cx->core_state);
97 } 121 }
98 122
99 /* 123 /*
100 * Call idle CPU PM enter notifier chain so that 124 * Call idle CPU PM enter notifier chain so that
101 * VFP context is saved. 125 * VFP context is saved.
102 */ 126 */
103 if (mpu_state == PWRDM_POWER_OFF) 127 if (cx->mpu_state == PWRDM_POWER_OFF)
104 cpu_pm_enter(); 128 cpu_pm_enter();
105 129
106 /* Execute ARM wfi */ 130 /* Execute ARM wfi */
@@ -110,17 +134,15 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
110 * Call idle CPU PM enter notifier chain to restore 134 * Call idle CPU PM enter notifier chain to restore
111 * VFP context. 135 * VFP context.
112 */ 136 */
113 if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF) 137 if (cx->mpu_state == PWRDM_POWER_OFF &&
138 pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
114 cpu_pm_exit(); 139 cpu_pm_exit();
115 140
116 /* Re-allow idle for C1 */ 141 /* Re-allow idle for C1 */
117 if (index == 0) { 142 if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE)
118 clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]); 143 clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
119 clkdm_allow_idle(core_pd->pwrdm_clkdms[0]);
120 }
121 144
122return_sleep_time: 145return_sleep_time:
123
124 local_fiq_enable(); 146 local_fiq_enable();
125 147
126 return index; 148 return index;
@@ -185,7 +207,7 @@ static int next_valid_state(struct cpuidle_device *dev,
185 * Start search from the next (lower) state. 207 * Start search from the next (lower) state.
186 */ 208 */
187 for (idx = index - 1; idx >= 0; idx--) { 209 for (idx = index - 1; idx >= 0; idx--) {
188 cx = &omap3_idle_data[idx]; 210 cx = &omap3_idle_data[idx];
189 if ((cx->mpu_state >= mpu_deepest_state) && 211 if ((cx->mpu_state >= mpu_deepest_state) &&
190 (cx->core_state >= core_deepest_state)) { 212 (cx->core_state >= core_deepest_state)) {
191 next_index = idx; 213 next_index = idx;
@@ -209,10 +231,9 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
209 struct cpuidle_driver *drv, 231 struct cpuidle_driver *drv,
210 int index) 232 int index)
211{ 233{
212 int new_state_idx; 234 int new_state_idx, ret;
213 u32 core_next_state, per_next_state = 0, per_saved_state = 0; 235 u8 per_next_state, per_saved_state;
214 struct omap3_idle_statedata *cx; 236 struct omap3_idle_statedata *cx;
215 int ret;
216 237
217 /* 238 /*
218 * Use only C1 if CAM is active. 239 * Use only C1 if CAM is active.
@@ -233,25 +254,13 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
233 254
234 /* Program PER state */ 255 /* Program PER state */
235 cx = &omap3_idle_data[new_state_idx]; 256 cx = &omap3_idle_data[new_state_idx];
236 core_next_state = cx->core_state;
237 per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
238 if (new_state_idx == 0) {
239 /* In C1 do not allow PER state lower than CORE state */
240 if (per_next_state < core_next_state)
241 per_next_state = core_next_state;
242 } else {
243 /*
244 * Prevent PER OFF if CORE is not in RETention or OFF as this
245 * would disable PER wakeups completely.
246 */
247 if ((per_next_state == PWRDM_POWER_OFF) &&
248 (core_next_state > PWRDM_POWER_RET))
249 per_next_state = PWRDM_POWER_RET;
250 }
251 257
252 /* Are we changing PER target state? */ 258 per_next_state = pwrdm_read_next_pwrst(per_pd);
253 if (per_next_state != per_saved_state) 259 per_saved_state = per_next_state;
260 if (per_next_state < cx->per_min_state) {
261 per_next_state = cx->per_min_state;
254 pwrdm_set_next_pwrst(per_pd, per_next_state); 262 pwrdm_set_next_pwrst(per_pd, per_next_state);
263 }
255 264
256 ret = omap3_enter_idle(dev, drv, new_state_idx); 265 ret = omap3_enter_idle(dev, drv, new_state_idx);
257 266
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 626f3ea3142f..6ecc89adda87 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -61,8 +61,7 @@ static int __init omap3_l3_init(void)
61 if (!oh) 61 if (!oh)
62 pr_err("could not look up %s\n", oh_name); 62 pr_err("could not look up %s\n", oh_name);
63 63
64 pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0, 64 pdev = omap_device_build("omap_l3_smx", 0, oh, NULL, 0);
65 NULL, 0, 0);
66 65
67 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); 66 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
68 67
@@ -96,8 +95,7 @@ static int __init omap4_l3_init(void)
96 pr_err("could not look up %s\n", oh_name); 95 pr_err("could not look up %s\n", oh_name);
97 } 96 }
98 97
99 pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, 98 pdev = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL, 0);
100 0, NULL, 0, 0);
101 99
102 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); 100 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
103 101
@@ -273,7 +271,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
273 keypad_data = sdp4430_keypad_data; 271 keypad_data = sdp4430_keypad_data;
274 272
275 pdev = omap_device_build(name, id, oh, keypad_data, 273 pdev = omap_device_build(name, id, oh, keypad_data,
276 sizeof(struct omap4_keypad_platform_data), NULL, 0, 0); 274 sizeof(struct omap4_keypad_platform_data));
277 275
278 if (IS_ERR(pdev)) { 276 if (IS_ERR(pdev)) {
279 WARN(1, "Can't build omap_device for %s:%s.\n", 277 WARN(1, "Can't build omap_device for %s:%s.\n",
@@ -297,7 +295,7 @@ static inline void __init omap_init_mbox(void)
297 return; 295 return;
298 } 296 }
299 297
300 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0); 298 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0);
301 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n", 299 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
302 __func__, PTR_ERR(pdev)); 300 __func__, PTR_ERR(pdev));
303} 301}
@@ -337,7 +335,7 @@ static void __init omap_init_mcpdm(void)
337 return; 335 return;
338 } 336 }
339 337
340 pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0, NULL, 0, 0); 338 pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0);
341 WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n"); 339 WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
342} 340}
343#else 341#else
@@ -358,7 +356,7 @@ static void __init omap_init_dmic(void)
358 return; 356 return;
359 } 357 }
360 358
361 pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0); 359 pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0);
362 WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n"); 360 WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
363} 361}
364#else 362#else
@@ -384,8 +382,7 @@ static void __init omap_init_hdmi_audio(void)
384 return; 382 return;
385 } 383 }
386 384
387 pdev = omap_device_build("omap-hdmi-audio-dai", 385 pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0);
388 -1, oh, NULL, 0, NULL, 0, 0);
389 WARN(IS_ERR(pdev), 386 WARN(IS_ERR(pdev),
390 "Can't build omap_device for omap-hdmi-audio-dai.\n"); 387 "Can't build omap_device for omap-hdmi-audio-dai.\n");
391 388
@@ -429,8 +426,7 @@ static int __init omap_mcspi_init(struct omap_hwmod *oh, void *unused)
429 } 426 }
430 427
431 spi_num++; 428 spi_num++;
432 pdev = omap_device_build(name, spi_num, oh, pdata, 429 pdev = omap_device_build(name, spi_num, oh, pdata, sizeof(*pdata));
433 sizeof(*pdata), NULL, 0, 0);
434 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n", 430 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
435 name, oh->name); 431 name, oh->name);
436 kfree(pdata); 432 kfree(pdata);
@@ -460,7 +456,7 @@ static void omap_init_rng(void)
460 if (!oh) 456 if (!oh)
461 return; 457 return;
462 458
463 pdev = omap_device_build("omap_rng", -1, oh, NULL, 0, NULL, 0, 0); 459 pdev = omap_device_build("omap_rng", -1, oh, NULL, 0);
464 WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n"); 460 WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
465} 461}
466 462
@@ -689,8 +685,7 @@ static void __init omap_init_ocp2scp(void)
689 685
690 pdata->dev_cnt = dev_cnt; 686 pdata->dev_cnt = dev_cnt;
691 687
692 pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata), NULL, 688 pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata));
693 0, false);
694 if (IS_ERR(pdev)) { 689 if (IS_ERR(pdev)) {
695 pr_err("Could not build omap_device for %s %s\n", 690 pr_err("Could not build omap_device for %s %s\n",
696 name, oh_name); 691 name, oh_name);
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index cc75aaf6e764..ff37be1f6f93 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -226,7 +226,7 @@ static struct platform_device *create_dss_pdev(const char *pdev_name,
226 dev_set_name(&pdev->dev, "%s", pdev->name); 226 dev_set_name(&pdev->dev, "%s", pdev->name);
227 227
228 ohs[0] = oh; 228 ohs[0] = oh;
229 od = omap_device_alloc(pdev, ohs, 1, NULL, 0); 229 od = omap_device_alloc(pdev, ohs, 1);
230 if (IS_ERR(od)) { 230 if (IS_ERR(od)) {
231 pr_err("Could not alloc omap_device for %s\n", pdev_name); 231 pr_err("Could not alloc omap_device for %s\n", pdev_name);
232 r = -ENOMEM; 232 r = -ENOMEM;
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 612b98249873..491c5c8837fa 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -248,7 +248,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
248 248
249 p->errata = configure_dma_errata(); 249 p->errata = configure_dma_errata();
250 250
251 pdev = omap_device_build(name, 0, oh, p, sizeof(*p), NULL, 0, 0); 251 pdev = omap_device_build(name, 0, oh, p, sizeof(*p));
252 kfree(p); 252 kfree(p);
253 if (IS_ERR(pdev)) { 253 if (IS_ERR(pdev)) {
254 pr_err("%s: Can't build omap_device for %s:%s.\n", 254 pr_err("%s: Can't build omap_device for %s:%s.\n",
diff --git a/arch/arm/mach-omap2/drm.c b/arch/arm/mach-omap2/drm.c
index 2a2cfa88ddbf..4d8d1a52ffe7 100644
--- a/arch/arm/mach-omap2/drm.c
+++ b/arch/arm/mach-omap2/drm.c
@@ -51,8 +51,7 @@ static int __init omap_init_drm(void)
51 oh = omap_hwmod_lookup("dmm"); 51 oh = omap_hwmod_lookup("dmm");
52 52
53 if (oh) { 53 if (oh) {
54 pdev = omap_device_build(oh->name, -1, oh, NULL, 0, NULL, 0, 54 pdev = omap_device_build(oh->name, -1, oh, NULL, 0);
55 false);
56 WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", 55 WARN(IS_ERR(pdev), "Could not build omap_device for %s\n",
57 oh->name); 56 oh->name);
58 } 57 }
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 399acabc3d0b..482ade1923b0 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -131,8 +131,7 @@ static int __init omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
131 pwrdm = omap_hwmod_get_pwrdm(oh); 131 pwrdm = omap_hwmod_get_pwrdm(oh);
132 pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm); 132 pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
133 133
134 pdev = omap_device_build(name, id - 1, oh, pdata, 134 pdev = omap_device_build(name, id - 1, oh, pdata, sizeof(*pdata));
135 sizeof(*pdata), NULL, 0, false);
136 kfree(pdata); 135 kfree(pdata);
137 136
138 if (IS_ERR(pdev)) { 137 if (IS_ERR(pdev)) {
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 8033cb747c86..bc0783364ad3 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1220,7 +1220,7 @@ static int __init omap_gpmc_init(void)
1220 return -ENODEV; 1220 return -ENODEV;
1221 } 1221 }
1222 1222
1223 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0); 1223 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
1224 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); 1224 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
1225 1225
1226 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; 1226 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index ab7bf181a105..b7aa8ba2ccb2 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -87,7 +87,7 @@ static int __init omap_init_hdq(void)
87 if (!oh) 87 if (!oh)
88 return 0; 88 return 0;
89 89
90 pdev = omap_device_build(devname, id, oh, NULL, 0, NULL, 0, 0); 90 pdev = omap_device_build(devname, id, oh, NULL, 0);
91 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", 91 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
92 devname, oh->name); 92 devname, oh->name);
93 93
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 4a964338992a..2ef1f8714fcf 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -522,7 +522,7 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
522 } 522 }
523 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); 523 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
524 524
525 od = omap_device_alloc(pdev, ohs, 1, NULL, 0); 525 od = omap_device_alloc(pdev, ohs, 1);
526 if (IS_ERR(od)) { 526 if (IS_ERR(od)) {
527 pr_err("Could not allocate od for %s\n", name); 527 pr_err("Could not allocate od for %s\n", name);
528 goto put_pdev; 528 goto put_pdev;
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index 1df9b5feda16..c3688903f3d4 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -46,8 +46,7 @@ static int __init hwspinlocks_init(void)
46 return -EINVAL; 46 return -EINVAL;
47 47
48 pdev = omap_device_build(dev_name, 0, oh, &omap_hwspinlock_pdata, 48 pdev = omap_device_build(dev_name, 0, oh, &omap_hwspinlock_pdata,
49 sizeof(struct hwspinlock_pdata), 49 sizeof(struct hwspinlock_pdata));
50 NULL, 0, false);
51 if (IS_ERR(pdev)) { 50 if (IS_ERR(pdev)) {
52 pr_err("Can't build omap_device for %s:%s\n", dev_name, 51 pr_err("Can't build omap_device for %s:%s\n", dev_name,
53 oh_name); 52 oh_name);
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index b9074dde3b9c..c11a23fa9665 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -178,8 +178,7 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
178 if (cpu_is_omap34xx()) 178 if (cpu_is_omap34xx())
179 pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; 179 pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
180 pdev = omap_device_build(name, bus_id, oh, pdata, 180 pdev = omap_device_build(name, bus_id, oh, pdata,
181 sizeof(struct omap_i2c_bus_platform_data), 181 sizeof(struct omap_i2c_bus_platform_data));
182 NULL, 0, 0);
183 WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name); 182 WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
184 183
185 return PTR_RET(pdev); 184 return PTR_RET(pdev);
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index df49f2a49461..453580410ae0 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -101,7 +101,7 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
101 count++; 101 count++;
102 } 102 }
103 pdev = omap_device_build_ss(name, id, oh_device, count, pdata, 103 pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
104 sizeof(*pdata), NULL, 0, false); 104 sizeof(*pdata));
105 kfree(pdata); 105 kfree(pdata);
106 if (IS_ERR(pdev)) { 106 if (IS_ERR(pdev)) {
107 pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, 107 pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index aafdd4ca9f4f..c52d8b4a3e91 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -150,7 +150,7 @@ void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
150 return; 150 return;
151 } 151 }
152 pdev = omap_device_build(dev_name, id, oh, mmc_data[0], 152 pdev = omap_device_build(dev_name, id, oh, mmc_data[0],
153 sizeof(struct omap_mmc_platform_data), NULL, 0, 0); 153 sizeof(struct omap_mmc_platform_data));
154 if (IS_ERR(pdev)) 154 if (IS_ERR(pdev))
155 WARN(1, "Can'd build omap_device for %s:%s.\n", 155 WARN(1, "Can'd build omap_device for %s:%s.\n",
156 dev_name, oh->name); 156 dev_name, oh->name);
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 6da4f7ae9d7f..f7f38c7fd5ff 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -41,8 +41,7 @@ static int __init omap_iommu_dev_init(struct omap_hwmod *oh, void *unused)
41 pdata->deassert_reset = omap_device_deassert_hardreset; 41 pdata->deassert_reset = omap_device_deassert_hardreset;
42 } 42 }
43 43
44 pdev = omap_device_build("omap-iommu", i, oh, pdata, sizeof(*pdata), 44 pdev = omap_device_build("omap-iommu", i, oh, pdata, sizeof(*pdata));
45 NULL, 0, 0);
46 45
47 kfree(pdata); 46 kfree(pdata);
48 47
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index aac46bfdbeb2..8bcb64bcdcdb 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -87,37 +87,6 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
87} 87}
88 88
89/* 89/*
90 * Set the CPUx powerdomain's previous power state
91 */
92static inline void set_cpu_next_pwrst(unsigned int cpu_id,
93 unsigned int power_state)
94{
95 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
96
97 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
98}
99
100/*
101 * Read CPU's previous power state
102 */
103static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
104{
105 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
106
107 return pwrdm_read_prev_pwrst(pm_info->pwrdm);
108}
109
110/*
111 * Clear the CPUx powerdomain's previous power state
112 */
113static inline void clear_cpu_prev_pwrst(unsigned int cpu_id)
114{
115 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
116
117 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
118}
119
120/*
121 * Store the SCU power status value to scratchpad memory 90 * Store the SCU power status value to scratchpad memory
122 */ 91 */
123static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state) 92static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
@@ -230,6 +199,7 @@ static void save_l2x0_context(void)
230 */ 199 */
231int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) 200int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
232{ 201{
202 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
233 unsigned int save_state = 0; 203 unsigned int save_state = 0;
234 unsigned int wakeup_cpu; 204 unsigned int wakeup_cpu;
235 205
@@ -268,7 +238,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
268 save_state = 2; 238 save_state = 2;
269 239
270 cpu_clear_prev_logic_pwrst(cpu); 240 cpu_clear_prev_logic_pwrst(cpu);
271 set_cpu_next_pwrst(cpu, power_state); 241 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
272 set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume)); 242 set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
273 scu_pwrst_prepare(cpu, power_state); 243 scu_pwrst_prepare(cpu, power_state);
274 l2x0_pwrst_prepare(cpu, save_state); 244 l2x0_pwrst_prepare(cpu, save_state);
@@ -286,7 +256,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
286 * domain transition 256 * domain transition
287 */ 257 */
288 wakeup_cpu = smp_processor_id(); 258 wakeup_cpu = smp_processor_id();
289 set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON); 259 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
290 260
291 pwrdm_post_transition(NULL); 261 pwrdm_post_transition(NULL);
292 262
@@ -300,8 +270,8 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
300 */ 270 */
301int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) 271int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
302{ 272{
303 unsigned int cpu_state = 0;
304 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu); 273 struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
274 unsigned int cpu_state = 0;
305 275
306 if (omap_rev() == OMAP4430_REV_ES1_0) 276 if (omap_rev() == OMAP4430_REV_ES1_0)
307 return -ENXIO; 277 return -ENXIO;
@@ -309,8 +279,8 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
309 if (power_state == PWRDM_POWER_OFF) 279 if (power_state == PWRDM_POWER_OFF)
310 cpu_state = 1; 280 cpu_state = 1;
311 281
312 clear_cpu_prev_pwrst(cpu); 282 pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
313 set_cpu_next_pwrst(cpu, power_state); 283 pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
314 set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup)); 284 set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
315 scu_pwrst_prepare(cpu, power_state); 285 scu_pwrst_prepare(cpu, power_state);
316 286
@@ -321,7 +291,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
321 */ 291 */
322 omap4_finish_suspend(cpu_state); 292 omap4_finish_suspend(cpu_state);
323 293
324 set_cpu_next_pwrst(cpu, PWRDM_POWER_ON); 294 pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
325 return 0; 295 return 0;
326} 296}
327 297
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index e065daa537c0..6ee3ad3dd95a 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -17,68 +17,15 @@
17 * to control power management and interconnect properties of their 17 * to control power management and interconnect properties of their
18 * devices. 18 * devices.
19 * 19 *
20 * In the medium- to long-term, this code should either be 20 * In the medium- to long-term, this code should be implemented as a
21 * a) implemented via arch-specific pointers in platform_data 21 * proper omap_bus/omap_device in Linux, no more platform_data func
22 * or 22 * pointers
23 * b) implemented as a proper omap_bus/omap_device in Linux, no more
24 * platform_data func pointers
25 * 23 *
26 * 24 *
27 * Guidelines for usage by driver authors:
28 *
29 * 1. These functions are intended to be used by device drivers via
30 * function pointers in struct platform_data. As an example,
31 * omap_device_enable() should be passed to the driver as
32 *
33 * struct foo_driver_platform_data {
34 * ...
35 * int (*device_enable)(struct platform_device *pdev);
36 * ...
37 * }
38 *
39 * Note that the generic "device_enable" name is used, rather than
40 * "omap_device_enable". This is so other architectures can pass in their
41 * own enable/disable functions here.
42 *
43 * This should be populated during device setup:
44 *
45 * ...
46 * pdata->device_enable = omap_device_enable;
47 * ...
48 *
49 * 2. Drivers should first check to ensure the function pointer is not null
50 * before calling it, as in:
51 *
52 * if (pdata->device_enable)
53 * pdata->device_enable(pdev);
54 *
55 * This allows other architectures that don't use similar device_enable()/
56 * device_shutdown() functions to execute normally.
57 *
58 * ...
59 *
60 * Suggested usage by device drivers:
61 *
62 * During device initialization:
63 * device_enable()
64 *
65 * During device idle:
66 * (save remaining device context if necessary)
67 * device_idle();
68 *
69 * During device resume:
70 * device_enable();
71 * (restore context if necessary)
72 *
73 * During device shutdown:
74 * device_shutdown()
75 * (device must be reinitialized at this point to use it again)
76 *
77 */ 25 */
78#undef DEBUG 26#undef DEBUG
79 27
80#include <linux/kernel.h> 28#include <linux/kernel.h>
81#include <linux/export.h>
82#include <linux/platform_device.h> 29#include <linux/platform_device.h>
83#include <linux/slab.h> 30#include <linux/slab.h>
84#include <linux/err.h> 31#include <linux/err.h>
@@ -92,155 +39,8 @@
92#include "omap_device.h" 39#include "omap_device.h"
93#include "omap_hwmod.h" 40#include "omap_hwmod.h"
94 41
95/* These parameters are passed to _omap_device_{de,}activate() */
96#define USE_WAKEUP_LAT 0
97#define IGNORE_WAKEUP_LAT 1
98
99static int omap_early_device_register(struct platform_device *pdev);
100
101static struct omap_device_pm_latency omap_default_latency[] = {
102 {
103 .deactivate_func = omap_device_idle_hwmods,
104 .activate_func = omap_device_enable_hwmods,
105 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
106 }
107};
108
109/* Private functions */ 42/* Private functions */
110 43
111/**
112 * _omap_device_activate - increase device readiness
113 * @od: struct omap_device *
114 * @ignore_lat: increase to latency target (0) or full readiness (1)?
115 *
116 * Increase readiness of omap_device @od (thus decreasing device
117 * wakeup latency, but consuming more power). If @ignore_lat is
118 * IGNORE_WAKEUP_LAT, make the omap_device fully active. Otherwise,
119 * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
120 * latency is greater than the requested maximum wakeup latency, step
121 * backwards in the omap_device_pm_latency table to ensure the
122 * device's maximum wakeup latency is less than or equal to the
123 * requested maximum wakeup latency. Returns 0.
124 */
125static int _omap_device_activate(struct omap_device *od, u8 ignore_lat)
126{
127 struct timespec a, b, c;
128
129 dev_dbg(&od->pdev->dev, "omap_device: activating\n");
130
131 while (od->pm_lat_level > 0) {
132 struct omap_device_pm_latency *odpl;
133 unsigned long long act_lat = 0;
134
135 od->pm_lat_level--;
136
137 odpl = od->pm_lats + od->pm_lat_level;
138
139 if (!ignore_lat &&
140 (od->dev_wakeup_lat <= od->_dev_wakeup_lat_limit))
141 break;
142
143 read_persistent_clock(&a);
144
145 /* XXX check return code */
146 odpl->activate_func(od);
147
148 read_persistent_clock(&b);
149
150 c = timespec_sub(b, a);
151 act_lat = timespec_to_ns(&c);
152
153 dev_dbg(&od->pdev->dev,
154 "omap_device: pm_lat %d: activate: elapsed time %llu nsec\n",
155 od->pm_lat_level, act_lat);
156
157 if (act_lat > odpl->activate_lat) {
158 odpl->activate_lat_worst = act_lat;
159 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
160 odpl->activate_lat = act_lat;
161 dev_dbg(&od->pdev->dev,
162 "new worst case activate latency %d: %llu\n",
163 od->pm_lat_level, act_lat);
164 } else
165 dev_warn(&od->pdev->dev,
166 "activate latency %d higher than expected. (%llu > %d)\n",
167 od->pm_lat_level, act_lat,
168 odpl->activate_lat);
169 }
170
171 od->dev_wakeup_lat -= odpl->activate_lat;
172 }
173
174 return 0;
175}
176
177/**
178 * _omap_device_deactivate - decrease device readiness
179 * @od: struct omap_device *
180 * @ignore_lat: decrease to latency target (0) or full inactivity (1)?
181 *
182 * Decrease readiness of omap_device @od (thus increasing device
183 * wakeup latency, but conserving power). If @ignore_lat is
184 * IGNORE_WAKEUP_LAT, make the omap_device fully inactive. Otherwise,
185 * if @ignore_lat is USE_WAKEUP_LAT, and the device's maximum wakeup
186 * latency is less than the requested maximum wakeup latency, step
187 * forwards in the omap_device_pm_latency table to ensure the device's
188 * maximum wakeup latency is less than or equal to the requested
189 * maximum wakeup latency. Returns 0.
190 */
191static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
192{
193 struct timespec a, b, c;
194
195 dev_dbg(&od->pdev->dev, "omap_device: deactivating\n");
196
197 while (od->pm_lat_level < od->pm_lats_cnt) {
198 struct omap_device_pm_latency *odpl;
199 unsigned long long deact_lat = 0;
200
201 odpl = od->pm_lats + od->pm_lat_level;
202
203 if (!ignore_lat &&
204 ((od->dev_wakeup_lat + odpl->activate_lat) >
205 od->_dev_wakeup_lat_limit))
206 break;
207
208 read_persistent_clock(&a);
209
210 /* XXX check return code */
211 odpl->deactivate_func(od);
212
213 read_persistent_clock(&b);
214
215 c = timespec_sub(b, a);
216 deact_lat = timespec_to_ns(&c);
217
218 dev_dbg(&od->pdev->dev,
219 "omap_device: pm_lat %d: deactivate: elapsed time %llu nsec\n",
220 od->pm_lat_level, deact_lat);
221
222 if (deact_lat > odpl->deactivate_lat) {
223 odpl->deactivate_lat_worst = deact_lat;
224 if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
225 odpl->deactivate_lat = deact_lat;
226 dev_dbg(&od->pdev->dev,
227 "new worst case deactivate latency %d: %llu\n",
228 od->pm_lat_level, deact_lat);
229 } else
230 dev_warn(&od->pdev->dev,
231 "deactivate latency %d higher than expected. (%llu > %d)\n",
232 od->pm_lat_level, deact_lat,
233 odpl->deactivate_lat);
234 }
235
236 od->dev_wakeup_lat += odpl->activate_lat;
237
238 od->pm_lat_level++;
239 }
240
241 return 0;
242}
243
244static void _add_clkdev(struct omap_device *od, const char *clk_alias, 44static void _add_clkdev(struct omap_device *od, const char *clk_alias,
245 const char *clk_name) 45 const char *clk_name)
246{ 46{
@@ -315,9 +115,6 @@ static void _add_hwmod_clocks_clkdev(struct omap_device *od,
315 * @oh: ptr to the single omap_hwmod that backs this omap_device 115 * @oh: ptr to the single omap_hwmod that backs this omap_device
316 * @pdata: platform_data ptr to associate with the platform_device 116 * @pdata: platform_data ptr to associate with the platform_device
317 * @pdata_len: amount of memory pointed to by @pdata 117 * @pdata_len: amount of memory pointed to by @pdata
318 * @pm_lats: pointer to a omap_device_pm_latency array for this device
319 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
320 * @is_early_device: should the device be registered as an early device or not
321 * 118 *
322 * Function for building an omap_device already registered from device-tree 119 * Function for building an omap_device already registered from device-tree
323 * 120 *
@@ -356,7 +153,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
356 hwmods[i] = oh; 153 hwmods[i] = oh;
357 } 154 }
358 155
359 od = omap_device_alloc(pdev, hwmods, oh_cnt, NULL, 0); 156 od = omap_device_alloc(pdev, hwmods, oh_cnt);
360 if (!od) { 157 if (!od) {
361 dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n", 158 dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n",
362 oh_name); 159 oh_name);
@@ -407,6 +204,39 @@ static int _omap_device_notifier_call(struct notifier_block *nb,
407 return NOTIFY_DONE; 204 return NOTIFY_DONE;
408} 205}
409 206
207/**
208 * _omap_device_enable_hwmods - call omap_hwmod_enable() on all hwmods
209 * @od: struct omap_device *od
210 *
211 * Enable all underlying hwmods. Returns 0.
212 */
213static int _omap_device_enable_hwmods(struct omap_device *od)
214{
215 int i;
216
217 for (i = 0; i < od->hwmods_cnt; i++)
218 omap_hwmod_enable(od->hwmods[i]);
219
220 /* XXX pass along return value here? */
221 return 0;
222}
223
224/**
225 * _omap_device_idle_hwmods - call omap_hwmod_idle() on all hwmods
226 * @od: struct omap_device *od
227 *
228 * Idle all underlying hwmods. Returns 0.
229 */
230static int _omap_device_idle_hwmods(struct omap_device *od)
231{
232 int i;
233
234 for (i = 0; i < od->hwmods_cnt; i++)
235 omap_hwmod_idle(od->hwmods[i]);
236
237 /* XXX pass along return value here? */
238 return 0;
239}
410 240
411/* Public functions for use by core code */ 241/* Public functions for use by core code */
412 242
@@ -526,18 +356,14 @@ static int _od_fill_dma_resources(struct omap_device *od,
526 * @oh: ptr to the single omap_hwmod that backs this omap_device 356 * @oh: ptr to the single omap_hwmod that backs this omap_device
527 * @pdata: platform_data ptr to associate with the platform_device 357 * @pdata: platform_data ptr to associate with the platform_device
528 * @pdata_len: amount of memory pointed to by @pdata 358 * @pdata_len: amount of memory pointed to by @pdata
529 * @pm_lats: pointer to a omap_device_pm_latency array for this device
530 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
531 * 359 *
532 * Convenience function for allocating an omap_device structure and filling 360 * Convenience function for allocating an omap_device structure and filling
533 * hwmods, resources and pm_latency attributes. 361 * hwmods, and resources.
534 * 362 *
535 * Returns an struct omap_device pointer or ERR_PTR() on error; 363 * Returns an struct omap_device pointer or ERR_PTR() on error;
536 */ 364 */
537struct omap_device *omap_device_alloc(struct platform_device *pdev, 365struct omap_device *omap_device_alloc(struct platform_device *pdev,
538 struct omap_hwmod **ohs, int oh_cnt, 366 struct omap_hwmod **ohs, int oh_cnt)
539 struct omap_device_pm_latency *pm_lats,
540 int pm_lats_cnt)
541{ 367{
542 int ret = -ENOMEM; 368 int ret = -ENOMEM;
543 struct omap_device *od; 369 struct omap_device *od;
@@ -626,18 +452,6 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
626 goto oda_exit3; 452 goto oda_exit3;
627 453
628have_everything: 454have_everything:
629 if (!pm_lats) {
630 pm_lats = omap_default_latency;
631 pm_lats_cnt = ARRAY_SIZE(omap_default_latency);
632 }
633
634 od->pm_lats_cnt = pm_lats_cnt;
635 od->pm_lats = kmemdup(pm_lats,
636 sizeof(struct omap_device_pm_latency) * pm_lats_cnt,
637 GFP_KERNEL);
638 if (!od->pm_lats)
639 goto oda_exit3;
640
641 pdev->archdata.od = od; 455 pdev->archdata.od = od;
642 456
643 for (i = 0; i < oh_cnt; i++) { 457 for (i = 0; i < oh_cnt; i++) {
@@ -663,7 +477,6 @@ void omap_device_delete(struct omap_device *od)
663 return; 477 return;
664 478
665 od->pdev->archdata.od = NULL; 479 od->pdev->archdata.od = NULL;
666 kfree(od->pm_lats);
667 kfree(od->hwmods); 480 kfree(od->hwmods);
668 kfree(od); 481 kfree(od);
669} 482}
@@ -675,9 +488,6 @@ void omap_device_delete(struct omap_device *od)
675 * @oh: ptr to the single omap_hwmod that backs this omap_device 488 * @oh: ptr to the single omap_hwmod that backs this omap_device
676 * @pdata: platform_data ptr to associate with the platform_device 489 * @pdata: platform_data ptr to associate with the platform_device
677 * @pdata_len: amount of memory pointed to by @pdata 490 * @pdata_len: amount of memory pointed to by @pdata
678 * @pm_lats: pointer to a omap_device_pm_latency array for this device
679 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
680 * @is_early_device: should the device be registered as an early device or not
681 * 491 *
682 * Convenience function for building and registering a single 492 * Convenience function for building and registering a single
683 * omap_device record, which in turn builds and registers a 493 * omap_device record, which in turn builds and registers a
@@ -685,11 +495,10 @@ void omap_device_delete(struct omap_device *od)
685 * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise, 495 * information. Returns ERR_PTR(-EINVAL) if @oh is NULL; otherwise,
686 * passes along the return value of omap_device_build_ss(). 496 * passes along the return value of omap_device_build_ss().
687 */ 497 */
688struct platform_device __init *omap_device_build(const char *pdev_name, int pdev_id, 498struct platform_device __init *omap_device_build(const char *pdev_name,
689 struct omap_hwmod *oh, void *pdata, 499 int pdev_id,
690 int pdata_len, 500 struct omap_hwmod *oh,
691 struct omap_device_pm_latency *pm_lats, 501 void *pdata, int pdata_len)
692 int pm_lats_cnt, int is_early_device)
693{ 502{
694 struct omap_hwmod *ohs[] = { oh }; 503 struct omap_hwmod *ohs[] = { oh };
695 504
@@ -697,8 +506,7 @@ struct platform_device __init *omap_device_build(const char *pdev_name, int pdev
697 return ERR_PTR(-EINVAL); 506 return ERR_PTR(-EINVAL);
698 507
699 return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata, 508 return omap_device_build_ss(pdev_name, pdev_id, ohs, 1, pdata,
700 pdata_len, pm_lats, pm_lats_cnt, 509 pdata_len);
701 is_early_device);
702} 510}
703 511
704/** 512/**
@@ -708,9 +516,6 @@ struct platform_device __init *omap_device_build(const char *pdev_name, int pdev
708 * @oh: ptr to the single omap_hwmod that backs this omap_device 516 * @oh: ptr to the single omap_hwmod that backs this omap_device
709 * @pdata: platform_data ptr to associate with the platform_device 517 * @pdata: platform_data ptr to associate with the platform_device
710 * @pdata_len: amount of memory pointed to by @pdata 518 * @pdata_len: amount of memory pointed to by @pdata
711 * @pm_lats: pointer to a omap_device_pm_latency array for this device
712 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
713 * @is_early_device: should the device be registered as an early device or not
714 * 519 *
715 * Convenience function for building and registering an omap_device 520 * Convenience function for building and registering an omap_device
716 * subsystem record. Subsystem records consist of multiple 521 * subsystem record. Subsystem records consist of multiple
@@ -718,11 +523,11 @@ struct platform_device __init *omap_device_build(const char *pdev_name, int pdev
718 * platform_device record. Returns an ERR_PTR() on error, or passes 523 * platform_device record. Returns an ERR_PTR() on error, or passes
719 * along the return value of omap_device_register(). 524 * along the return value of omap_device_register().
720 */ 525 */
721struct platform_device __init *omap_device_build_ss(const char *pdev_name, int pdev_id, 526struct platform_device __init *omap_device_build_ss(const char *pdev_name,
722 struct omap_hwmod **ohs, int oh_cnt, 527 int pdev_id,
723 void *pdata, int pdata_len, 528 struct omap_hwmod **ohs,
724 struct omap_device_pm_latency *pm_lats, 529 int oh_cnt, void *pdata,
725 int pm_lats_cnt, int is_early_device) 530 int pdata_len)
726{ 531{
727 int ret = -ENOMEM; 532 int ret = -ENOMEM;
728 struct platform_device *pdev; 533 struct platform_device *pdev;
@@ -746,7 +551,7 @@ struct platform_device __init *omap_device_build_ss(const char *pdev_name, int p
746 else 551 else
747 dev_set_name(&pdev->dev, "%s", pdev->name); 552 dev_set_name(&pdev->dev, "%s", pdev->name);
748 553
749 od = omap_device_alloc(pdev, ohs, oh_cnt, pm_lats, pm_lats_cnt); 554 od = omap_device_alloc(pdev, ohs, oh_cnt);
750 if (IS_ERR(od)) 555 if (IS_ERR(od))
751 goto odbs_exit1; 556 goto odbs_exit1;
752 557
@@ -754,10 +559,7 @@ struct platform_device __init *omap_device_build_ss(const char *pdev_name, int p
754 if (ret) 559 if (ret)
755 goto odbs_exit2; 560 goto odbs_exit2;
756 561
757 if (is_early_device) 562 ret = omap_device_register(pdev);
758 ret = omap_early_device_register(pdev);
759 else
760 ret = omap_device_register(pdev);
761 if (ret) 563 if (ret)
762 goto odbs_exit2; 564 goto odbs_exit2;
763 565
@@ -774,24 +576,6 @@ odbs_exit:
774 return ERR_PTR(ret); 576 return ERR_PTR(ret);
775} 577}
776 578
777/**
778 * omap_early_device_register - register an omap_device as an early platform
779 * device.
780 * @od: struct omap_device * to register
781 *
782 * Register the omap_device structure. This currently just calls
783 * platform_early_add_device() on the underlying platform_device.
784 * Returns 0 by default.
785 */
786static int __init omap_early_device_register(struct platform_device *pdev)
787{
788 struct platform_device *devices[1];
789
790 devices[0] = pdev;
791 early_platform_add_devices(devices, 1);
792 return 0;
793}
794
795#ifdef CONFIG_PM_RUNTIME 579#ifdef CONFIG_PM_RUNTIME
796static int _od_runtime_suspend(struct device *dev) 580static int _od_runtime_suspend(struct device *dev)
797{ 581{
@@ -902,10 +686,9 @@ int omap_device_register(struct platform_device *pdev)
902 * to be accessible and ready to operate. This generally involves 686 * to be accessible and ready to operate. This generally involves
903 * enabling clocks, setting SYSCONFIG registers; and in the future may 687 * enabling clocks, setting SYSCONFIG registers; and in the future may
904 * involve remuxing pins. Device drivers should call this function 688 * involve remuxing pins. Device drivers should call this function
905 * (through platform_data function pointers) where they would normally 689 * indirectly via pm_runtime_get*(). Returns -EINVAL if called when
906 * enable clocks, etc. Returns -EINVAL if called when the omap_device 690 * the omap_device is already enabled, or passes along the return
907 * is already enabled, or passes along the return value of 691 * value of _omap_device_enable_hwmods().
908 * _omap_device_activate().
909 */ 692 */
910int omap_device_enable(struct platform_device *pdev) 693int omap_device_enable(struct platform_device *pdev)
911{ 694{
@@ -921,14 +704,8 @@ int omap_device_enable(struct platform_device *pdev)
921 return -EINVAL; 704 return -EINVAL;
922 } 705 }
923 706
924 /* Enable everything if we're enabling this device from scratch */ 707 ret = _omap_device_enable_hwmods(od);
925 if (od->_state == OMAP_DEVICE_STATE_UNKNOWN)
926 od->pm_lat_level = od->pm_lats_cnt;
927
928 ret = _omap_device_activate(od, IGNORE_WAKEUP_LAT);
929 708
930 od->dev_wakeup_lat = 0;
931 od->_dev_wakeup_lat_limit = UINT_MAX;
932 od->_state = OMAP_DEVICE_STATE_ENABLED; 709 od->_state = OMAP_DEVICE_STATE_ENABLED;
933 710
934 return ret; 711 return ret;
@@ -938,14 +715,10 @@ int omap_device_enable(struct platform_device *pdev)
938 * omap_device_idle - idle an omap_device 715 * omap_device_idle - idle an omap_device
939 * @od: struct omap_device * to idle 716 * @od: struct omap_device * to idle
940 * 717 *
941 * Idle omap_device @od by calling as many .deactivate_func() entries 718 * Idle omap_device @od. Device drivers call this function indirectly
942 * in the omap_device's pm_lats table as is possible without exceeding 719 * via pm_runtime_put*(). Returns -EINVAL if the omap_device is not
943 * the device's maximum wakeup latency limit, pm_lat_limit. Device
944 * drivers should call this function (through platform_data function
945 * pointers) where they would normally disable clocks after operations
946 * complete, etc.. Returns -EINVAL if the omap_device is not
947 * currently enabled, or passes along the return value of 720 * currently enabled, or passes along the return value of
948 * _omap_device_deactivate(). 721 * _omap_device_idle_hwmods().
949 */ 722 */
950int omap_device_idle(struct platform_device *pdev) 723int omap_device_idle(struct platform_device *pdev)
951{ 724{
@@ -961,7 +734,7 @@ int omap_device_idle(struct platform_device *pdev)
961 return -EINVAL; 734 return -EINVAL;
962 } 735 }
963 736
964 ret = _omap_device_deactivate(od, USE_WAKEUP_LAT); 737 ret = _omap_device_idle_hwmods(od);
965 738
966 od->_state = OMAP_DEVICE_STATE_IDLE; 739 od->_state = OMAP_DEVICE_STATE_IDLE;
967 740
@@ -969,42 +742,6 @@ int omap_device_idle(struct platform_device *pdev)
969} 742}
970 743
971/** 744/**
972 * omap_device_shutdown - shut down an omap_device
973 * @od: struct omap_device * to shut down
974 *
975 * Shut down omap_device @od by calling all .deactivate_func() entries
976 * in the omap_device's pm_lats table and then shutting down all of
977 * the underlying omap_hwmods. Used when a device is being "removed"
978 * or a device driver is being unloaded. Returns -EINVAL if the
979 * omap_device is not currently enabled or idle, or passes along the
980 * return value of _omap_device_deactivate().
981 */
982int omap_device_shutdown(struct platform_device *pdev)
983{
984 int ret, i;
985 struct omap_device *od;
986
987 od = to_omap_device(pdev);
988
989 if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
990 od->_state != OMAP_DEVICE_STATE_IDLE) {
991 dev_warn(&pdev->dev,
992 "omap_device: %s() called from invalid state %d\n",
993 __func__, od->_state);
994 return -EINVAL;
995 }
996
997 ret = _omap_device_deactivate(od, IGNORE_WAKEUP_LAT);
998
999 for (i = 0; i < od->hwmods_cnt; i++)
1000 omap_hwmod_shutdown(od->hwmods[i]);
1001
1002 od->_state = OMAP_DEVICE_STATE_SHUTDOWN;
1003
1004 return ret;
1005}
1006
1007/**
1008 * omap_device_assert_hardreset - set a device's hardreset line 745 * omap_device_assert_hardreset - set a device's hardreset line
1009 * @pdev: struct platform_device * to reset 746 * @pdev: struct platform_device * to reset
1010 * @name: const char * name of the reset line 747 * @name: const char * name of the reset line
@@ -1060,86 +797,6 @@ int omap_device_deassert_hardreset(struct platform_device *pdev,
1060} 797}
1061 798
1062/** 799/**
1063 * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim
1064 * @od: struct omap_device *
1065 *
1066 * When a device's maximum wakeup latency limit changes, call some of
1067 * the .activate_func or .deactivate_func function pointers in the
1068 * omap_device's pm_lats array to ensure that the device's maximum
1069 * wakeup latency is less than or equal to the new latency limit.
1070 * Intended to be called by OMAP PM code whenever a device's maximum
1071 * wakeup latency limit changes (e.g., via
1072 * omap_pm_set_dev_wakeup_lat()). Returns 0 if nothing needs to be
1073 * done (e.g., if the omap_device is not currently idle, or if the
1074 * wakeup latency is already current with the new limit) or passes
1075 * along the return value of _omap_device_deactivate() or
1076 * _omap_device_activate().
1077 */
1078int omap_device_align_pm_lat(struct platform_device *pdev,
1079 u32 new_wakeup_lat_limit)
1080{
1081 int ret = -EINVAL;
1082 struct omap_device *od;
1083
1084 od = to_omap_device(pdev);
1085
1086 if (new_wakeup_lat_limit == od->dev_wakeup_lat)
1087 return 0;
1088
1089 od->_dev_wakeup_lat_limit = new_wakeup_lat_limit;
1090
1091 if (od->_state != OMAP_DEVICE_STATE_IDLE)
1092 return 0;
1093 else if (new_wakeup_lat_limit > od->dev_wakeup_lat)
1094 ret = _omap_device_deactivate(od, USE_WAKEUP_LAT);
1095 else if (new_wakeup_lat_limit < od->dev_wakeup_lat)
1096 ret = _omap_device_activate(od, USE_WAKEUP_LAT);
1097
1098 return ret;
1099}
1100
1101/**
1102 * omap_device_get_pwrdm - return the powerdomain * associated with @od
1103 * @od: struct omap_device *
1104 *
1105 * Return the powerdomain associated with the first underlying
1106 * omap_hwmod for this omap_device. Intended for use by core OMAP PM
1107 * code. Returns NULL on error or a struct powerdomain * upon
1108 * success.
1109 */
1110struct powerdomain *omap_device_get_pwrdm(struct omap_device *od)
1111{
1112 /*
1113 * XXX Assumes that all omap_hwmod powerdomains are identical.
1114 * This may not necessarily be true. There should be a sanity
1115 * check in here to WARN() if any difference appears.
1116 */
1117 if (!od->hwmods_cnt)
1118 return NULL;
1119
1120 return omap_hwmod_get_pwrdm(od->hwmods[0]);
1121}
1122
1123/**
1124 * omap_device_get_mpu_rt_va - return the MPU's virtual addr for the hwmod base
1125 * @od: struct omap_device *
1126 *
1127 * Return the MPU's virtual address for the base of the hwmod, from
1128 * the ioremap() that the hwmod code does. Only valid if there is one
1129 * hwmod associated with this device. Returns NULL if there are zero
1130 * or more than one hwmods associated with this omap_device;
1131 * otherwise, passes along the return value from
1132 * omap_hwmod_get_mpu_rt_va().
1133 */
1134void __iomem *omap_device_get_rt_va(struct omap_device *od)
1135{
1136 if (od->hwmods_cnt != 1)
1137 return NULL;
1138
1139 return omap_hwmod_get_mpu_rt_va(od->hwmods[0]);
1140}
1141
1142/**
1143 * omap_device_get_by_hwmod_name() - convert a hwmod name to 800 * omap_device_get_by_hwmod_name() - convert a hwmod name to
1144 * device pointer. 801 * device pointer.
1145 * @oh_name: name of the hwmod device 802 * @oh_name: name of the hwmod device
@@ -1173,82 +830,6 @@ struct device *omap_device_get_by_hwmod_name(const char *oh_name)
1173 830
1174 return &oh->od->pdev->dev; 831 return &oh->od->pdev->dev;
1175} 832}
1176EXPORT_SYMBOL(omap_device_get_by_hwmod_name);
1177
1178/*
1179 * Public functions intended for use in omap_device_pm_latency
1180 * .activate_func and .deactivate_func function pointers
1181 */
1182
1183/**
1184 * omap_device_enable_hwmods - call omap_hwmod_enable() on all hwmods
1185 * @od: struct omap_device *od
1186 *
1187 * Enable all underlying hwmods. Returns 0.
1188 */
1189int omap_device_enable_hwmods(struct omap_device *od)
1190{
1191 int i;
1192
1193 for (i = 0; i < od->hwmods_cnt; i++)
1194 omap_hwmod_enable(od->hwmods[i]);
1195
1196 /* XXX pass along return value here? */
1197 return 0;
1198}
1199
1200/**
1201 * omap_device_idle_hwmods - call omap_hwmod_idle() on all hwmods
1202 * @od: struct omap_device *od
1203 *
1204 * Idle all underlying hwmods. Returns 0.
1205 */
1206int omap_device_idle_hwmods(struct omap_device *od)
1207{
1208 int i;
1209
1210 for (i = 0; i < od->hwmods_cnt; i++)
1211 omap_hwmod_idle(od->hwmods[i]);
1212
1213 /* XXX pass along return value here? */
1214 return 0;
1215}
1216
1217/**
1218 * omap_device_disable_clocks - disable all main and interface clocks
1219 * @od: struct omap_device *od
1220 *
1221 * Disable the main functional clock and interface clock for all of the
1222 * omap_hwmods associated with the omap_device. Returns 0.
1223 */
1224int omap_device_disable_clocks(struct omap_device *od)
1225{
1226 int i;
1227
1228 for (i = 0; i < od->hwmods_cnt; i++)
1229 omap_hwmod_disable_clocks(od->hwmods[i]);
1230
1231 /* XXX pass along return value here? */
1232 return 0;
1233}
1234
1235/**
1236 * omap_device_enable_clocks - enable all main and interface clocks
1237 * @od: struct omap_device *od
1238 *
1239 * Enable the main functional clock and interface clock for all of the
1240 * omap_hwmods associated with the omap_device. Returns 0.
1241 */
1242int omap_device_enable_clocks(struct omap_device *od)
1243{
1244 int i;
1245
1246 for (i = 0; i < od->hwmods_cnt; i++)
1247 omap_hwmod_enable_clocks(od->hwmods[i]);
1248
1249 /* XXX pass along return value here? */
1250 return 0;
1251}
1252 833
1253static struct notifier_block platform_nb = { 834static struct notifier_block platform_nb = {
1254 .notifier_call = _omap_device_notifier_call, 835 .notifier_call = _omap_device_notifier_call,
diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h
index 0933c599bf89..044c31d50e5b 100644
--- a/arch/arm/mach-omap2/omap_device.h
+++ b/arch/arm/mach-omap2/omap_device.h
@@ -13,20 +13,12 @@
13 * it under the terms of the GNU General Public License version 2 as 13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 * 15 *
16 * Eventually this type of functionality should either be 16 * This type of functionality should be implemented as a proper
17 * a) implemented via arch-specific pointers in platform_device 17 * omap_bus/omap_device in Linux.
18 * or
19 * b) implemented as a proper omap_bus/omap_device in Linux, no more
20 * platform_device
21 * 18 *
22 * omap_device differs from omap_hwmod in that it includes external 19 * omap_device differs from omap_hwmod in that it includes external
23 * (e.g., board- and system-level) integration details. omap_hwmod 20 * (e.g., board- and system-level) integration details. omap_hwmod
24 * stores hardware data that is invariant for a given OMAP chip. 21 * stores hardware data that is invariant for a given OMAP chip.
25 *
26 * To do:
27 * - GPIO integration
28 * - regulator integration
29 *
30 */ 22 */
31#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H 23#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
32#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H 24#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_DEVICE_H
@@ -45,19 +37,14 @@ extern struct dev_pm_domain omap_device_pm_domain;
45#define OMAP_DEVICE_STATE_SHUTDOWN 3 37#define OMAP_DEVICE_STATE_SHUTDOWN 3
46 38
47/* omap_device.flags values */ 39/* omap_device.flags values */
48#define OMAP_DEVICE_SUSPENDED BIT(0) 40#define OMAP_DEVICE_SUSPENDED BIT(0)
49#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1) 41#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1)
50 42
51/** 43/**
52 * struct omap_device - omap_device wrapper for platform_devices 44 * struct omap_device - omap_device wrapper for platform_devices
53 * @pdev: platform_device 45 * @pdev: platform_device
54 * @hwmods: (one .. many per omap_device) 46 * @hwmods: (one .. many per omap_device)
55 * @hwmods_cnt: ARRAY_SIZE() of @hwmods 47 * @hwmods_cnt: ARRAY_SIZE() of @hwmods
56 * @pm_lats: ptr to an omap_device_pm_latency table
57 * @pm_lats_cnt: ARRAY_SIZE() of what is passed to @pm_lats
58 * @pm_lat_level: array index of the last odpl entry executed - -1 if never
59 * @dev_wakeup_lat: dev wakeup latency in nanoseconds
60 * @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
61 * @_state: one of OMAP_DEVICE_STATE_* (see above) 48 * @_state: one of OMAP_DEVICE_STATE_* (see above)
62 * @flags: device flags 49 * @flags: device flags
63 * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h> 50 * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h>
@@ -71,12 +58,7 @@ extern struct dev_pm_domain omap_device_pm_domain;
71struct omap_device { 58struct omap_device {
72 struct platform_device *pdev; 59 struct platform_device *pdev;
73 struct omap_hwmod **hwmods; 60 struct omap_hwmod **hwmods;
74 struct omap_device_pm_latency *pm_lats;
75 u32 dev_wakeup_lat;
76 u32 _dev_wakeup_lat_limit;
77 unsigned long _driver_status; 61 unsigned long _driver_status;
78 u8 pm_lats_cnt;
79 s8 pm_lat_level;
80 u8 hwmods_cnt; 62 u8 hwmods_cnt;
81 u8 _state; 63 u8 _state;
82 u8 flags; 64 u8 flags;
@@ -86,36 +68,25 @@ struct omap_device {
86 68
87int omap_device_enable(struct platform_device *pdev); 69int omap_device_enable(struct platform_device *pdev);
88int omap_device_idle(struct platform_device *pdev); 70int omap_device_idle(struct platform_device *pdev);
89int omap_device_shutdown(struct platform_device *pdev);
90 71
91/* Core code interface */ 72/* Core code interface */
92 73
93struct platform_device *omap_device_build(const char *pdev_name, int pdev_id, 74struct platform_device *omap_device_build(const char *pdev_name, int pdev_id,
94 struct omap_hwmod *oh, void *pdata, 75 struct omap_hwmod *oh, void *pdata,
95 int pdata_len, 76 int pdata_len);
96 struct omap_device_pm_latency *pm_lats,
97 int pm_lats_cnt, int is_early_device);
98 77
99struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id, 78struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
100 struct omap_hwmod **oh, int oh_cnt, 79 struct omap_hwmod **oh, int oh_cnt,
101 void *pdata, int pdata_len, 80 void *pdata, int pdata_len);
102 struct omap_device_pm_latency *pm_lats,
103 int pm_lats_cnt, int is_early_device);
104 81
105struct omap_device *omap_device_alloc(struct platform_device *pdev, 82struct omap_device *omap_device_alloc(struct platform_device *pdev,
106 struct omap_hwmod **ohs, int oh_cnt, 83 struct omap_hwmod **ohs, int oh_cnt);
107 struct omap_device_pm_latency *pm_lats,
108 int pm_lats_cnt);
109void omap_device_delete(struct omap_device *od); 84void omap_device_delete(struct omap_device *od);
110int omap_device_register(struct platform_device *pdev); 85int omap_device_register(struct platform_device *pdev);
111 86
112void __iomem *omap_device_get_rt_va(struct omap_device *od);
113struct device *omap_device_get_by_hwmod_name(const char *oh_name); 87struct device *omap_device_get_by_hwmod_name(const char *oh_name);
114 88
115/* OMAP PM interface */ 89/* OMAP PM interface */
116int omap_device_align_pm_lat(struct platform_device *pdev,
117 u32 new_wakeup_lat_limit);
118struct powerdomain *omap_device_get_pwrdm(struct omap_device *od);
119int omap_device_get_context_loss_count(struct platform_device *pdev); 90int omap_device_get_context_loss_count(struct platform_device *pdev);
120 91
121/* Other */ 92/* Other */
@@ -124,40 +95,6 @@ int omap_device_assert_hardreset(struct platform_device *pdev,
124 const char *name); 95 const char *name);
125int omap_device_deassert_hardreset(struct platform_device *pdev, 96int omap_device_deassert_hardreset(struct platform_device *pdev,
126 const char *name); 97 const char *name);
127int omap_device_idle_hwmods(struct omap_device *od);
128int omap_device_enable_hwmods(struct omap_device *od);
129
130int omap_device_disable_clocks(struct omap_device *od);
131int omap_device_enable_clocks(struct omap_device *od);
132
133/*
134 * Entries should be kept in latency order ascending
135 *
136 * deact_lat is the maximum number of microseconds required to complete
137 * deactivate_func() at the device's slowest OPP.
138 *
139 * act_lat is the maximum number of microseconds required to complete
140 * activate_func() at the device's slowest OPP.
141 *
142 * This will result in some suboptimal power management decisions at fast
143 * OPPs, but avoids having to recompute all device power management decisions
144 * if the system shifts from a fast OPP to a slow OPP (in order to meet
145 * latency requirements).
146 *
147 * XXX should deactivate_func/activate_func() take platform_device pointers
148 * rather than omap_device pointers?
149 */
150struct omap_device_pm_latency {
151 u32 deactivate_lat;
152 u32 deactivate_lat_worst;
153 int (*deactivate_func)(struct omap_device *od);
154 u32 activate_lat;
155 u32 activate_lat_worst;
156 int (*activate_func)(struct omap_device *od);
157 u32 flags;
158};
159
160#define OMAP_DEVICE_LATENCY_AUTO_ADJUST BIT(1)
161 98
162/* Get omap_device pointer from platform_device pointer */ 99/* Get omap_device pointer from platform_device pointer */
163static inline struct omap_device *to_omap_device(struct platform_device *pdev) 100static inline struct omap_device *to_omap_device(struct platform_device *pdev)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 6549439d8d5f..30657b7c3e33 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -139,6 +139,8 @@
139#include <linux/slab.h> 139#include <linux/slab.h>
140#include <linux/bootmem.h> 140#include <linux/bootmem.h>
141 141
142#include <asm/system_misc.h>
143
142#include "clock.h" 144#include "clock.h"
143#include "omap_hwmod.h" 145#include "omap_hwmod.h"
144 146
@@ -2134,6 +2136,8 @@ static int _enable(struct omap_hwmod *oh)
2134 _enable_clocks(oh); 2136 _enable_clocks(oh);
2135 if (soc_ops.enable_module) 2137 if (soc_ops.enable_module)
2136 soc_ops.enable_module(oh); 2138 soc_ops.enable_module(oh);
2139 if (oh->flags & HWMOD_BLOCK_WFI)
2140 disable_hlt();
2137 2141
2138 if (soc_ops.update_context_lost) 2142 if (soc_ops.update_context_lost)
2139 soc_ops.update_context_lost(oh); 2143 soc_ops.update_context_lost(oh);
@@ -2195,6 +2199,8 @@ static int _idle(struct omap_hwmod *oh)
2195 _idle_sysc(oh); 2199 _idle_sysc(oh);
2196 _del_initiator_dep(oh, mpu_oh); 2200 _del_initiator_dep(oh, mpu_oh);
2197 2201
2202 if (oh->flags & HWMOD_BLOCK_WFI)
2203 enable_hlt();
2198 if (soc_ops.disable_module) 2204 if (soc_ops.disable_module)
2199 soc_ops.disable_module(oh); 2205 soc_ops.disable_module(oh);
2200 2206
@@ -2303,6 +2309,8 @@ static int _shutdown(struct omap_hwmod *oh)
2303 if (oh->_state == _HWMOD_STATE_ENABLED) { 2309 if (oh->_state == _HWMOD_STATE_ENABLED) {
2304 _del_initiator_dep(oh, mpu_oh); 2310 _del_initiator_dep(oh, mpu_oh);
2305 /* XXX what about the other system initiators here? dma, dsp */ 2311 /* XXX what about the other system initiators here? dma, dsp */
2312 if (oh->flags & HWMOD_BLOCK_WFI)
2313 enable_hlt();
2306 if (soc_ops.disable_module) 2314 if (soc_ops.disable_module)
2307 soc_ops.disable_module(oh); 2315 soc_ops.disable_module(oh);
2308 _disable_clocks(oh); 2316 _disable_clocks(oh);
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 3ae852a522f9..80c00e706d69 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -451,6 +451,14 @@ struct omap_hwmod_omap4_prcm {
451 * enabled. This prevents the hwmod code from being able to 451 * enabled. This prevents the hwmod code from being able to
452 * enable and reset the IP block early. XXX Eventually it should 452 * enable and reset the IP block early. XXX Eventually it should
453 * be possible to query the clock framework for this information. 453 * be possible to query the clock framework for this information.
454 * HWMOD_BLOCK_WFI: Some OMAP peripherals apparently don't work
455 * correctly if the MPU is allowed to go idle while the
456 * peripherals are active. This is apparently true for the I2C on
457 * OMAP2420, and also the EMAC on AM3517/3505. It's unlikely that
458 * this is really true -- we're probably not configuring something
459 * correctly, or this is being abused to deal with some PM latency
460 * issues -- but we're currently suffering from a shortage of
461 * folks who are able to track these issues down properly.
454 */ 462 */
455#define HWMOD_SWSUP_SIDLE (1 << 0) 463#define HWMOD_SWSUP_SIDLE (1 << 0)
456#define HWMOD_SWSUP_MSTANDBY (1 << 1) 464#define HWMOD_SWSUP_MSTANDBY (1 << 1)
@@ -462,6 +470,7 @@ struct omap_hwmod_omap4_prcm {
462#define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7) 470#define HWMOD_CONTROL_OPT_CLKS_IN_RESET (1 << 7)
463#define HWMOD_16BIT_REG (1 << 8) 471#define HWMOD_16BIT_REG (1 << 8)
464#define HWMOD_EXT_OPT_MAIN_CLK (1 << 9) 472#define HWMOD_EXT_OPT_MAIN_CLK (1 << 9)
473#define HWMOD_BLOCK_WFI (1 << 10)
465 474
466/* 475/*
467 * omap_hwmod._int_flags definitions 476 * omap_hwmod._int_flags definitions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index b5efe58c0be0..6a764af6c6d3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -121,7 +121,12 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
121 }, 121 },
122 .class = &i2c_class, 122 .class = &i2c_class,
123 .dev_attr = &i2c_dev_attr, 123 .dev_attr = &i2c_dev_attr,
124 .flags = HWMOD_16BIT_REG, 124 /*
125 * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
126 * while a transfer is active seems to cause the I2C block to
127 * timeout. Why? Good question."
128 */
129 .flags = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
125}; 130};
126 131
127/* I2C2 */ 132/* I2C2 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8bb2628df34e..ac7e03ec952f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3493,7 +3493,12 @@ static struct omap_hwmod am35xx_emac_hwmod = {
3493 .name = "davinci_emac", 3493 .name = "davinci_emac",
3494 .mpu_irqs = am35xx_emac_mpu_irqs, 3494 .mpu_irqs = am35xx_emac_mpu_irqs,
3495 .class = &am35xx_emac_class, 3495 .class = &am35xx_emac_class,
3496 .flags = HWMOD_NO_IDLEST, 3496 /*
3497 * According to Mark Greer, the MPU will not return from WFI
3498 * when the EMAC signals an interrupt.
3499 * http://www.spinics.net/lists/arm-kernel/msg174734.html
3500 */
3501 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
3497}; 3502};
3498 3503
3499/* l3_core -> davinci emac interface */ 3504/* l3_core -> davinci emac interface */
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 793f54ac7d14..a1849a883702 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -616,7 +616,7 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
616 .clkdm_name = "abe_clkdm", 616 .clkdm_name = "abe_clkdm",
617 .mpu_irqs = omap44xx_dmic_irqs, 617 .mpu_irqs = omap44xx_dmic_irqs,
618 .sdma_reqs = omap44xx_dmic_sdma_reqs, 618 .sdma_reqs = omap44xx_dmic_sdma_reqs,
619 .main_clk = "dmic_fck", 619 .main_clk = "func_dmic_abe_gfclk",
620 .prcm = { 620 .prcm = {
621 .omap4 = { 621 .omap4 = {
622 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, 622 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
@@ -1161,7 +1161,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
1161 .class = &omap44xx_gpio_hwmod_class, 1161 .class = &omap44xx_gpio_hwmod_class,
1162 .clkdm_name = "l4_wkup_clkdm", 1162 .clkdm_name = "l4_wkup_clkdm",
1163 .mpu_irqs = omap44xx_gpio1_irqs, 1163 .mpu_irqs = omap44xx_gpio1_irqs,
1164 .main_clk = "gpio1_ick", 1164 .main_clk = "l4_wkup_clk_mux_ck",
1165 .prcm = { 1165 .prcm = {
1166 .omap4 = { 1166 .omap4 = {
1167 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, 1167 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
@@ -1190,7 +1190,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
1190 .clkdm_name = "l4_per_clkdm", 1190 .clkdm_name = "l4_per_clkdm",
1191 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1191 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1192 .mpu_irqs = omap44xx_gpio2_irqs, 1192 .mpu_irqs = omap44xx_gpio2_irqs,
1193 .main_clk = "gpio2_ick", 1193 .main_clk = "l4_div_ck",
1194 .prcm = { 1194 .prcm = {
1195 .omap4 = { 1195 .omap4 = {
1196 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, 1196 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
@@ -1219,7 +1219,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
1219 .clkdm_name = "l4_per_clkdm", 1219 .clkdm_name = "l4_per_clkdm",
1220 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1220 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1221 .mpu_irqs = omap44xx_gpio3_irqs, 1221 .mpu_irqs = omap44xx_gpio3_irqs,
1222 .main_clk = "gpio3_ick", 1222 .main_clk = "l4_div_ck",
1223 .prcm = { 1223 .prcm = {
1224 .omap4 = { 1224 .omap4 = {
1225 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, 1225 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
@@ -1248,7 +1248,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
1248 .clkdm_name = "l4_per_clkdm", 1248 .clkdm_name = "l4_per_clkdm",
1249 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1249 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1250 .mpu_irqs = omap44xx_gpio4_irqs, 1250 .mpu_irqs = omap44xx_gpio4_irqs,
1251 .main_clk = "gpio4_ick", 1251 .main_clk = "l4_div_ck",
1252 .prcm = { 1252 .prcm = {
1253 .omap4 = { 1253 .omap4 = {
1254 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, 1254 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
@@ -1277,7 +1277,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
1277 .clkdm_name = "l4_per_clkdm", 1277 .clkdm_name = "l4_per_clkdm",
1278 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1278 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1279 .mpu_irqs = omap44xx_gpio5_irqs, 1279 .mpu_irqs = omap44xx_gpio5_irqs,
1280 .main_clk = "gpio5_ick", 1280 .main_clk = "l4_div_ck",
1281 .prcm = { 1281 .prcm = {
1282 .omap4 = { 1282 .omap4 = {
1283 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, 1283 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
@@ -1306,7 +1306,7 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
1306 .clkdm_name = "l4_per_clkdm", 1306 .clkdm_name = "l4_per_clkdm",
1307 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1307 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1308 .mpu_irqs = omap44xx_gpio6_irqs, 1308 .mpu_irqs = omap44xx_gpio6_irqs,
1309 .main_clk = "gpio6_ick", 1309 .main_clk = "l4_div_ck",
1310 .prcm = { 1310 .prcm = {
1311 .omap4 = { 1311 .omap4 = {
1312 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, 1312 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
@@ -1405,7 +1405,7 @@ static struct omap_hwmod omap44xx_gpu_hwmod = {
1405 .class = &omap44xx_gpu_hwmod_class, 1405 .class = &omap44xx_gpu_hwmod_class,
1406 .clkdm_name = "l3_gfx_clkdm", 1406 .clkdm_name = "l3_gfx_clkdm",
1407 .mpu_irqs = omap44xx_gpu_irqs, 1407 .mpu_irqs = omap44xx_gpu_irqs,
1408 .main_clk = "gpu_fck", 1408 .main_clk = "sgx_clk_mux",
1409 .prcm = { 1409 .prcm = {
1410 .omap4 = { 1410 .omap4 = {
1411 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, 1411 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
@@ -1446,7 +1446,7 @@ static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1446 .clkdm_name = "l4_per_clkdm", 1446 .clkdm_name = "l4_per_clkdm",
1447 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ 1447 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1448 .mpu_irqs = omap44xx_hdq1w_irqs, 1448 .mpu_irqs = omap44xx_hdq1w_irqs,
1449 .main_clk = "hdq1w_fck", 1449 .main_clk = "func_12m_fclk",
1450 .prcm = { 1450 .prcm = {
1451 .omap4 = { 1451 .omap4 = {
1452 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, 1452 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
@@ -1550,7 +1550,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
1550 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1550 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1551 .mpu_irqs = omap44xx_i2c1_irqs, 1551 .mpu_irqs = omap44xx_i2c1_irqs,
1552 .sdma_reqs = omap44xx_i2c1_sdma_reqs, 1552 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
1553 .main_clk = "i2c1_fck", 1553 .main_clk = "func_96m_fclk",
1554 .prcm = { 1554 .prcm = {
1555 .omap4 = { 1555 .omap4 = {
1556 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, 1556 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
@@ -1580,7 +1580,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
1580 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1580 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1581 .mpu_irqs = omap44xx_i2c2_irqs, 1581 .mpu_irqs = omap44xx_i2c2_irqs,
1582 .sdma_reqs = omap44xx_i2c2_sdma_reqs, 1582 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
1583 .main_clk = "i2c2_fck", 1583 .main_clk = "func_96m_fclk",
1584 .prcm = { 1584 .prcm = {
1585 .omap4 = { 1585 .omap4 = {
1586 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, 1586 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
@@ -1610,7 +1610,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
1610 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1610 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1611 .mpu_irqs = omap44xx_i2c3_irqs, 1611 .mpu_irqs = omap44xx_i2c3_irqs,
1612 .sdma_reqs = omap44xx_i2c3_sdma_reqs, 1612 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
1613 .main_clk = "i2c3_fck", 1613 .main_clk = "func_96m_fclk",
1614 .prcm = { 1614 .prcm = {
1615 .omap4 = { 1615 .omap4 = {
1616 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, 1616 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
@@ -1640,7 +1640,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
1640 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, 1640 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1641 .mpu_irqs = omap44xx_i2c4_irqs, 1641 .mpu_irqs = omap44xx_i2c4_irqs,
1642 .sdma_reqs = omap44xx_i2c4_sdma_reqs, 1642 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
1643 .main_clk = "i2c4_fck", 1643 .main_clk = "func_96m_fclk",
1644 .prcm = { 1644 .prcm = {
1645 .omap4 = { 1645 .omap4 = {
1646 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, 1646 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
@@ -1743,7 +1743,7 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
1743 .clkdm_name = "iss_clkdm", 1743 .clkdm_name = "iss_clkdm",
1744 .mpu_irqs = omap44xx_iss_irqs, 1744 .mpu_irqs = omap44xx_iss_irqs,
1745 .sdma_reqs = omap44xx_iss_sdma_reqs, 1745 .sdma_reqs = omap44xx_iss_sdma_reqs,
1746 .main_clk = "iss_fck", 1746 .main_clk = "ducati_clk_mux_ck",
1747 .prcm = { 1747 .prcm = {
1748 .omap4 = { 1748 .omap4 = {
1749 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, 1749 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
@@ -1785,7 +1785,7 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
1785 .mpu_irqs = omap44xx_iva_irqs, 1785 .mpu_irqs = omap44xx_iva_irqs,
1786 .rst_lines = omap44xx_iva_resets, 1786 .rst_lines = omap44xx_iva_resets,
1787 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), 1787 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1788 .main_clk = "iva_fck", 1788 .main_clk = "dpll_iva_m5x2_ck",
1789 .prcm = { 1789 .prcm = {
1790 .omap4 = { 1790 .omap4 = {
1791 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, 1791 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
@@ -1829,7 +1829,7 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
1829 .class = &omap44xx_kbd_hwmod_class, 1829 .class = &omap44xx_kbd_hwmod_class,
1830 .clkdm_name = "l4_wkup_clkdm", 1830 .clkdm_name = "l4_wkup_clkdm",
1831 .mpu_irqs = omap44xx_kbd_irqs, 1831 .mpu_irqs = omap44xx_kbd_irqs,
1832 .main_clk = "kbd_fck", 1832 .main_clk = "sys_32k_ck",
1833 .prcm = { 1833 .prcm = {
1834 .omap4 = { 1834 .omap4 = {
1835 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, 1835 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
@@ -1920,7 +1920,7 @@ static struct omap_hwmod omap44xx_mcasp_hwmod = {
1920 .clkdm_name = "abe_clkdm", 1920 .clkdm_name = "abe_clkdm",
1921 .mpu_irqs = omap44xx_mcasp_irqs, 1921 .mpu_irqs = omap44xx_mcasp_irqs,
1922 .sdma_reqs = omap44xx_mcasp_sdma_reqs, 1922 .sdma_reqs = omap44xx_mcasp_sdma_reqs,
1923 .main_clk = "mcasp_fck", 1923 .main_clk = "func_mcasp_abe_gfclk",
1924 .prcm = { 1924 .prcm = {
1925 .omap4 = { 1925 .omap4 = {
1926 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, 1926 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
@@ -1972,7 +1972,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1972 .clkdm_name = "abe_clkdm", 1972 .clkdm_name = "abe_clkdm",
1973 .mpu_irqs = omap44xx_mcbsp1_irqs, 1973 .mpu_irqs = omap44xx_mcbsp1_irqs,
1974 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, 1974 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
1975 .main_clk = "mcbsp1_fck", 1975 .main_clk = "func_mcbsp1_gfclk",
1976 .prcm = { 1976 .prcm = {
1977 .omap4 = { 1977 .omap4 = {
1978 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, 1978 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
@@ -2007,7 +2007,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2007 .clkdm_name = "abe_clkdm", 2007 .clkdm_name = "abe_clkdm",
2008 .mpu_irqs = omap44xx_mcbsp2_irqs, 2008 .mpu_irqs = omap44xx_mcbsp2_irqs,
2009 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, 2009 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
2010 .main_clk = "mcbsp2_fck", 2010 .main_clk = "func_mcbsp2_gfclk",
2011 .prcm = { 2011 .prcm = {
2012 .omap4 = { 2012 .omap4 = {
2013 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, 2013 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
@@ -2042,7 +2042,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2042 .clkdm_name = "abe_clkdm", 2042 .clkdm_name = "abe_clkdm",
2043 .mpu_irqs = omap44xx_mcbsp3_irqs, 2043 .mpu_irqs = omap44xx_mcbsp3_irqs,
2044 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, 2044 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
2045 .main_clk = "mcbsp3_fck", 2045 .main_clk = "func_mcbsp3_gfclk",
2046 .prcm = { 2046 .prcm = {
2047 .omap4 = { 2047 .omap4 = {
2048 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, 2048 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
@@ -2077,7 +2077,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2077 .clkdm_name = "l4_per_clkdm", 2077 .clkdm_name = "l4_per_clkdm",
2078 .mpu_irqs = omap44xx_mcbsp4_irqs, 2078 .mpu_irqs = omap44xx_mcbsp4_irqs,
2079 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, 2079 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
2080 .main_clk = "mcbsp4_fck", 2080 .main_clk = "per_mcbsp4_gfclk",
2081 .prcm = { 2081 .prcm = {
2082 .omap4 = { 2082 .omap4 = {
2083 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, 2083 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
@@ -2140,7 +2140,7 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2140 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, 2140 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
2141 .mpu_irqs = omap44xx_mcpdm_irqs, 2141 .mpu_irqs = omap44xx_mcpdm_irqs,
2142 .sdma_reqs = omap44xx_mcpdm_sdma_reqs, 2142 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
2143 .main_clk = "mcpdm_fck", 2143 .main_clk = "pad_clks_ck",
2144 .prcm = { 2144 .prcm = {
2145 .omap4 = { 2145 .omap4 = {
2146 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, 2146 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
@@ -2201,7 +2201,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2201 .clkdm_name = "l4_per_clkdm", 2201 .clkdm_name = "l4_per_clkdm",
2202 .mpu_irqs = omap44xx_mcspi1_irqs, 2202 .mpu_irqs = omap44xx_mcspi1_irqs,
2203 .sdma_reqs = omap44xx_mcspi1_sdma_reqs, 2203 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
2204 .main_clk = "mcspi1_fck", 2204 .main_clk = "func_48m_fclk",
2205 .prcm = { 2205 .prcm = {
2206 .omap4 = { 2206 .omap4 = {
2207 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, 2207 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
@@ -2237,7 +2237,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2237 .clkdm_name = "l4_per_clkdm", 2237 .clkdm_name = "l4_per_clkdm",
2238 .mpu_irqs = omap44xx_mcspi2_irqs, 2238 .mpu_irqs = omap44xx_mcspi2_irqs,
2239 .sdma_reqs = omap44xx_mcspi2_sdma_reqs, 2239 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
2240 .main_clk = "mcspi2_fck", 2240 .main_clk = "func_48m_fclk",
2241 .prcm = { 2241 .prcm = {
2242 .omap4 = { 2242 .omap4 = {
2243 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, 2243 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
@@ -2273,7 +2273,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2273 .clkdm_name = "l4_per_clkdm", 2273 .clkdm_name = "l4_per_clkdm",
2274 .mpu_irqs = omap44xx_mcspi3_irqs, 2274 .mpu_irqs = omap44xx_mcspi3_irqs,
2275 .sdma_reqs = omap44xx_mcspi3_sdma_reqs, 2275 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
2276 .main_clk = "mcspi3_fck", 2276 .main_clk = "func_48m_fclk",
2277 .prcm = { 2277 .prcm = {
2278 .omap4 = { 2278 .omap4 = {
2279 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, 2279 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
@@ -2307,7 +2307,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2307 .clkdm_name = "l4_per_clkdm", 2307 .clkdm_name = "l4_per_clkdm",
2308 .mpu_irqs = omap44xx_mcspi4_irqs, 2308 .mpu_irqs = omap44xx_mcspi4_irqs,
2309 .sdma_reqs = omap44xx_mcspi4_sdma_reqs, 2309 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
2310 .main_clk = "mcspi4_fck", 2310 .main_clk = "func_48m_fclk",
2311 .prcm = { 2311 .prcm = {
2312 .omap4 = { 2312 .omap4 = {
2313 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, 2313 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
@@ -2363,7 +2363,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
2363 .clkdm_name = "l3_init_clkdm", 2363 .clkdm_name = "l3_init_clkdm",
2364 .mpu_irqs = omap44xx_mmc1_irqs, 2364 .mpu_irqs = omap44xx_mmc1_irqs,
2365 .sdma_reqs = omap44xx_mmc1_sdma_reqs, 2365 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
2366 .main_clk = "mmc1_fck", 2366 .main_clk = "hsmmc1_fclk",
2367 .prcm = { 2367 .prcm = {
2368 .omap4 = { 2368 .omap4 = {
2369 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, 2369 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
@@ -2392,7 +2392,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
2392 .clkdm_name = "l3_init_clkdm", 2392 .clkdm_name = "l3_init_clkdm",
2393 .mpu_irqs = omap44xx_mmc2_irqs, 2393 .mpu_irqs = omap44xx_mmc2_irqs,
2394 .sdma_reqs = omap44xx_mmc2_sdma_reqs, 2394 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
2395 .main_clk = "mmc2_fck", 2395 .main_clk = "hsmmc2_fclk",
2396 .prcm = { 2396 .prcm = {
2397 .omap4 = { 2397 .omap4 = {
2398 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, 2398 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
@@ -2420,7 +2420,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
2420 .clkdm_name = "l4_per_clkdm", 2420 .clkdm_name = "l4_per_clkdm",
2421 .mpu_irqs = omap44xx_mmc3_irqs, 2421 .mpu_irqs = omap44xx_mmc3_irqs,
2422 .sdma_reqs = omap44xx_mmc3_sdma_reqs, 2422 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2423 .main_clk = "mmc3_fck", 2423 .main_clk = "func_48m_fclk",
2424 .prcm = { 2424 .prcm = {
2425 .omap4 = { 2425 .omap4 = {
2426 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, 2426 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
@@ -2448,7 +2448,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
2448 .clkdm_name = "l4_per_clkdm", 2448 .clkdm_name = "l4_per_clkdm",
2449 .mpu_irqs = omap44xx_mmc4_irqs, 2449 .mpu_irqs = omap44xx_mmc4_irqs,
2450 .sdma_reqs = omap44xx_mmc4_sdma_reqs, 2450 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2451 .main_clk = "mmc4_fck", 2451 .main_clk = "func_48m_fclk",
2452 .prcm = { 2452 .prcm = {
2453 .omap4 = { 2453 .omap4 = {
2454 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, 2454 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
@@ -2476,7 +2476,7 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
2476 .clkdm_name = "l4_per_clkdm", 2476 .clkdm_name = "l4_per_clkdm",
2477 .mpu_irqs = omap44xx_mmc5_irqs, 2477 .mpu_irqs = omap44xx_mmc5_irqs,
2478 .sdma_reqs = omap44xx_mmc5_sdma_reqs, 2478 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2479 .main_clk = "mmc5_fck", 2479 .main_clk = "func_48m_fclk",
2480 .prcm = { 2480 .prcm = {
2481 .omap4 = { 2481 .omap4 = {
2482 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, 2482 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
@@ -2725,7 +2725,7 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2725 .name = "ocp2scp_usb_phy", 2725 .name = "ocp2scp_usb_phy",
2726 .class = &omap44xx_ocp2scp_hwmod_class, 2726 .class = &omap44xx_ocp2scp_hwmod_class,
2727 .clkdm_name = "l3_init_clkdm", 2727 .clkdm_name = "l3_init_clkdm",
2728 .main_clk = "ocp2scp_usb_phy_phy_48m", 2728 .main_clk = "func_48m_fclk",
2729 .prcm = { 2729 .prcm = {
2730 .omap4 = { 2730 .omap4 = {
2731 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, 2731 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
@@ -3162,7 +3162,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
3162 .clkdm_name = "l4_wkup_clkdm", 3162 .clkdm_name = "l4_wkup_clkdm",
3163 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 3163 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3164 .mpu_irqs = omap44xx_timer1_irqs, 3164 .mpu_irqs = omap44xx_timer1_irqs,
3165 .main_clk = "timer1_fck", 3165 .main_clk = "dmt1_clk_mux",
3166 .prcm = { 3166 .prcm = {
3167 .omap4 = { 3167 .omap4 = {
3168 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, 3168 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
@@ -3185,7 +3185,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
3185 .clkdm_name = "l4_per_clkdm", 3185 .clkdm_name = "l4_per_clkdm",
3186 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 3186 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3187 .mpu_irqs = omap44xx_timer2_irqs, 3187 .mpu_irqs = omap44xx_timer2_irqs,
3188 .main_clk = "timer2_fck", 3188 .main_clk = "cm2_dm2_mux",
3189 .prcm = { 3189 .prcm = {
3190 .omap4 = { 3190 .omap4 = {
3191 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, 3191 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
@@ -3206,7 +3206,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
3206 .class = &omap44xx_timer_hwmod_class, 3206 .class = &omap44xx_timer_hwmod_class,
3207 .clkdm_name = "l4_per_clkdm", 3207 .clkdm_name = "l4_per_clkdm",
3208 .mpu_irqs = omap44xx_timer3_irqs, 3208 .mpu_irqs = omap44xx_timer3_irqs,
3209 .main_clk = "timer3_fck", 3209 .main_clk = "cm2_dm3_mux",
3210 .prcm = { 3210 .prcm = {
3211 .omap4 = { 3211 .omap4 = {
3212 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, 3212 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
@@ -3227,7 +3227,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
3227 .class = &omap44xx_timer_hwmod_class, 3227 .class = &omap44xx_timer_hwmod_class,
3228 .clkdm_name = "l4_per_clkdm", 3228 .clkdm_name = "l4_per_clkdm",
3229 .mpu_irqs = omap44xx_timer4_irqs, 3229 .mpu_irqs = omap44xx_timer4_irqs,
3230 .main_clk = "timer4_fck", 3230 .main_clk = "cm2_dm4_mux",
3231 .prcm = { 3231 .prcm = {
3232 .omap4 = { 3232 .omap4 = {
3233 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, 3233 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
@@ -3248,7 +3248,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
3248 .class = &omap44xx_timer_hwmod_class, 3248 .class = &omap44xx_timer_hwmod_class,
3249 .clkdm_name = "abe_clkdm", 3249 .clkdm_name = "abe_clkdm",
3250 .mpu_irqs = omap44xx_timer5_irqs, 3250 .mpu_irqs = omap44xx_timer5_irqs,
3251 .main_clk = "timer5_fck", 3251 .main_clk = "timer5_sync_mux",
3252 .prcm = { 3252 .prcm = {
3253 .omap4 = { 3253 .omap4 = {
3254 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, 3254 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
@@ -3270,8 +3270,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
3270 .class = &omap44xx_timer_hwmod_class, 3270 .class = &omap44xx_timer_hwmod_class,
3271 .clkdm_name = "abe_clkdm", 3271 .clkdm_name = "abe_clkdm",
3272 .mpu_irqs = omap44xx_timer6_irqs, 3272 .mpu_irqs = omap44xx_timer6_irqs,
3273 3273 .main_clk = "timer6_sync_mux",
3274 .main_clk = "timer6_fck",
3275 .prcm = { 3274 .prcm = {
3276 .omap4 = { 3275 .omap4 = {
3277 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, 3276 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
@@ -3293,7 +3292,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
3293 .class = &omap44xx_timer_hwmod_class, 3292 .class = &omap44xx_timer_hwmod_class,
3294 .clkdm_name = "abe_clkdm", 3293 .clkdm_name = "abe_clkdm",
3295 .mpu_irqs = omap44xx_timer7_irqs, 3294 .mpu_irqs = omap44xx_timer7_irqs,
3296 .main_clk = "timer7_fck", 3295 .main_clk = "timer7_sync_mux",
3297 .prcm = { 3296 .prcm = {
3298 .omap4 = { 3297 .omap4 = {
3299 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, 3298 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
@@ -3315,7 +3314,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
3315 .class = &omap44xx_timer_hwmod_class, 3314 .class = &omap44xx_timer_hwmod_class,
3316 .clkdm_name = "abe_clkdm", 3315 .clkdm_name = "abe_clkdm",
3317 .mpu_irqs = omap44xx_timer8_irqs, 3316 .mpu_irqs = omap44xx_timer8_irqs,
3318 .main_clk = "timer8_fck", 3317 .main_clk = "timer8_sync_mux",
3319 .prcm = { 3318 .prcm = {
3320 .omap4 = { 3319 .omap4 = {
3321 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, 3320 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
@@ -3337,7 +3336,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
3337 .class = &omap44xx_timer_hwmod_class, 3336 .class = &omap44xx_timer_hwmod_class,
3338 .clkdm_name = "l4_per_clkdm", 3337 .clkdm_name = "l4_per_clkdm",
3339 .mpu_irqs = omap44xx_timer9_irqs, 3338 .mpu_irqs = omap44xx_timer9_irqs,
3340 .main_clk = "timer9_fck", 3339 .main_clk = "cm2_dm9_mux",
3341 .prcm = { 3340 .prcm = {
3342 .omap4 = { 3341 .omap4 = {
3343 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, 3342 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
@@ -3360,7 +3359,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
3360 .clkdm_name = "l4_per_clkdm", 3359 .clkdm_name = "l4_per_clkdm",
3361 .flags = HWMOD_SET_DEFAULT_CLOCKACT, 3360 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3362 .mpu_irqs = omap44xx_timer10_irqs, 3361 .mpu_irqs = omap44xx_timer10_irqs,
3363 .main_clk = "timer10_fck", 3362 .main_clk = "cm2_dm10_mux",
3364 .prcm = { 3363 .prcm = {
3365 .omap4 = { 3364 .omap4 = {
3366 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, 3365 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
@@ -3382,7 +3381,7 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
3382 .class = &omap44xx_timer_hwmod_class, 3381 .class = &omap44xx_timer_hwmod_class,
3383 .clkdm_name = "l4_per_clkdm", 3382 .clkdm_name = "l4_per_clkdm",
3384 .mpu_irqs = omap44xx_timer11_irqs, 3383 .mpu_irqs = omap44xx_timer11_irqs,
3385 .main_clk = "timer11_fck", 3384 .main_clk = "cm2_dm11_mux",
3386 .prcm = { 3385 .prcm = {
3387 .omap4 = { 3386 .omap4 = {
3388 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, 3387 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
@@ -3433,7 +3432,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
3433 .clkdm_name = "l4_per_clkdm", 3432 .clkdm_name = "l4_per_clkdm",
3434 .mpu_irqs = omap44xx_uart1_irqs, 3433 .mpu_irqs = omap44xx_uart1_irqs,
3435 .sdma_reqs = omap44xx_uart1_sdma_reqs, 3434 .sdma_reqs = omap44xx_uart1_sdma_reqs,
3436 .main_clk = "uart1_fck", 3435 .main_clk = "func_48m_fclk",
3437 .prcm = { 3436 .prcm = {
3438 .omap4 = { 3437 .omap4 = {
3439 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, 3438 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
@@ -3461,7 +3460,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
3461 .clkdm_name = "l4_per_clkdm", 3460 .clkdm_name = "l4_per_clkdm",
3462 .mpu_irqs = omap44xx_uart2_irqs, 3461 .mpu_irqs = omap44xx_uart2_irqs,
3463 .sdma_reqs = omap44xx_uart2_sdma_reqs, 3462 .sdma_reqs = omap44xx_uart2_sdma_reqs,
3464 .main_clk = "uart2_fck", 3463 .main_clk = "func_48m_fclk",
3465 .prcm = { 3464 .prcm = {
3466 .omap4 = { 3465 .omap4 = {
3467 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, 3466 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
@@ -3490,7 +3489,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
3490 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, 3489 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3491 .mpu_irqs = omap44xx_uart3_irqs, 3490 .mpu_irqs = omap44xx_uart3_irqs,
3492 .sdma_reqs = omap44xx_uart3_sdma_reqs, 3491 .sdma_reqs = omap44xx_uart3_sdma_reqs,
3493 .main_clk = "uart3_fck", 3492 .main_clk = "func_48m_fclk",
3494 .prcm = { 3493 .prcm = {
3495 .omap4 = { 3494 .omap4 = {
3496 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, 3495 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
@@ -3518,7 +3517,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
3518 .clkdm_name = "l4_per_clkdm", 3517 .clkdm_name = "l4_per_clkdm",
3519 .mpu_irqs = omap44xx_uart4_irqs, 3518 .mpu_irqs = omap44xx_uart4_irqs,
3520 .sdma_reqs = omap44xx_uart4_sdma_reqs, 3519 .sdma_reqs = omap44xx_uart4_sdma_reqs,
3521 .main_clk = "uart4_fck", 3520 .main_clk = "func_48m_fclk",
3522 .prcm = { 3521 .prcm = {
3523 .omap4 = { 3522 .omap4 = {
3524 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, 3523 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
@@ -3797,7 +3796,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3797 .class = &omap44xx_wd_timer_hwmod_class, 3796 .class = &omap44xx_wd_timer_hwmod_class,
3798 .clkdm_name = "l4_wkup_clkdm", 3797 .clkdm_name = "l4_wkup_clkdm",
3799 .mpu_irqs = omap44xx_wd_timer2_irqs, 3798 .mpu_irqs = omap44xx_wd_timer2_irqs,
3800 .main_clk = "wd_timer2_fck", 3799 .main_clk = "sys_32k_ck",
3801 .prcm = { 3800 .prcm = {
3802 .omap4 = { 3801 .omap4 = {
3803 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, 3802 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
@@ -3818,7 +3817,7 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3818 .class = &omap44xx_wd_timer_hwmod_class, 3817 .class = &omap44xx_wd_timer_hwmod_class,
3819 .clkdm_name = "abe_clkdm", 3818 .clkdm_name = "abe_clkdm",
3820 .mpu_irqs = omap44xx_wd_timer3_irqs, 3819 .mpu_irqs = omap44xx_wd_timer3_irqs,
3821 .main_clk = "wd_timer3_fck", 3820 .main_clk = "sys_32k_ck",
3822 .prcm = { 3821 .prcm = {
3823 .omap4 = { 3822 .omap4 = {
3824 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, 3823 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index e2c291f52f92..6db89ae92389 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -83,10 +83,8 @@ static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
83 strncmp(clkdm->name, "dpll", 4) == 0) 83 strncmp(clkdm->name, "dpll", 4) == 0)
84 return 0; 84 return 0;
85 85
86 seq_printf(s, "%s->%s (%d)", clkdm->name, 86 seq_printf(s, "%s->%s (%d)\n", clkdm->name, clkdm->pwrdm.ptr->name,
87 clkdm->pwrdm.ptr->name, 87 clkdm->usecount);
88 atomic_read(&clkdm->usecount));
89 seq_printf(s, "\n");
90 88
91 return 0; 89 return 0;
92} 90}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index f4b3143a8b1d..9a9be3c9f208 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -32,8 +32,6 @@
32#include "pm.h" 32#include "pm.h"
33#include "twl-common.h" 33#include "twl-common.h"
34 34
35static struct omap_device_pm_latency *pm_lats;
36
37/* 35/*
38 * omap_pm_suspend: points to a function that does the SoC-specific 36 * omap_pm_suspend: points to a function that does the SoC-specific
39 * suspend work 37 * suspend work
@@ -82,7 +80,7 @@ static int __init _init_omap_device(char *name)
82 __func__, name)) 80 __func__, name))
83 return -ENODEV; 81 return -ENODEV;
84 82
85 pdev = omap_device_build(oh->name, 0, oh, NULL, 0, pm_lats, 0, false); 83 pdev = omap_device_build(oh->name, 0, oh, NULL, 0);
86 if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n", 84 if (WARN(IS_ERR(pdev), "%s: could not build omap_device for %s\n",
87 __func__, name)) 85 __func__, name))
88 return -ENODEV; 86 return -ENODEV;
@@ -108,80 +106,19 @@ static void __init omap2_init_processor_devices(void)
108 } 106 }
109} 107}
110 108
111/* Types of sleep_switch used in omap_set_pwrdm_state */
112#define FORCEWAKEUP_SWITCH 0
113#define LOWPOWERSTATE_SWITCH 1
114
115int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) 109int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
116{ 110{
111 /* XXX The usecount test is racy */
117 if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) && 112 if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) &&
118 !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING)) 113 !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING))
119 clkdm_allow_idle(clkdm); 114 clkdm_allow_idle(clkdm);
120 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && 115 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
121 atomic_read(&clkdm->usecount) == 0) 116 clkdm->usecount == 0)
122 clkdm_sleep(clkdm); 117 clkdm_sleep(clkdm);
123 return 0; 118 return 0;
124} 119}
125 120
126/* 121/*
127 * This sets pwrdm state (other than mpu & core. Currently only ON &
128 * RET are supported.
129 */
130int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 pwrst)
131{
132 u8 curr_pwrst, next_pwrst;
133 int sleep_switch = -1, ret = 0, hwsup = 0;
134
135 if (!pwrdm || IS_ERR(pwrdm))
136 return -EINVAL;
137
138 while (!(pwrdm->pwrsts & (1 << pwrst))) {
139 if (pwrst == PWRDM_POWER_OFF)
140 return ret;
141 pwrst--;
142 }
143
144 next_pwrst = pwrdm_read_next_pwrst(pwrdm);
145 if (next_pwrst == pwrst)
146 return ret;
147
148 curr_pwrst = pwrdm_read_pwrst(pwrdm);
149 if (curr_pwrst < PWRDM_POWER_ON) {
150 if ((curr_pwrst > pwrst) &&
151 (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
152 sleep_switch = LOWPOWERSTATE_SWITCH;
153 } else {
154 hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
155 clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
156 sleep_switch = FORCEWAKEUP_SWITCH;
157 }
158 }
159
160 ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
161 if (ret)
162 pr_err("%s: unable to set power state of powerdomain: %s\n",
163 __func__, pwrdm->name);
164
165 switch (sleep_switch) {
166 case FORCEWAKEUP_SWITCH:
167 if (hwsup)
168 clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
169 else
170 clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
171 break;
172 case LOWPOWERSTATE_SWITCH:
173 pwrdm_set_lowpwrstchange(pwrdm);
174 pwrdm_wait_transition(pwrdm);
175 pwrdm_state_switch(pwrdm);
176 break;
177 }
178
179 return ret;
180}
181
182
183
184/*
185 * This API is to be called during init to set the various voltage 122 * This API is to be called during init to set the various voltage
186 * domains to the voltage as per the opp table. Typically we boot up 123 * domains to the voltage as per the opp table. Typically we boot up
187 * at the nominal voltage. So this function finds out the rate of 124 * at the nominal voltage. So this function finds out the rate of
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index c22503b17abd..7bdd22afce69 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -33,7 +33,6 @@ static inline int omap4_idle_init(void)
33extern void *omap3_secure_ram_storage; 33extern void *omap3_secure_ram_storage;
34extern void omap3_pm_off_mode_enable(int); 34extern void omap3_pm_off_mode_enable(int);
35extern void omap_sram_idle(void); 35extern void omap_sram_idle(void);
36extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
37extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused); 36extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
38extern int (*omap_pm_suspend)(void); 37extern int (*omap_pm_suspend)(void);
39 38
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index c333fa6dffa8..b59d93908341 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -54,7 +54,6 @@
54#include "powerdomain.h" 54#include "powerdomain.h"
55#include "clockdomain.h" 55#include "clockdomain.h"
56 56
57static void (*omap2_sram_idle)(void);
58static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, 57static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
59 void __iomem *sdrc_power); 58 void __iomem *sdrc_power);
60 59
@@ -90,11 +89,7 @@ static int omap2_enter_full_retention(void)
90 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); 89 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
91 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); 90 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
92 91
93 /* 92 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
94 * Set MPU powerdomain's next power state to RETENTION;
95 * preserve logic state during retention
96 */
97 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
98 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); 93 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
99 94
100 /* Workaround to kill USB */ 95 /* Workaround to kill USB */
@@ -137,15 +132,10 @@ no_sleep:
137 /* Mask future PRCM-to-MPU interrupts */ 132 /* Mask future PRCM-to-MPU interrupts */
138 omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); 133 omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
139 134
140 return 0; 135 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
141} 136 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON);
142
143static int omap2_i2c_active(void)
144{
145 u32 l;
146 137
147 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); 138 return 0;
148 return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
149} 139}
150 140
151static int sti_console_enabled; 141static int sti_console_enabled;
@@ -172,10 +162,7 @@ static int omap2_allow_mpu_retention(void)
172 162
173static void omap2_enter_mpu_retention(void) 163static void omap2_enter_mpu_retention(void)
174{ 164{
175 /* Putting MPU into the WFI state while a transfer is active 165 const int zero = 0;
176 * seems to cause the I2C block to timeout. Why? Good question. */
177 if (omap2_i2c_active())
178 return;
179 166
180 /* The peripherals seem not to be able to wake up the MPU when 167 /* The peripherals seem not to be able to wake up the MPU when
181 * it is in retention mode. */ 168 * it is in retention mode. */
@@ -186,17 +173,17 @@ static void omap2_enter_mpu_retention(void)
186 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); 173 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
187 174
188 /* Try to enter MPU retention */ 175 /* Try to enter MPU retention */
189 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | 176 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
190 OMAP_LOGICRETSTATE_MASK, 177
191 MPU_MOD, OMAP2_PM_PWSTCTRL);
192 } else { 178 } else {
193 /* Block MPU retention */ 179 /* Block MPU retention */
194 180 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
195 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
196 OMAP2_PM_PWSTCTRL);
197 } 181 }
198 182
199 omap2_sram_idle(); 183 /* WFI */
184 asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");
185
186 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
200} 187}
201 188
202static int omap2_can_sleep(void) 189static int omap2_can_sleep(void)
@@ -251,25 +238,17 @@ static void __init prcm_setup_regs(void)
251 for (i = 0; i < num_mem_banks; i++) 238 for (i = 0; i < num_mem_banks; i++)
252 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET); 239 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
253 240
254 /* Set CORE powerdomain's next power state to RETENTION */ 241 pwrdm_set_logic_retst(core_pwrdm, PWRDM_POWER_RET);
255 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
256 242
257 /*
258 * Set MPU powerdomain's next power state to RETENTION;
259 * preserve logic state during retention
260 */
261 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); 243 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
262 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
263 244
264 /* Force-power down DSP, GFX powerdomains */ 245 /* Force-power down DSP, GFX powerdomains */
265 246
266 pwrdm = clkdm_get_pwrdm(dsp_clkdm); 247 pwrdm = clkdm_get_pwrdm(dsp_clkdm);
267 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); 248 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
268 clkdm_sleep(dsp_clkdm);
269 249
270 pwrdm = clkdm_get_pwrdm(gfx_clkdm); 250 pwrdm = clkdm_get_pwrdm(gfx_clkdm);
271 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); 251 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
272 clkdm_sleep(gfx_clkdm);
273 252
274 /* Enable hardware-supervised idle for all clkdms */ 253 /* Enable hardware-supervised idle for all clkdms */
275 clkdm_for_each(omap_pm_clkdms_setup, NULL); 254 clkdm_for_each(omap_pm_clkdms_setup, NULL);
@@ -356,11 +335,9 @@ int __init omap2_pm_init(void)
356 /* 335 /*
357 * We copy the assembler sleep/wakeup routines to SRAM. 336 * We copy the assembler sleep/wakeup routines to SRAM.
358 * These routines need to be in SRAM as that's the only 337 * These routines need to be in SRAM as that's the only
359 * memory the MPU can see when it wakes up. 338 * memory the MPU can see when it wakes up after the entire
339 * chip enters idle.
360 */ 340 */
361 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
362 omap24xx_idle_loop_suspend_sz);
363
364 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, 341 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
365 omap24xx_cpu_suspend_sz); 342 omap24xx_cpu_suspend_sz);
366 343
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
index eb78ae7a3464..0ef4d6aa758e 100644
--- a/arch/arm/mach-omap2/pmu.c
+++ b/arch/arm/mach-omap2/pmu.c
@@ -48,8 +48,7 @@ static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
48 } 48 }
49 } 49 }
50 50
51 omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0, 51 omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0);
52 NULL, 0, 0);
53 WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n", 52 WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n",
54 dev_name); 53 dev_name);
55 54
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index dea62a9aad07..8e61d80bf6b3 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -19,6 +19,7 @@
19#include <linux/list.h> 19#include <linux/list.h>
20#include <linux/errno.h> 20#include <linux/errno.h>
21#include <linux/string.h> 21#include <linux/string.h>
22#include <linux/spinlock.h>
22#include <trace/events/power.h> 23#include <trace/events/power.h>
23 24
24#include "cm2xxx_3xxx.h" 25#include "cm2xxx_3xxx.h"
@@ -42,6 +43,16 @@ enum {
42 PWRDM_STATE_PREV, 43 PWRDM_STATE_PREV,
43}; 44};
44 45
46/*
47 * Types of sleep_switch used internally in omap_set_pwrdm_state()
48 * and its associated static functions
49 *
50 * XXX Better documentation is needed here
51 */
52#define ALREADYACTIVE_SWITCH 0
53#define FORCEWAKEUP_SWITCH 1
54#define LOWPOWERSTATE_SWITCH 2
55#define ERROR_SWITCH 3
45 56
46/* pwrdm_list contains all registered struct powerdomains */ 57/* pwrdm_list contains all registered struct powerdomains */
47static LIST_HEAD(pwrdm_list); 58static LIST_HEAD(pwrdm_list);
@@ -101,6 +112,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
101 pwrdm->voltdm.ptr = voltdm; 112 pwrdm->voltdm.ptr = voltdm;
102 INIT_LIST_HEAD(&pwrdm->voltdm_node); 113 INIT_LIST_HEAD(&pwrdm->voltdm_node);
103 voltdm_add_pwrdm(voltdm, pwrdm); 114 voltdm_add_pwrdm(voltdm, pwrdm);
115 spin_lock_init(&pwrdm->_lock);
104 116
105 list_add(&pwrdm->node, &pwrdm_list); 117 list_add(&pwrdm->node, &pwrdm_list);
106 118
@@ -112,7 +124,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
112 for (i = 0; i < pwrdm->banks; i++) 124 for (i = 0; i < pwrdm->banks; i++)
113 pwrdm->ret_mem_off_counter[i] = 0; 125 pwrdm->ret_mem_off_counter[i] = 0;
114 126
115 pwrdm_wait_transition(pwrdm); 127 arch_pwrdm->pwrdm_wait_transition(pwrdm);
116 pwrdm->state = pwrdm_read_pwrst(pwrdm); 128 pwrdm->state = pwrdm_read_pwrst(pwrdm);
117 pwrdm->state_counter[pwrdm->state] = 1; 129 pwrdm->state_counter[pwrdm->state] = 1;
118 130
@@ -143,7 +155,7 @@ static void _update_logic_membank_counters(struct powerdomain *pwrdm)
143static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) 155static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
144{ 156{
145 157
146 int prev, state, trace_state = 0; 158 int prev, next, state, trace_state = 0;
147 159
148 if (pwrdm == NULL) 160 if (pwrdm == NULL)
149 return -EINVAL; 161 return -EINVAL;
@@ -164,9 +176,10 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag)
164 * If the power domain did not hit the desired state, 176 * If the power domain did not hit the desired state,
165 * generate a trace event with both the desired and hit states 177 * generate a trace event with both the desired and hit states
166 */ 178 */
167 if (state != prev) { 179 next = pwrdm_read_next_pwrst(pwrdm);
180 if (next != prev) {
168 trace_state = (PWRDM_TRACE_STATES_FLAG | 181 trace_state = (PWRDM_TRACE_STATES_FLAG |
169 ((state & OMAP_POWERSTATE_MASK) << 8) | 182 ((next & OMAP_POWERSTATE_MASK) << 8) |
170 ((prev & OMAP_POWERSTATE_MASK) << 0)); 183 ((prev & OMAP_POWERSTATE_MASK) << 0));
171 trace_power_domain_target(pwrdm->name, trace_state, 184 trace_power_domain_target(pwrdm->name, trace_state,
172 smp_processor_id()); 185 smp_processor_id());
@@ -199,6 +212,80 @@ static int _pwrdm_post_transition_cb(struct powerdomain *pwrdm, void *unused)
199 return 0; 212 return 0;
200} 213}
201 214
215/**
216 * _pwrdm_save_clkdm_state_and_activate - prepare for power state change
217 * @pwrdm: struct powerdomain * to operate on
218 * @curr_pwrst: current power state of @pwrdm
219 * @pwrst: power state to switch to
220 * @hwsup: ptr to a bool to return whether the clkdm is hardware-supervised
221 *
222 * Determine whether the powerdomain needs to be turned on before
223 * attempting to switch power states. Called by
224 * omap_set_pwrdm_state(). NOTE that if the powerdomain contains
225 * multiple clockdomains, this code assumes that the first clockdomain
226 * supports software-supervised wakeup mode - potentially a problem.
227 * Returns the power state switch mode currently in use (see the
228 * "Types of sleep_switch" comment above).
229 */
230static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
231 u8 curr_pwrst, u8 pwrst,
232 bool *hwsup)
233{
234 u8 sleep_switch;
235
236 if (curr_pwrst < 0) {
237 WARN_ON(1);
238 sleep_switch = ERROR_SWITCH;
239 } else if (curr_pwrst < PWRDM_POWER_ON) {
240 if (curr_pwrst > pwrst &&
241 pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE &&
242 arch_pwrdm->pwrdm_set_lowpwrstchange) {
243 sleep_switch = LOWPOWERSTATE_SWITCH;
244 } else {
245 *hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
246 clkdm_wakeup_nolock(pwrdm->pwrdm_clkdms[0]);
247 sleep_switch = FORCEWAKEUP_SWITCH;
248 }
249 } else {
250 sleep_switch = ALREADYACTIVE_SWITCH;
251 }
252
253 return sleep_switch;
254}
255
256/**
257 * _pwrdm_restore_clkdm_state - restore the clkdm hwsup state after pwrst change
258 * @pwrdm: struct powerdomain * to operate on
259 * @sleep_switch: return value from _pwrdm_save_clkdm_state_and_activate()
260 * @hwsup: should @pwrdm's first clockdomain be set to hardware-supervised mode?
261 *
262 * Restore the clockdomain state perturbed by
263 * _pwrdm_save_clkdm_state_and_activate(), and call the power state
264 * bookkeeping code. Called by omap_set_pwrdm_state(). NOTE that if
265 * the powerdomain contains multiple clockdomains, this assumes that
266 * the first associated clockdomain supports either
267 * hardware-supervised idle control in the register, or
268 * software-supervised sleep. No return value.
269 */
270static void _pwrdm_restore_clkdm_state(struct powerdomain *pwrdm,
271 u8 sleep_switch, bool hwsup)
272{
273 switch (sleep_switch) {
274 case FORCEWAKEUP_SWITCH:
275 if (hwsup)
276 clkdm_allow_idle_nolock(pwrdm->pwrdm_clkdms[0]);
277 else
278 clkdm_sleep_nolock(pwrdm->pwrdm_clkdms[0]);
279 break;
280 case LOWPOWERSTATE_SWITCH:
281 if (pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE &&
282 arch_pwrdm->pwrdm_set_lowpwrstchange)
283 arch_pwrdm->pwrdm_set_lowpwrstchange(pwrdm);
284 pwrdm_state_switch_nolock(pwrdm);
285 break;
286 }
287}
288
202/* Public functions */ 289/* Public functions */
203 290
204/** 291/**
@@ -275,6 +362,30 @@ int pwrdm_complete_init(void)
275} 362}
276 363
277/** 364/**
365 * pwrdm_lock - acquire a Linux spinlock on a powerdomain
366 * @pwrdm: struct powerdomain * to lock
367 *
368 * Acquire the powerdomain spinlock on @pwrdm. No return value.
369 */
370void pwrdm_lock(struct powerdomain *pwrdm)
371 __acquires(&pwrdm->_lock)
372{
373 spin_lock_irqsave(&pwrdm->_lock, pwrdm->_lock_flags);
374}
375
376/**
377 * pwrdm_unlock - release a Linux spinlock on a powerdomain
378 * @pwrdm: struct powerdomain * to unlock
379 *
380 * Release the powerdomain spinlock on @pwrdm. No return value.
381 */
382void pwrdm_unlock(struct powerdomain *pwrdm)
383 __releases(&pwrdm->_lock)
384{
385 spin_unlock_irqrestore(&pwrdm->_lock, pwrdm->_lock_flags);
386}
387
388/**
278 * pwrdm_lookup - look up a powerdomain by name, return a pointer 389 * pwrdm_lookup - look up a powerdomain by name, return a pointer
279 * @name: name of powerdomain 390 * @name: name of powerdomain
280 * 391 *
@@ -920,65 +1031,27 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm)
920 return (pwrdm && pwrdm->flags & PWRDM_HAS_HDWR_SAR) ? 1 : 0; 1031 return (pwrdm && pwrdm->flags & PWRDM_HAS_HDWR_SAR) ? 1 : 0;
921} 1032}
922 1033
923/** 1034int pwrdm_state_switch_nolock(struct powerdomain *pwrdm)
924 * pwrdm_set_lowpwrstchange - Request a low power state change
925 * @pwrdm: struct powerdomain *
926 *
927 * Allows a powerdomain to transtion to a lower power sleep state
928 * from an existing sleep state without waking up the powerdomain.
929 * Returns -EINVAL if the powerdomain pointer is null or if the
930 * powerdomain does not support LOWPOWERSTATECHANGE, or returns 0
931 * upon success.
932 */
933int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
934{
935 int ret = -EINVAL;
936
937 if (!pwrdm)
938 return -EINVAL;
939
940 if (!(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE))
941 return -EINVAL;
942
943 pr_debug("powerdomain: %s: setting LOWPOWERSTATECHANGE bit\n",
944 pwrdm->name);
945
946 if (arch_pwrdm && arch_pwrdm->pwrdm_set_lowpwrstchange)
947 ret = arch_pwrdm->pwrdm_set_lowpwrstchange(pwrdm);
948
949 return ret;
950}
951
952/**
953 * pwrdm_wait_transition - wait for powerdomain power transition to finish
954 * @pwrdm: struct powerdomain * to wait for
955 *
956 * If the powerdomain @pwrdm is in the process of a state transition,
957 * spin until it completes the power transition, or until an iteration
958 * bailout value is reached. Returns -EINVAL if the powerdomain
959 * pointer is null, -EAGAIN if the bailout value was reached, or
960 * returns 0 upon success.
961 */
962int pwrdm_wait_transition(struct powerdomain *pwrdm)
963{ 1035{
964 int ret = -EINVAL; 1036 int ret;
965 1037
966 if (!pwrdm) 1038 if (!pwrdm || !arch_pwrdm)
967 return -EINVAL; 1039 return -EINVAL;
968 1040
969 if (arch_pwrdm && arch_pwrdm->pwrdm_wait_transition) 1041 ret = arch_pwrdm->pwrdm_wait_transition(pwrdm);
970 ret = arch_pwrdm->pwrdm_wait_transition(pwrdm); 1042 if (!ret)
1043 ret = _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW);
971 1044
972 return ret; 1045 return ret;
973} 1046}
974 1047
975int pwrdm_state_switch(struct powerdomain *pwrdm) 1048int __deprecated pwrdm_state_switch(struct powerdomain *pwrdm)
976{ 1049{
977 int ret; 1050 int ret;
978 1051
979 ret = pwrdm_wait_transition(pwrdm); 1052 pwrdm_lock(pwrdm);
980 if (!ret) 1053 ret = pwrdm_state_switch_nolock(pwrdm);
981 ret = _pwrdm_state_switch(pwrdm, PWRDM_STATE_NOW); 1054 pwrdm_unlock(pwrdm);
982 1055
983 return ret; 1056 return ret;
984} 1057}
@@ -1004,6 +1077,61 @@ int pwrdm_post_transition(struct powerdomain *pwrdm)
1004} 1077}
1005 1078
1006/** 1079/**
1080 * omap_set_pwrdm_state - change a powerdomain's current power state
1081 * @pwrdm: struct powerdomain * to change the power state of
1082 * @pwrst: power state to change to
1083 *
1084 * Change the current hardware power state of the powerdomain
1085 * represented by @pwrdm to the power state represented by @pwrst.
1086 * Returns -EINVAL if @pwrdm is null or invalid or if the
1087 * powerdomain's current power state could not be read, or returns 0
1088 * upon success or if @pwrdm does not support @pwrst or any
1089 * lower-power state. XXX Should not return 0 if the @pwrdm does not
1090 * support @pwrst or any lower-power state: this should be an error.
1091 */
1092int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
1093{
1094 u8 curr_pwrst, next_pwrst, sleep_switch;
1095 int ret = 0;
1096 bool hwsup = false;
1097
1098 if (!pwrdm || IS_ERR(pwrdm))
1099 return -EINVAL;
1100
1101 while (!(pwrdm->pwrsts & (1 << pwrst))) {
1102 if (pwrst == PWRDM_POWER_OFF)
1103 return ret;
1104 pwrst--;
1105 }
1106
1107 pwrdm_lock(pwrdm);
1108
1109 curr_pwrst = pwrdm_read_pwrst(pwrdm);
1110 next_pwrst = pwrdm_read_next_pwrst(pwrdm);
1111 if (curr_pwrst == pwrst && next_pwrst == pwrst)
1112 goto osps_out;
1113
1114 sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst,
1115 pwrst, &hwsup);
1116 if (sleep_switch == ERROR_SWITCH) {
1117 ret = -EINVAL;
1118 goto osps_out;
1119 }
1120
1121 ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
1122 if (ret)
1123 pr_err("%s: unable to set power state of powerdomain: %s\n",
1124 __func__, pwrdm->name);
1125
1126 _pwrdm_restore_clkdm_state(pwrdm, sleep_switch, hwsup);
1127
1128osps_out:
1129 pwrdm_unlock(pwrdm);
1130
1131 return ret;
1132}
1133
1134/**
1007 * pwrdm_get_context_loss_count - get powerdomain's context loss count 1135 * pwrdm_get_context_loss_count - get powerdomain's context loss count
1008 * @pwrdm: struct powerdomain * to wait for 1136 * @pwrdm: struct powerdomain * to wait for
1009 * 1137 *
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 5277d56eb37f..140c36074fed 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -19,8 +19,7 @@
19 19
20#include <linux/types.h> 20#include <linux/types.h>
21#include <linux/list.h> 21#include <linux/list.h>
22 22#include <linux/spinlock.h>
23#include <linux/atomic.h>
24 23
25#include "voltage.h" 24#include "voltage.h"
26 25
@@ -44,18 +43,20 @@
44#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON) 43#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
45 44
46 45
47/* Powerdomain flags */ 46/*
48#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ 47 * Powerdomain flags (struct powerdomain.flags)
49#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits 48 *
50 * in MEM bank 1 position. This is 49 * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support
51 * true for OMAP3430 50 *
52 */ 51 * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
53#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* 52 * bank 1 position. This is true for OMAP3430
54 * support to transition from a 53 *
55 * sleep state to a lower sleep 54 * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
56 * state without waking up the 55 * to a lower sleep state without waking up the powerdomain
57 * powerdomain 56 */
58 */ 57#define PWRDM_HAS_HDWR_SAR BIT(0)
58#define PWRDM_HAS_MPU_QUIRK BIT(1)
59#define PWRDM_HAS_LOWPOWERSTATECHANGE BIT(2)
59 60
60/* 61/*
61 * Number of memory banks that are power-controllable. On OMAP4430, the 62 * Number of memory banks that are power-controllable. On OMAP4430, the
@@ -103,6 +104,8 @@ struct powerdomain;
103 * @state_counter: 104 * @state_counter:
104 * @timer: 105 * @timer:
105 * @state_timer: 106 * @state_timer:
107 * @_lock: spinlock used to serialize powerdomain and some clockdomain ops
108 * @_lock_flags: stored flags when @_lock is taken
106 * 109 *
107 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. 110 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
108 */ 111 */
@@ -127,7 +130,8 @@ struct powerdomain {
127 unsigned state_counter[PWRDM_MAX_PWRSTS]; 130 unsigned state_counter[PWRDM_MAX_PWRSTS];
128 unsigned ret_logic_off_counter; 131 unsigned ret_logic_off_counter;
129 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; 132 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
130 133 spinlock_t _lock;
134 unsigned long _lock_flags;
131 const u8 pwrstctrl_offs; 135 const u8 pwrstctrl_offs;
132 const u8 pwrstst_offs; 136 const u8 pwrstst_offs;
133 const u32 logicretstate_mask; 137 const u32 logicretstate_mask;
@@ -162,6 +166,16 @@ struct powerdomain {
162 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd 166 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
163 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep 167 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
164 * @pwrdm_wait_transition: Wait for a pd state transition to complete 168 * @pwrdm_wait_transition: Wait for a pd state transition to complete
169 *
170 * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
171 * chips, a powerdomain's power state is not allowed to directly
172 * transition from one low-power state (e.g., CSWR) to another
173 * low-power state (e.g., OFF) without first waking up the
174 * powerdomain. This wastes energy. So OMAP4 chips support the
175 * ability to transition a powerdomain power state directly from one
176 * low-power state to another. The function pointed to by
177 * @pwrdm_set_lowpwrstchange is intended to configure the OMAP4
178 * hardware powerdomain state machine to enable this feature.
165 */ 179 */
166struct pwrdm_ops { 180struct pwrdm_ops {
167 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); 181 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
@@ -225,15 +239,15 @@ int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
225int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); 239int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
226bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); 240bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
227 241
228int pwrdm_wait_transition(struct powerdomain *pwrdm); 242int pwrdm_state_switch_nolock(struct powerdomain *pwrdm);
229
230int pwrdm_state_switch(struct powerdomain *pwrdm); 243int pwrdm_state_switch(struct powerdomain *pwrdm);
231int pwrdm_pre_transition(struct powerdomain *pwrdm); 244int pwrdm_pre_transition(struct powerdomain *pwrdm);
232int pwrdm_post_transition(struct powerdomain *pwrdm); 245int pwrdm_post_transition(struct powerdomain *pwrdm);
233int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
234int pwrdm_get_context_loss_count(struct powerdomain *pwrdm); 246int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
235bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm); 247bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
236 248
249extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
250
237extern void omap242x_powerdomains_init(void); 251extern void omap242x_powerdomains_init(void);
238extern void omap243x_powerdomains_init(void); 252extern void omap243x_powerdomains_init(void);
239extern void omap3xxx_powerdomains_init(void); 253extern void omap3xxx_powerdomains_init(void);
@@ -253,5 +267,7 @@ extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
253extern struct powerdomain wkup_omap2_pwrdm; 267extern struct powerdomain wkup_omap2_pwrdm;
254extern struct powerdomain gfx_omap2_pwrdm; 268extern struct powerdomain gfx_omap2_pwrdm;
255 269
270extern void pwrdm_lock(struct powerdomain *pwrdm);
271extern void pwrdm_unlock(struct powerdomain *pwrdm);
256 272
257#endif 273#endif
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index d3a5399091ad..7b946f1005b1 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -54,12 +54,12 @@ struct powerdomain gfx_omap2_pwrdm = {
54 .pwrsts_mem_on = { 54 .pwrsts_mem_on = {
55 [0] = PWRSTS_ON, /* MEMONSTATE */ 55 [0] = PWRSTS_ON, /* MEMONSTATE */
56 }, 56 },
57 .voltdm = { .name = "core" }, 57 .voltdm = { .name = "core" },
58}; 58};
59 59
60struct powerdomain wkup_omap2_pwrdm = { 60struct powerdomain wkup_omap2_pwrdm = {
61 .name = "wkup_pwrdm", 61 .name = "wkup_pwrdm",
62 .prcm_offs = WKUP_MOD, 62 .prcm_offs = WKUP_MOD,
63 .pwrsts = PWRSTS_ON, 63 .pwrsts = PWRSTS_ON,
64 .voltdm = { .name = "wakeup" }, 64 .voltdm = { .name = "wakeup" },
65}; 65};
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index ba520d4f7c7b..578eef86fcf2 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -38,7 +38,7 @@ static struct powerdomain dsp_pwrdm = {
38 .pwrsts_mem_on = { 38 .pwrsts_mem_on = {
39 [0] = PWRSTS_ON, 39 [0] = PWRSTS_ON,
40 }, 40 },
41 .voltdm = { .name = "core" }, 41 .voltdm = { .name = "core" },
42}; 42};
43 43
44static struct powerdomain mpu_24xx_pwrdm = { 44static struct powerdomain mpu_24xx_pwrdm = {
@@ -53,13 +53,14 @@ static struct powerdomain mpu_24xx_pwrdm = {
53 .pwrsts_mem_on = { 53 .pwrsts_mem_on = {
54 [0] = PWRSTS_ON, 54 [0] = PWRSTS_ON,
55 }, 55 },
56 .voltdm = { .name = "core" }, 56 .voltdm = { .name = "core" },
57}; 57};
58 58
59static struct powerdomain core_24xx_pwrdm = { 59static struct powerdomain core_24xx_pwrdm = {
60 .name = "core_pwrdm", 60 .name = "core_pwrdm",
61 .prcm_offs = CORE_MOD, 61 .prcm_offs = CORE_MOD,
62 .pwrsts = PWRSTS_OFF_RET_ON, 62 .pwrsts = PWRSTS_OFF_RET_ON,
63 .pwrsts_logic_ret = PWRSTS_RET,
63 .banks = 3, 64 .banks = 3,
64 .pwrsts_mem_ret = { 65 .pwrsts_mem_ret = {
65 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ 66 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
@@ -71,7 +72,7 @@ static struct powerdomain core_24xx_pwrdm = {
71 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ 72 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
72 [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */ 73 [2] = PWRSTS_OFF_RET_ON, /* MEM3ONSTATE */
73 }, 74 },
74 .voltdm = { .name = "core" }, 75 .voltdm = { .name = "core" },
75}; 76};
76 77
77 78
@@ -93,7 +94,7 @@ static struct powerdomain mdm_pwrdm = {
93 .pwrsts_mem_on = { 94 .pwrsts_mem_on = {
94 [0] = PWRSTS_ON, /* MEMONSTATE */ 95 [0] = PWRSTS_ON, /* MEMONSTATE */
95 }, 96 },
96 .voltdm = { .name = "core" }, 97 .voltdm = { .name = "core" },
97}; 98};
98 99
99/* 100/*
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index 8b23d234fb55..f0e14e9efe5a 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -50,7 +50,7 @@ static struct powerdomain iva2_pwrdm = {
50 [2] = PWRSTS_OFF_ON, 50 [2] = PWRSTS_OFF_ON,
51 [3] = PWRSTS_ON, 51 [3] = PWRSTS_ON,
52 }, 52 },
53 .voltdm = { .name = "mpu_iva" }, 53 .voltdm = { .name = "mpu_iva" },
54}; 54};
55 55
56static struct powerdomain mpu_3xxx_pwrdm = { 56static struct powerdomain mpu_3xxx_pwrdm = {
@@ -66,7 +66,7 @@ static struct powerdomain mpu_3xxx_pwrdm = {
66 .pwrsts_mem_on = { 66 .pwrsts_mem_on = {
67 [0] = PWRSTS_OFF_ON, 67 [0] = PWRSTS_OFF_ON,
68 }, 68 },
69 .voltdm = { .name = "mpu_iva" }, 69 .voltdm = { .name = "mpu_iva" },
70}; 70};
71 71
72static struct powerdomain mpu_am35x_pwrdm = { 72static struct powerdomain mpu_am35x_pwrdm = {
@@ -82,7 +82,7 @@ static struct powerdomain mpu_am35x_pwrdm = {
82 .pwrsts_mem_on = { 82 .pwrsts_mem_on = {
83 [0] = PWRSTS_ON, 83 [0] = PWRSTS_ON,
84 }, 84 },
85 .voltdm = { .name = "mpu_iva" }, 85 .voltdm = { .name = "mpu_iva" },
86}; 86};
87 87
88/* 88/*
@@ -109,7 +109,7 @@ static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
109 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ 109 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
110 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ 110 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
111 }, 111 },
112 .voltdm = { .name = "core" }, 112 .voltdm = { .name = "core" },
113}; 113};
114 114
115static struct powerdomain core_3xxx_es3_1_pwrdm = { 115static struct powerdomain core_3xxx_es3_1_pwrdm = {
@@ -131,7 +131,7 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
131 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ 131 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
132 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ 132 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
133 }, 133 },
134 .voltdm = { .name = "core" }, 134 .voltdm = { .name = "core" },
135}; 135};
136 136
137static struct powerdomain core_am35x_pwrdm = { 137static struct powerdomain core_am35x_pwrdm = {
@@ -148,7 +148,7 @@ static struct powerdomain core_am35x_pwrdm = {
148 [0] = PWRSTS_ON, /* MEM1ONSTATE */ 148 [0] = PWRSTS_ON, /* MEM1ONSTATE */
149 [1] = PWRSTS_ON, /* MEM2ONSTATE */ 149 [1] = PWRSTS_ON, /* MEM2ONSTATE */
150 }, 150 },
151 .voltdm = { .name = "core" }, 151 .voltdm = { .name = "core" },
152}; 152};
153 153
154static struct powerdomain dss_pwrdm = { 154static struct powerdomain dss_pwrdm = {
@@ -163,7 +163,7 @@ static struct powerdomain dss_pwrdm = {
163 .pwrsts_mem_on = { 163 .pwrsts_mem_on = {
164 [0] = PWRSTS_ON, /* MEMONSTATE */ 164 [0] = PWRSTS_ON, /* MEMONSTATE */
165 }, 165 },
166 .voltdm = { .name = "core" }, 166 .voltdm = { .name = "core" },
167}; 167};
168 168
169static struct powerdomain dss_am35x_pwrdm = { 169static struct powerdomain dss_am35x_pwrdm = {
@@ -178,7 +178,7 @@ static struct powerdomain dss_am35x_pwrdm = {
178 .pwrsts_mem_on = { 178 .pwrsts_mem_on = {
179 [0] = PWRSTS_ON, /* MEMONSTATE */ 179 [0] = PWRSTS_ON, /* MEMONSTATE */
180 }, 180 },
181 .voltdm = { .name = "core" }, 181 .voltdm = { .name = "core" },
182}; 182};
183 183
184/* 184/*
@@ -199,7 +199,7 @@ static struct powerdomain sgx_pwrdm = {
199 .pwrsts_mem_on = { 199 .pwrsts_mem_on = {
200 [0] = PWRSTS_ON, /* MEMONSTATE */ 200 [0] = PWRSTS_ON, /* MEMONSTATE */
201 }, 201 },
202 .voltdm = { .name = "core" }, 202 .voltdm = { .name = "core" },
203}; 203};
204 204
205static struct powerdomain sgx_am35x_pwrdm = { 205static struct powerdomain sgx_am35x_pwrdm = {
@@ -214,7 +214,7 @@ static struct powerdomain sgx_am35x_pwrdm = {
214 .pwrsts_mem_on = { 214 .pwrsts_mem_on = {
215 [0] = PWRSTS_ON, /* MEMONSTATE */ 215 [0] = PWRSTS_ON, /* MEMONSTATE */
216 }, 216 },
217 .voltdm = { .name = "core" }, 217 .voltdm = { .name = "core" },
218}; 218};
219 219
220static struct powerdomain cam_pwrdm = { 220static struct powerdomain cam_pwrdm = {
@@ -229,7 +229,7 @@ static struct powerdomain cam_pwrdm = {
229 .pwrsts_mem_on = { 229 .pwrsts_mem_on = {
230 [0] = PWRSTS_ON, /* MEMONSTATE */ 230 [0] = PWRSTS_ON, /* MEMONSTATE */
231 }, 231 },
232 .voltdm = { .name = "core" }, 232 .voltdm = { .name = "core" },
233}; 233};
234 234
235static struct powerdomain per_pwrdm = { 235static struct powerdomain per_pwrdm = {
@@ -244,7 +244,7 @@ static struct powerdomain per_pwrdm = {
244 .pwrsts_mem_on = { 244 .pwrsts_mem_on = {
245 [0] = PWRSTS_ON, /* MEMONSTATE */ 245 [0] = PWRSTS_ON, /* MEMONSTATE */
246 }, 246 },
247 .voltdm = { .name = "core" }, 247 .voltdm = { .name = "core" },
248}; 248};
249 249
250static struct powerdomain per_am35x_pwrdm = { 250static struct powerdomain per_am35x_pwrdm = {
@@ -259,13 +259,13 @@ static struct powerdomain per_am35x_pwrdm = {
259 .pwrsts_mem_on = { 259 .pwrsts_mem_on = {
260 [0] = PWRSTS_ON, /* MEMONSTATE */ 260 [0] = PWRSTS_ON, /* MEMONSTATE */
261 }, 261 },
262 .voltdm = { .name = "core" }, 262 .voltdm = { .name = "core" },
263}; 263};
264 264
265static struct powerdomain emu_pwrdm = { 265static struct powerdomain emu_pwrdm = {
266 .name = "emu_pwrdm", 266 .name = "emu_pwrdm",
267 .prcm_offs = OMAP3430_EMU_MOD, 267 .prcm_offs = OMAP3430_EMU_MOD,
268 .voltdm = { .name = "core" }, 268 .voltdm = { .name = "core" },
269}; 269};
270 270
271static struct powerdomain neon_pwrdm = { 271static struct powerdomain neon_pwrdm = {
@@ -273,7 +273,7 @@ static struct powerdomain neon_pwrdm = {
273 .prcm_offs = OMAP3430_NEON_MOD, 273 .prcm_offs = OMAP3430_NEON_MOD,
274 .pwrsts = PWRSTS_OFF_RET_ON, 274 .pwrsts = PWRSTS_OFF_RET_ON,
275 .pwrsts_logic_ret = PWRSTS_RET, 275 .pwrsts_logic_ret = PWRSTS_RET,
276 .voltdm = { .name = "mpu_iva" }, 276 .voltdm = { .name = "mpu_iva" },
277}; 277};
278 278
279static struct powerdomain neon_am35x_pwrdm = { 279static struct powerdomain neon_am35x_pwrdm = {
@@ -281,7 +281,7 @@ static struct powerdomain neon_am35x_pwrdm = {
281 .prcm_offs = OMAP3430_NEON_MOD, 281 .prcm_offs = OMAP3430_NEON_MOD,
282 .pwrsts = PWRSTS_ON, 282 .pwrsts = PWRSTS_ON,
283 .pwrsts_logic_ret = PWRSTS_ON, 283 .pwrsts_logic_ret = PWRSTS_ON,
284 .voltdm = { .name = "mpu_iva" }, 284 .voltdm = { .name = "mpu_iva" },
285}; 285};
286 286
287static struct powerdomain usbhost_pwrdm = { 287static struct powerdomain usbhost_pwrdm = {
@@ -303,37 +303,37 @@ static struct powerdomain usbhost_pwrdm = {
303 .pwrsts_mem_on = { 303 .pwrsts_mem_on = {
304 [0] = PWRSTS_ON, /* MEMONSTATE */ 304 [0] = PWRSTS_ON, /* MEMONSTATE */
305 }, 305 },
306 .voltdm = { .name = "core" }, 306 .voltdm = { .name = "core" },
307}; 307};
308 308
309static struct powerdomain dpll1_pwrdm = { 309static struct powerdomain dpll1_pwrdm = {
310 .name = "dpll1_pwrdm", 310 .name = "dpll1_pwrdm",
311 .prcm_offs = MPU_MOD, 311 .prcm_offs = MPU_MOD,
312 .voltdm = { .name = "mpu_iva" }, 312 .voltdm = { .name = "mpu_iva" },
313}; 313};
314 314
315static struct powerdomain dpll2_pwrdm = { 315static struct powerdomain dpll2_pwrdm = {
316 .name = "dpll2_pwrdm", 316 .name = "dpll2_pwrdm",
317 .prcm_offs = OMAP3430_IVA2_MOD, 317 .prcm_offs = OMAP3430_IVA2_MOD,
318 .voltdm = { .name = "mpu_iva" }, 318 .voltdm = { .name = "mpu_iva" },
319}; 319};
320 320
321static struct powerdomain dpll3_pwrdm = { 321static struct powerdomain dpll3_pwrdm = {
322 .name = "dpll3_pwrdm", 322 .name = "dpll3_pwrdm",
323 .prcm_offs = PLL_MOD, 323 .prcm_offs = PLL_MOD,
324 .voltdm = { .name = "core" }, 324 .voltdm = { .name = "core" },
325}; 325};
326 326
327static struct powerdomain dpll4_pwrdm = { 327static struct powerdomain dpll4_pwrdm = {
328 .name = "dpll4_pwrdm", 328 .name = "dpll4_pwrdm",
329 .prcm_offs = PLL_MOD, 329 .prcm_offs = PLL_MOD,
330 .voltdm = { .name = "core" }, 330 .voltdm = { .name = "core" },
331}; 331};
332 332
333static struct powerdomain dpll5_pwrdm = { 333static struct powerdomain dpll5_pwrdm = {
334 .name = "dpll5_pwrdm", 334 .name = "dpll5_pwrdm",
335 .prcm_offs = PLL_MOD, 335 .prcm_offs = PLL_MOD,
336 .voltdm = { .name = "core" }, 336 .voltdm = { .name = "core" },
337}; 337};
338 338
339/* As powerdomains are added or removed above, this list must also be changed */ 339/* As powerdomains are added or removed above, this list must also be changed */
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index a3e121f94a86..947f6adfed0c 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -210,6 +210,7 @@ int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
210 PM_WKDEP, (1 << clkdm2->dep_bit)); 210 PM_WKDEP, (1 << clkdm2->dep_bit));
211} 211}
212 212
213/* XXX Caller must hold the clkdm's powerdomain lock */
213int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm) 214int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
214{ 215{
215 struct clkdm_dep *cd; 216 struct clkdm_dep *cd;
@@ -221,7 +222,7 @@ int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
221 222
222 /* PRM accesses are slow, so minimize them */ 223 /* PRM accesses are slow, so minimize them */
223 mask |= 1 << cd->clkdm->dep_bit; 224 mask |= 1 << cd->clkdm->dep_bit;
224 atomic_set(&cd->wkdep_usecount, 0); 225 cd->wkdep_usecount = 0;
225 } 226 }
226 227
227 omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, 228 omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 04fdbc4c499b..d01c373cbbef 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -316,8 +316,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
316 if (WARN_ON(!oh)) 316 if (WARN_ON(!oh))
317 return; 317 return;
318 318
319 pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size, 319 pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size);
320 NULL, 0, false);
321 if (IS_ERR(pdev)) { 320 if (IS_ERR(pdev)) {
322 WARN(1, "Could not build omap_device for %s: %s.\n", name, 321 WARN(1, "Could not build omap_device for %s: %s.\n", name,
323 oh->name); 322 oh->name);
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
index ce0ccd26efbd..1d3cb25c9629 100644
--- a/arch/arm/mach-omap2/sleep24xx.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -37,25 +37,6 @@
37 .text 37 .text
38 38
39/* 39/*
40 * Forces OMAP into idle state
41 *
42 * omap24xx_idle_loop_suspend() - This bit of code just executes the WFI
43 * for normal idles.
44 *
45 * Note: This code get's copied to internal SRAM at boot. When the OMAP
46 * wakes up it continues execution at the point it went to sleep.
47 */
48 .align 3
49ENTRY(omap24xx_idle_loop_suspend)
50 stmfd sp!, {r0, lr} @ save registers on stack
51 mov r0, #0 @ clear for mcr setup
52 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
53 ldmfd sp!, {r0, pc} @ restore regs and return
54
55ENTRY(omap24xx_idle_loop_suspend_sz)
56 .word . - omap24xx_idle_loop_suspend
57
58/*
59 * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing 40 * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
60 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore 41 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
61 * SDRC. 42 * SDRC.
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index b9753fe27232..d7bc33f15344 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -152,8 +152,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
152 152
153 sr_data->enable_on_init = sr_enable_on_init; 153 sr_data->enable_on_init = sr_enable_on_init;
154 154
155 pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data), 155 pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data));
156 NULL, 0, 0);
157 if (IS_ERR(pdev)) 156 if (IS_ERR(pdev))
158 pr_warning("%s: Could not build omap_device for %s: %s.\n\n", 157 pr_warning("%s: Could not build omap_device for %s: %s.\n\n",
159 __func__, name, oh->name); 158 __func__, name, oh->name);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index b8ad6e632bb8..63e5fb017fd8 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -702,8 +702,7 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
702 pdata->timer_errata = omap_dm_timer_get_errata(); 702 pdata->timer_errata = omap_dm_timer_get_errata();
703 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; 703 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
704 704
705 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), 705 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata));
706 NULL, 0, 0);
707 706
708 if (IS_ERR(pdev)) { 707 if (IS_ERR(pdev)) {
709 pr_err("%s: Can't build omap_device for %s: %s.\n", 708 pr_err("%s: Can't build omap_device for %s: %s.\n",
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 2e44e8a22884..99f04deb4c7f 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -42,14 +42,6 @@ static struct usbtll_omap_platform_data usbtll_data;
42static struct ehci_hcd_omap_platform_data ehci_data; 42static struct ehci_hcd_omap_platform_data ehci_data;
43static struct ohci_hcd_omap_platform_data ohci_data; 43static struct ohci_hcd_omap_platform_data ohci_data;
44 44
45static struct omap_device_pm_latency omap_uhhtll_latency[] = {
46 {
47 .deactivate_func = omap_device_idle_hwmods,
48 .activate_func = omap_device_enable_hwmods,
49 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
50 },
51};
52
53/* MUX settings for EHCI pins */ 45/* MUX settings for EHCI pins */
54/* 46/*
55 * setup_ehci_io_mux - initialize IO pad mux for USBHOST 47 * setup_ehci_io_mux - initialize IO pad mux for USBHOST
@@ -530,9 +522,7 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
530 } 522 }
531 523
532 pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm, 524 pdev = omap_device_build(OMAP_USBTLL_DEVICE, bus_id, tll_hwm,
533 &usbtll_data, sizeof(usbtll_data), 525 &usbtll_data, sizeof(usbtll_data));
534 omap_uhhtll_latency,
535 ARRAY_SIZE(omap_uhhtll_latency), false);
536 if (IS_ERR(pdev)) { 526 if (IS_ERR(pdev)) {
537 pr_err("Could not build hwmod device %s\n", 527 pr_err("Could not build hwmod device %s\n",
538 USBHS_TLL_HWMODNAME); 528 USBHS_TLL_HWMODNAME);
@@ -540,9 +530,7 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
540 } 530 }
541 531
542 pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm, 532 pdev = omap_device_build(OMAP_USBHS_DEVICE, bus_id, uhh_hwm,
543 &usbhs_data, sizeof(usbhs_data), 533 &usbhs_data, sizeof(usbhs_data));
544 omap_uhhtll_latency,
545 ARRAY_SIZE(omap_uhhtll_latency), false);
546 if (IS_ERR(pdev)) { 534 if (IS_ERR(pdev)) {
547 pr_err("Could not build hwmod devices %s\n", 535 pr_err("Could not build hwmod devices %s\n",
548 USBHS_UHH_HWMODNAME); 536 USBHS_UHH_HWMODNAME);
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 7b33b375fe77..8c4de2708cf2 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -102,7 +102,7 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
102 return; 102 return;
103 103
104 pdev = omap_device_build(name, bus_id, oh, &musb_plat, 104 pdev = omap_device_build(name, bus_id, oh, &musb_plat,
105 sizeof(musb_plat), NULL, 0, false); 105 sizeof(musb_plat));
106 if (IS_ERR(pdev)) { 106 if (IS_ERR(pdev)) {
107 pr_err("Could not build omap_device for %s %s\n", 107 pr_err("Could not build omap_device for %s %s\n",
108 name, oh_name); 108 name, oh_name);
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index 7c2b4ed38f02..910243f54a05 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -124,8 +124,7 @@ static int __init omap_init_wdt(void)
124 pdata.read_reset_sources = prm_read_reset_sources; 124 pdata.read_reset_sources = prm_read_reset_sources;
125 125
126 pdev = omap_device_build(dev_name, id, oh, &pdata, 126 pdev = omap_device_build(dev_name, id, oh, &pdata,
127 sizeof(struct omap_wd_timer_platform_data), 127 sizeof(struct omap_wd_timer_platform_data));
128 NULL, 0, 0);
129 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", 128 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
130 dev_name, oh->name); 129 dev_name, oh->name);
131 return 0; 130 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 19:32:52 -0500