Merge branch 'omap/fixes-non-critical' into late/cleanup

* omap/fixes-non-critical:
  ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS"
  ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD"
  ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass
  ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0
  ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag
  ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk
  ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry
  ARM: OMAP: fix typo "CONFIG_SMC91x_MODULE"
  ARM: OMAP5: clock: No Freqsel on OMAP5 devices too
  ARM: OMAP5: Make errata i688 workaround available
  ARM: OMAP5: Update SAR memory layout for WakeupGen
  ARM: OMAP5: Update SAR RAM base address
  ARM: OMAP5: Reuse prm read_inst/write_inst
  ARM: OMAP5: prm: Allow prm init to succeed
  ARM: OMAP5: timer: Update the clocksource name as per clock data
  ARM: OMAP5: Update SOC id detection code for ES2

18 files changed, 94 insertions, 56 deletions

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 8111cd9ff3e5..b9c0ed3f648c 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -408,7 +408,7 @@ config OMAP3_SDRC_AC_TIMING
 
 config OMAP4_ERRATA_I688
         bool "OMAP4 errata: Async Bridge Corruption"
-        depends on ARCH_OMAP4 && !ARCH_MULTIPLATFORM
+        depends on (ARCH_OMAP4 || SOC_OMAP5) && !ARCH_MULTIPLATFORM
         select ARCH_HAS_BARRIERS
         help
           If a data is stalled inside asynchronous bridge because of back
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index a3e0aaa4886b..cb0596b631cf 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -166,7 +166,7 @@ static void __init sdp2430_display_init(void)
         omap_display_init(&sdp2430_dss_data);
 }
 
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 
 static struct omap_smc91x_platform_data board_smc91x_data = {
         .cs             = 5,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 812c829fa46f..5b4ec51c385f 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -246,7 +246,7 @@ static u32 is_gpmc_muxed(void)
                 return 0;
 }
 
-#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91x_MODULE)
+#if IS_ENABLED(CONFIG_SMC91X)
 
 static struct omap_smc91x_platform_data board_smc91x_data = {
         .cs             = 1,
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 476b82066cb6..7f091c85384e 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -958,6 +958,14 @@ int __init am33xx_clk_init(void)
 
         clk_set_parent(&timer3_fck, &sys_clkin_ck);
         clk_set_parent(&timer6_fck, &sys_clkin_ck);
+        /*
+         * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
+         * the design/spec, so as a result, for example, timer which supposed
+         * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
+         * not expected by any use-case, so change WDT1 clock source to PRCM
+         * 32KHz clock.
+         */
+        clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3aed4b0b9563..3a0296cfcace 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -307,10 +307,10 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
         _omap3_noncore_dpll_bypass(clk);
 
         /*
-         * Set jitter correction. No jitter correction for OMAP4 and 3630
-         * since freqsel field is no longer present
+         * Set jitter correction. Jitter correction applicable for OMAP343X
+         * only since freqsel field is no longer present on other devices.
          */
-        if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()) {
+        if (cpu_is_omap343x()) {
                 v = __raw_readl(dd->control_reg);
                 v &= ~dd->freqsel_mask;
                 v |= freqsel << __ffs(dd->freqsel_mask);
@@ -480,29 +480,30 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
         if (!dd)
                 return -EINVAL;
 
-        __clk_prepare(dd->clk_bypass);
-        clk_enable(dd->clk_bypass);
-        __clk_prepare(dd->clk_ref);
-        clk_enable(dd->clk_ref);
-
         if (__clk_get_rate(dd->clk_bypass) == rate &&
             (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
                 pr_debug("%s: %s: set rate: entering bypass.\n",
                          __func__, __clk_get_name(hw->clk));
 
+                __clk_prepare(dd->clk_bypass);
+                clk_enable(dd->clk_bypass);
                 ret = _omap3_noncore_dpll_bypass(clk);
                 if (!ret)
                         new_parent = dd->clk_bypass;
+                clk_disable(dd->clk_bypass);
+                __clk_unprepare(dd->clk_bypass);
         } else {
+                __clk_prepare(dd->clk_ref);
+                clk_enable(dd->clk_ref);
+
                 if (dd->last_rounded_rate != rate)
                         rate = __clk_round_rate(hw->clk, rate);
 
                 if (dd->last_rounded_rate == 0)
                         return -EINVAL;
 
-                /* No freqsel on AM335x, OMAP4 and OMAP3630 */
-                if (!soc_is_am33xx() && !cpu_is_omap44xx() &&
-                    !cpu_is_omap3630()) {
+                /* Freqsel is available only on OMAP343X devices */
+                if (cpu_is_omap343x()) {
                         freqsel = _omap3_dpll_compute_freqsel(clk,
                                                 dd->last_rounded_n);
                         WARN_ON(!freqsel);
@@ -514,6 +515,8 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
                 ret = omap3_noncore_dpll_program(clk, freqsel);
                 if (!ret)
                         new_parent = dd->clk_ref;
+                clk_disable(dd->clk_ref);
+                __clk_unprepare(dd->clk_ref);
         }
         /*
         * FIXME - this is all wrong.  common code handles reparenting and
@@ -525,11 +528,6 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
         if (!ret)
                 __clk_reparent(hw->clk, new_parent);
 
-        clk_disable(dd->clk_ref);
-        __clk_unprepare(dd->clk_ref);
-        clk_disable(dd->clk_bypass);
-        __clk_unprepare(dd->clk_bypass);
-
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index b155500e84a8..b8208b4b1bd9 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -26,7 +26,7 @@
 #include "control.h"
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
-#ifdef CONFIG_BRIDGE_DVFS
+#ifdef CONFIG_TIDSPBRIDGE_DVFS
 #include "omap-pm.h"
 #endif
 
@@ -35,7 +35,7 @@
 static struct platform_device *omap_dsp_pdev;
 
 static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
-#ifdef CONFIG_BRIDGE_DVFS
+#ifdef CONFIG_TIDSPBRIDGE_DVFS
         .dsp_set_min_opp = omap_pm_dsp_set_min_opp,
         .dsp_get_opp = omap_pm_dsp_get_opp,
         .cpu_set_freq = omap_pm_cpu_set_freq,
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 8a68f1ec66b9..ff0bc9e51aa7 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -529,22 +529,28 @@ void __init omap5xxx_check_revision(void)
         case 0xb942:
                 switch (rev) {
                 case 0:
-                default:
                         omap_revision = OMAP5430_REV_ES1_0;
+                        break;
+                case 1:
+                default:
+                        omap_revision = OMAP5430_REV_ES2_0;
                 }
                 break;
 
         case 0xb998:
                 switch (rev) {
                 case 0:
-                default:
                         omap_revision = OMAP5432_REV_ES1_0;
+                        break;
+                case 1:
+                default:
+                        omap_revision = OMAP5432_REV_ES2_0;
                 }
                 break;
 
         default:
                 /* Unknown default to latest silicon rev as default*/
-                omap_revision = OMAP5430_REV_ES1_0;
+                omap_revision = OMAP5430_REV_ES2_0;
         }
 
         pr_info("OMAP%04x ES%d.0\n",
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5c445ca1e271..e210fa830f8d 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -277,6 +277,14 @@ static struct map_desc omap54xx_io_desc[] __initdata = {
                 .length         = L4_PER_54XX_SIZE,
                 .type           = MT_DEVICE,
         },
+#ifdef CONFIG_OMAP4_ERRATA_I688
+        {
+                .virtual        = OMAP4_SRAM_VA,
+                .pfn            = __phys_to_pfn(OMAP4_SRAM_PA),
+                .length         = PAGE_SIZE,
+                .type           = MT_MEMORY_SO,
+        },
+#endif
 };
 #endif
 
@@ -329,6 +337,7 @@ void __init omap4_map_io(void)
 void __init omap5_map_io(void)
 {
         iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
+        omap_barriers_init();
 }
 #endif
 /*
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 708bb115a27f..2aeb928efdfd 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -240,15 +240,21 @@ void __iomem *omap4_get_sar_ram_base(void)
  */
 static int __init omap4_sar_ram_init(void)
 {
+        unsigned long sar_base;
+
         /*
          * To avoid code running on other OMAPs in
          * multi-omap builds
          */
-        if (!cpu_is_omap44xx())
+        if (cpu_is_omap44xx())
+                sar_base = OMAP44XX_SAR_RAM_BASE;
+        else if (soc_is_omap54xx())
+                sar_base = OMAP54XX_SAR_RAM_BASE;
+        else
                 return -ENOMEM;
 
         /* Static mapping, never released */
-        sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
+        sar_ram_base = ioremap(sar_base, SZ_16K);
         if (WARN_ON(!sar_ram_base))
                 return -ENOMEM;
 
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index e170fe803b04..937417523b8e 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -48,13 +48,13 @@
 #define SAR_BACKUP_STATUS_WAKEUPGEN             0x10
 
 /* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
-#define OMAP5_WAKEUPGENENB_OFFSET_CPU0          (SAR_BANK3_OFFSET + 0x8d4)
-#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0   (SAR_BANK3_OFFSET + 0x8e8)
-#define OMAP5_WAKEUPGENENB_OFFSET_CPU1          (SAR_BANK3_OFFSET + 0x8fc)
-#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1   (SAR_BANK3_OFFSET + 0x910)
-#define OMAP5_AUXCOREBOOT0_OFFSET               (SAR_BANK3_OFFSET + 0x924)
-#define OMAP5_AUXCOREBOOT1_OFFSET               (SAR_BANK3_OFFSET + 0x928)
-#define OMAP5_AMBA_IF_MODE_OFFSET               (SAR_BANK3_OFFSET + 0x92c)
+#define OMAP5_WAKEUPGENENB_OFFSET_CPU0          (SAR_BANK3_OFFSET + 0x9dc)
+#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0   (SAR_BANK3_OFFSET + 0x9f0)
+#define OMAP5_WAKEUPGENENB_OFFSET_CPU1          (SAR_BANK3_OFFSET + 0xa04)
+#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1   (SAR_BANK3_OFFSET + 0xa18)
+#define OMAP5_AUXCOREBOOT0_OFFSET               (SAR_BANK3_OFFSET + 0xa2c)
+#define OMAP5_AUXCOREBOOT1_OFFSET               (SAR_BANK3_OFFSET + 0x930)
+#define OMAP5_AMBA_IF_MODE_OFFSET               (SAR_BANK3_OFFSET + 0xa34)
 #define OMAP5_SAR_BACKUP_STATUS_OFFSET          (SAR_BANK3_OFFSET + 0x800)
 
 #endif
diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h
index a2582bb3cab3..a086ba15868b 100644
--- a/arch/arm/mach-omap2/omap54xx.h
+++ b/arch/arm/mach-omap2/omap54xx.h
@@ -28,5 +28,6 @@
 #define OMAP54XX_PRCM_MPU_BASE          0x48243000
 #define OMAP54XX_SCM_BASE               0x4a002000
 #define OMAP54XX_CTRL_BASE              0x4a002800
+#define OMAP54XX_SAR_RAM_BASE           0x4ae26000
 
 #endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index a202a4785104..5f33c2da6999 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -610,8 +610,6 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
 
         /* XXX test pwrdm_get_wken for this hwmod's subsystem */
 
-        oh->_int_flags |= _HWMOD_WAKEUP_ENABLED;
-
         return 0;
 }
 
@@ -645,8 +643,6 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
 
         /* XXX test pwrdm_get_wken for this hwmod's subsystem */
 
-        oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED;
-
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index d5dc935f6060..fe5962921f07 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -482,15 +482,13 @@ struct omap_hwmod_omap4_prcm {
  * These are for internal use only and are managed by the omap_hwmod code.
  *
  * _HWMOD_NO_MPU_PORT: no path exists for the MPU to write to this module
- * _HWMOD_WAKEUP_ENABLED: set when the omap_hwmod code has enabled ENAWAKEUP
  * _HWMOD_SYSCONFIG_LOADED: set when the OCP_SYSCONFIG value has been cached
  * _HWMOD_SKIP_ENABLE: set if hwmod enabled during init (HWMOD_INIT_NO_IDLE) -
  *     causes the first call to _enable() to only update the pinmux
  */
 #define _HWMOD_NO_MPU_PORT                      (1 << 0)
-#define _HWMOD_WAKEUP_ENABLED                   (1 << 1)
-#define _HWMOD_SYSCONFIG_LOADED                 (1 << 2)
-#define _HWMOD_SKIP_ENABLE                      (1 << 3)
+#define _HWMOD_SYSCONFIG_LOADED                 (1 << 1)
+#define _HWMOD_SKIP_ENABLE                      (1 << 2)
 
 /*
  * omap_hwmod._state definitions
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 26eee4a556ad..31bea1ce3de1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -28,6 +28,7 @@
 #include "prm-regbits-33xx.h"
 #include "i2c.h"
 #include "mmc.h"
+#include "wd_timer.h"
 
 /*
  * IP blocks
@@ -2087,8 +2088,21 @@ static struct omap_hwmod am33xx_uart6_hwmod = {
 };
 
 /* 'wd_timer' class */
+static struct omap_hwmod_class_sysconfig wdt_sysc = {
+        .rev_offs       = 0x0,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+                        SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                        SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
         .name           = "wd_timer",
+        .sysc           = &wdt_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable,
 };
 
 /*
@@ -2099,6 +2113,7 @@ static struct omap_hwmod am33xx_wd_timer1_hwmod = {
         .name           = "wd_timer2",
         .class          = &am33xx_wd_timer_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
         .main_clk       = "wdt1_fck",
         .prcm           = {
                 .omap4  = {
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 8e61d80bf6b3..89cad4a605dd 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -52,7 +52,6 @@ enum {
 #define ALREADYACTIVE_SWITCH            0
 #define FORCEWAKEUP_SWITCH              1
 #define LOWPOWERSTATE_SWITCH            2
-#define ERROR_SWITCH                    3
 
 /* pwrdm_list contains all registered struct powerdomains */
 static LIST_HEAD(pwrdm_list);
@@ -233,10 +232,7 @@ static u8 _pwrdm_save_clkdm_state_and_activate(struct powerdomain *pwrdm,
 {
         u8 sleep_switch;
 
-        if (curr_pwrst < 0) {
-                WARN_ON(1);
-                sleep_switch = ERROR_SWITCH;
-        } else if (curr_pwrst < PWRDM_POWER_ON) {
+        if (curr_pwrst < PWRDM_POWER_ON) {
                 if (curr_pwrst > pwrst &&
                     pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE &&
                     arch_pwrdm->pwrdm_set_lowpwrstchange) {
@@ -1091,7 +1087,8 @@ int pwrdm_post_transition(struct powerdomain *pwrdm)
  */
 int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
 {
-        u8 curr_pwrst, next_pwrst, sleep_switch;
+        u8 next_pwrst, sleep_switch;
+        int curr_pwrst;
         int ret = 0;
         bool hwsup = false;
 
@@ -1107,16 +1104,17 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 pwrst)
         pwrdm_lock(pwrdm);
 
         curr_pwrst = pwrdm_read_pwrst(pwrdm);
+        if (curr_pwrst < 0) {
+                ret = -EINVAL;
+                goto osps_out;
+        }
+
         next_pwrst = pwrdm_read_next_pwrst(pwrdm);
         if (curr_pwrst == pwrst && next_pwrst == pwrst)
                 goto osps_out;
 
         sleep_switch = _pwrdm_save_clkdm_state_and_activate(pwrdm, curr_pwrst,
                                                             pwrst, &hwsup);
-        if (sleep_switch == ERROR_SWITCH) {
-                ret = -EINVAL;
-                goto osps_out;
-        }
 
         ret = pwrdm_set_next_pwrst(pwrdm, pwrst);
         if (ret)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index d35f98aabf7a..415c7e0c9393 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -81,13 +81,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
 /* Read a register in a CM/PRM instance in the PRM module */
 u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
 {
-        return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg));
+        return __raw_readl(prm_base + inst + reg);
 }
 
 /* Write into a register in a CM/PRM instance in the PRM module */
 void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
-        __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg));
+        __raw_writel(val, prm_base + inst + reg);
 }
 
 /* Read-modify-write a register in a PRM module. Caller must lock */
@@ -650,7 +650,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
 
 int __init omap44xx_prm_init(void)
 {
-        if (!cpu_is_omap44xx())
+        if (!cpu_is_omap44xx() && !soc_is_omap54xx())
                 return 0;
 
         return prm_register(&omap44xx_prm_ll_data);
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index c62116bbc760..18fdeeb3a44a 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -413,7 +413,9 @@ IS_OMAP_TYPE(3430, 0x3430)
 
 #define OMAP54XX_CLASS          0x54000054
 #define OMAP5430_REV_ES1_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
+#define OMAP5430_REV_ES2_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
 #define OMAP5432_REV_ES1_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
+#define OMAP5432_REV_ES2_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
 
 void omap2xxx_check_revision(void);
 void omap3xxx_check_revision(void);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index f62b509ed08d..d00d89c93f1c 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -62,6 +62,7 @@
 #define OMAP2_MPU_SOURCE        "sys_ck"
 #define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
 #define OMAP4_MPU_SOURCE        "sys_clkin_ck"
+#define OMAP5_MPU_SOURCE        "sys_clkin"
 #define OMAP2_32K_SOURCE        "func_32k_ck"
 #define OMAP3_32K_SOURCE        "omap_32k_fck"
 #define OMAP4_32K_SOURCE        "sys_32k_ck"
@@ -487,7 +488,7 @@ static void __init realtime_counter_init(void)
                 pr_err("%s: ioremap failed\n", __func__);
                 return;
         }
-        sys_clk = clk_get(NULL, "sys_clkin_ck");
+        sys_clk = clk_get(NULL, OMAP5_MPU_SOURCE);
         if (IS_ERR(sys_clk)) {
                 pr_err("%s: failed to get system clock handle\n", __func__);
                 iounmap(base);
@@ -620,7 +621,7 @@ void __init omap4_local_timer_init(void)
 
 #ifdef CONFIG_SOC_OMAP5
 OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
-                        2, OMAP4_MPU_SOURCE);
+                        2, OMAP5_MPU_SOURCE);
 void __init omap5_realtime_timer_init(void)
 {
         int err;