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authorR Sricharan <r.sricharan@ti.com>2013-10-10 03:43:48 -0400
committerTony Lindgren <tony@atomide.com>2013-10-10 13:14:22 -0400
commit5523e4092ee4f2ef58d00c78365c8bddf730c900 (patch)
treeddca2e68a02c282bdf8034e08fcd7286f054b39b /arch/arm/mach-omap2/timer.c
parentaa2f4b16f8305f0bddb5731a222b0ce39e6844aa (diff)
ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register
The realtime counter called master counter, produces the count used by the private timer peripherals in the MPU_CLUSTER. The CNTFRQ per cpu register is used to denote the frequency of the counter. Currently the frequency value is passed from the DT file, but this is not scalable when we have other non-DT guest OS. This register must be set to the right value by the secure rom code. Setting this register helps in propagating the right frequency value across OSes. More discussions and the reason for adding this in a non-DT way can be seen from below. http://www.mail-archive.com/linux-omap@vger.kernel.org/msg93832.html So configuring this secure register for all the cpus here. Cc: Nishanth Menon <nm@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/timer.c')
-rw-r--r--arch/arm/mach-omap2/timer.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index d0f80c020423..87259dc82aa2 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -55,6 +55,7 @@
55#include "soc.h" 55#include "soc.h"
56#include "common.h" 56#include "common.h"
57#include "powerdomain.h" 57#include "powerdomain.h"
58#include "omap-secure.h"
58 59
59#define REALTIME_COUNTER_BASE 0x48243200 60#define REALTIME_COUNTER_BASE 0x48243200
60#define INCREMENTER_NUMERATOR_OFFSET 0x10 61#define INCREMENTER_NUMERATOR_OFFSET 0x10
@@ -65,6 +66,12 @@
65 66
66static struct omap_dm_timer clkev; 67static struct omap_dm_timer clkev;
67static struct clock_event_device clockevent_gpt; 68static struct clock_event_device clockevent_gpt;
69static unsigned long arch_timer_freq;
70
71void set_cntfreq(void)
72{
73 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
74}
68 75
69static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) 76static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
70{ 77{
@@ -546,6 +553,9 @@ static void __init realtime_counter_init(void)
546 reg |= den; 553 reg |= den;
547 __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); 554 __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
548 555
556 arch_timer_freq = (rate / den) * num;
557 set_cntfreq();
558
549 iounmap(base); 559 iounmap(base);
550} 560}
551#else 561#else