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authorKevin Hilman <khilman@deeprootsystems.com>2009-05-28 13:56:16 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-05-28 13:58:50 -0400
commit8bd229492209c0c7d050e2f9a600c12f035d72f7 (patch)
treec76039df215b1c3ba58adb23845baa4af40f25fe /arch/arm/mach-omap2/pm34xx.c
parenta330bd4750bc84aebb28faddd525d0bcbdde262d (diff)
OMAP2/3: PM: push core PM code from linux-omap
This patch is to sync the core linux-omap PM code with mainline. This code has evolved and been used for a while the linux-omap tree, but the attempt here is to finally get this into mainline. Following this will be a series of patches from the 'PM branch' of the linux-omap tree to add full PM hardware support from the linux-omap tree. Much of this PM core code was written by Jouni Hogander with significant contributions from Paul Walmsley as well as many others from Nokia, Texas Instruments and linux-omap community. Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-omap2/pm34xx.c')
-rw-r--r--arch/arm/mach-omap2/pm34xx.c606
1 files changed, 606 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
new file mode 100644
index 000000000000..4474947ddd64
--- /dev/null
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -0,0 +1,606 @@
1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
8 * Copyright (C) 2005 Texas Instruments, Inc.
9 * Richard Woodruff <r-woodruff2@ti.com>
10 *
11 * Based on pm.c for omap1
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/pm.h>
19#include <linux/suspend.h>
20#include <linux/interrupt.h>
21#include <linux/module.h>
22#include <linux/list.h>
23#include <linux/err.h>
24#include <linux/gpio.h>
25
26#include <mach/sram.h>
27#include <mach/clockdomain.h>
28#include <mach/powerdomain.h>
29#include <mach/control.h>
30
31#include "cm.h"
32#include "cm-regbits-34xx.h"
33#include "prm-regbits-34xx.h"
34
35#include "prm.h"
36#include "pm.h"
37
38struct power_state {
39 struct powerdomain *pwrdm;
40 u32 next_state;
41 u32 saved_state;
42 struct list_head node;
43};
44
45static LIST_HEAD(pwrst_list);
46
47static void (*_omap_sram_idle)(u32 *addr, int save_state);
48
49static struct powerdomain *mpu_pwrdm;
50
51/* PRCM Interrupt Handler for wakeups */
52static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
53{
54 u32 wkst, irqstatus_mpu;
55 u32 fclk, iclk;
56
57 /* WKUP */
58 wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
59 if (wkst) {
60 iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
61 fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
62 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
63 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
64 prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
65 while (prm_read_mod_reg(WKUP_MOD, PM_WKST))
66 cpu_relax();
67 cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
68 cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
69 }
70
71 /* CORE */
72 wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
73 if (wkst) {
74 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
75 fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
76 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
77 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
78 prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
79 while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
80 cpu_relax();
81 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
82 cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
83 }
84 wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
85 if (wkst) {
86 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
87 fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
88 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
89 cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
90 prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
91 while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
92 cpu_relax();
93 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
94 cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
95 }
96
97 /* PER */
98 wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
99 if (wkst) {
100 iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
101 fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
102 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
103 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
104 prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
105 while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST))
106 cpu_relax();
107 cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
108 cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
109 }
110
111 if (omap_rev() > OMAP3430_REV_ES1_0) {
112 /* USBHOST */
113 wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
114 if (wkst) {
115 iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
116 CM_ICLKEN);
117 fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
118 CM_FCLKEN);
119 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
120 CM_ICLKEN);
121 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
122 CM_FCLKEN);
123 prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
124 PM_WKST);
125 while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
126 PM_WKST))
127 cpu_relax();
128 cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
129 CM_ICLKEN);
130 cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
131 CM_FCLKEN);
132 }
133 }
134
135 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
136 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
137 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
138 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
139
140 while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET))
141 cpu_relax();
142
143 return IRQ_HANDLED;
144}
145
146static void omap_sram_idle(void)
147{
148 /* Variable to tell what needs to be saved and restored
149 * in omap_sram_idle*/
150 /* save_state = 0 => Nothing to save and restored */
151 /* save_state = 1 => Only L1 and logic lost */
152 /* save_state = 2 => Only L2 lost */
153 /* save_state = 3 => L1, L2 and logic lost */
154 int save_state = 0, mpu_next_state;
155
156 if (!_omap_sram_idle)
157 return;
158
159 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
160 switch (mpu_next_state) {
161 case PWRDM_POWER_RET:
162 /* No need to save context */
163 save_state = 0;
164 break;
165 default:
166 /* Invalid state */
167 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
168 return;
169 }
170 omap2_gpio_prepare_for_retention();
171
172 _omap_sram_idle(NULL, save_state);
173 cpu_init();
174
175 omap2_gpio_resume_after_retention();
176}
177
178/*
179 * Check if functional clocks are enabled before entering
180 * sleep. This function could be behind CONFIG_PM_DEBUG
181 * when all drivers are configuring their sysconfig registers
182 * properly and using their clocks properly.
183 */
184static int omap3_fclks_active(void)
185{
186 u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
187 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
188
189 fck_core1 = cm_read_mod_reg(CORE_MOD,
190 CM_FCLKEN1);
191 if (omap_rev() > OMAP3430_REV_ES1_0) {
192 fck_core3 = cm_read_mod_reg(CORE_MOD,
193 OMAP3430ES2_CM_FCLKEN3);
194 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
195 CM_FCLKEN);
196 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
197 CM_FCLKEN);
198 } else
199 fck_sgx = cm_read_mod_reg(GFX_MOD,
200 OMAP3430ES2_CM_FCLKEN3);
201 fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
202 CM_FCLKEN);
203 fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
204 CM_FCLKEN);
205 fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
206 CM_FCLKEN);
207 if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
208 fck_cam | fck_per | fck_usbhost)
209 return 1;
210 return 0;
211}
212
213static int omap3_can_sleep(void)
214{
215 if (omap3_fclks_active())
216 return 0;
217 return 1;
218}
219
220/* This sets pwrdm state (other than mpu & core. Currently only ON &
221 * RET are supported. Function is assuming that clkdm doesn't have
222 * hw_sup mode enabled. */
223static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
224{
225 u32 cur_state;
226 int sleep_switch = 0;
227 int ret = 0;
228
229 if (pwrdm == NULL || IS_ERR(pwrdm))
230 return -EINVAL;
231
232 while (!(pwrdm->pwrsts & (1 << state))) {
233 if (state == PWRDM_POWER_OFF)
234 return ret;
235 state--;
236 }
237
238 cur_state = pwrdm_read_next_pwrst(pwrdm);
239 if (cur_state == state)
240 return ret;
241
242 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
243 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
244 sleep_switch = 1;
245 pwrdm_wait_transition(pwrdm);
246 }
247
248 ret = pwrdm_set_next_pwrst(pwrdm, state);
249 if (ret) {
250 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
251 pwrdm->name);
252 goto err;
253 }
254
255 if (sleep_switch) {
256 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
257 pwrdm_wait_transition(pwrdm);
258 }
259
260err:
261 return ret;
262}
263
264static void omap3_pm_idle(void)
265{
266 local_irq_disable();
267 local_fiq_disable();
268
269 if (!omap3_can_sleep())
270 goto out;
271
272 if (omap_irq_pending())
273 goto out;
274
275 omap_sram_idle();
276
277out:
278 local_fiq_enable();
279 local_irq_enable();
280}
281
282static int omap3_pm_prepare(void)
283{
284 disable_hlt();
285 return 0;
286}
287
288static int omap3_pm_suspend(void)
289{
290 struct power_state *pwrst;
291 int state, ret = 0;
292
293 /* Read current next_pwrsts */
294 list_for_each_entry(pwrst, &pwrst_list, node)
295 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
296 /* Set ones wanted by suspend */
297 list_for_each_entry(pwrst, &pwrst_list, node) {
298 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
299 goto restore;
300 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
301 goto restore;
302 }
303
304 omap_sram_idle();
305
306restore:
307 /* Restore next_pwrsts */
308 list_for_each_entry(pwrst, &pwrst_list, node) {
309 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
310 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
311 if (state > pwrst->next_state) {
312 printk(KERN_INFO "Powerdomain (%s) didn't enter "
313 "target state %d\n",
314 pwrst->pwrdm->name, pwrst->next_state);
315 ret = -1;
316 }
317 }
318 if (ret)
319 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
320 else
321 printk(KERN_INFO "Successfully put all powerdomains "
322 "to target state\n");
323
324 return ret;
325}
326
327static int omap3_pm_enter(suspend_state_t state)
328{
329 int ret = 0;
330
331 switch (state) {
332 case PM_SUSPEND_STANDBY:
333 case PM_SUSPEND_MEM:
334 ret = omap3_pm_suspend();
335 break;
336 default:
337 ret = -EINVAL;
338 }
339
340 return ret;
341}
342
343static void omap3_pm_finish(void)
344{
345 enable_hlt();
346}
347
348static struct platform_suspend_ops omap_pm_ops = {
349 .prepare = omap3_pm_prepare,
350 .enter = omap3_pm_enter,
351 .finish = omap3_pm_finish,
352 .valid = suspend_valid_only_mem,
353};
354
355static void __init prcm_setup_regs(void)
356{
357 /* reset modem */
358 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
359 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
360 CORE_MOD, RM_RSTCTRL);
361 prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
362
363 /* XXX Reset all wkdeps. This should be done when initializing
364 * powerdomains */
365 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
366 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
367 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
368 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
369 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
370 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
371 if (omap_rev() > OMAP3430_REV_ES1_0) {
372 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
373 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
374 } else
375 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
376
377 /*
378 * Enable interface clock autoidle for all modules.
379 * Note that in the long run this should be done by clockfw
380 */
381 cm_write_mod_reg(
382 OMAP3430ES2_AUTO_MMC3 |
383 OMAP3430ES2_AUTO_ICR |
384 OMAP3430_AUTO_AES2 |
385 OMAP3430_AUTO_SHA12 |
386 OMAP3430_AUTO_DES2 |
387 OMAP3430_AUTO_MMC2 |
388 OMAP3430_AUTO_MMC1 |
389 OMAP3430_AUTO_MSPRO |
390 OMAP3430_AUTO_HDQ |
391 OMAP3430_AUTO_MCSPI4 |
392 OMAP3430_AUTO_MCSPI3 |
393 OMAP3430_AUTO_MCSPI2 |
394 OMAP3430_AUTO_MCSPI1 |
395 OMAP3430_AUTO_I2C3 |
396 OMAP3430_AUTO_I2C2 |
397 OMAP3430_AUTO_I2C1 |
398 OMAP3430_AUTO_UART2 |
399 OMAP3430_AUTO_UART1 |
400 OMAP3430_AUTO_GPT11 |
401 OMAP3430_AUTO_GPT10 |
402 OMAP3430_AUTO_MCBSP5 |
403 OMAP3430_AUTO_MCBSP1 |
404 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
405 OMAP3430_AUTO_MAILBOXES |
406 OMAP3430_AUTO_OMAPCTRL |
407 OMAP3430ES1_AUTO_FSHOSTUSB |
408 OMAP3430_AUTO_HSOTGUSB |
409 OMAP3430ES1_AUTO_D2D | /* This is es1 only */
410 OMAP3430_AUTO_SSI,
411 CORE_MOD, CM_AUTOIDLE1);
412
413 cm_write_mod_reg(
414 OMAP3430_AUTO_PKA |
415 OMAP3430_AUTO_AES1 |
416 OMAP3430_AUTO_RNG |
417 OMAP3430_AUTO_SHA11 |
418 OMAP3430_AUTO_DES1,
419 CORE_MOD, CM_AUTOIDLE2);
420
421 if (omap_rev() > OMAP3430_REV_ES1_0) {
422 cm_write_mod_reg(
423 OMAP3430ES2_AUTO_USBTLL,
424 CORE_MOD, CM_AUTOIDLE3);
425 }
426
427 cm_write_mod_reg(
428 OMAP3430_AUTO_WDT2 |
429 OMAP3430_AUTO_WDT1 |
430 OMAP3430_AUTO_GPIO1 |
431 OMAP3430_AUTO_32KSYNC |
432 OMAP3430_AUTO_GPT12 |
433 OMAP3430_AUTO_GPT1 ,
434 WKUP_MOD, CM_AUTOIDLE);
435
436 cm_write_mod_reg(
437 OMAP3430_AUTO_DSS,
438 OMAP3430_DSS_MOD,
439 CM_AUTOIDLE);
440
441 cm_write_mod_reg(
442 OMAP3430_AUTO_CAM,
443 OMAP3430_CAM_MOD,
444 CM_AUTOIDLE);
445
446 cm_write_mod_reg(
447 OMAP3430_AUTO_GPIO6 |
448 OMAP3430_AUTO_GPIO5 |
449 OMAP3430_AUTO_GPIO4 |
450 OMAP3430_AUTO_GPIO3 |
451 OMAP3430_AUTO_GPIO2 |
452 OMAP3430_AUTO_WDT3 |
453 OMAP3430_AUTO_UART3 |
454 OMAP3430_AUTO_GPT9 |
455 OMAP3430_AUTO_GPT8 |
456 OMAP3430_AUTO_GPT7 |
457 OMAP3430_AUTO_GPT6 |
458 OMAP3430_AUTO_GPT5 |
459 OMAP3430_AUTO_GPT4 |
460 OMAP3430_AUTO_GPT3 |
461 OMAP3430_AUTO_GPT2 |
462 OMAP3430_AUTO_MCBSP4 |
463 OMAP3430_AUTO_MCBSP3 |
464 OMAP3430_AUTO_MCBSP2,
465 OMAP3430_PER_MOD,
466 CM_AUTOIDLE);
467
468 if (omap_rev() > OMAP3430_REV_ES1_0) {
469 cm_write_mod_reg(
470 OMAP3430ES2_AUTO_USBHOST,
471 OMAP3430ES2_USBHOST_MOD,
472 CM_AUTOIDLE);
473 }
474
475 /*
476 * Set all plls to autoidle. This is needed until autoidle is
477 * enabled by clockfw
478 */
479 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
480 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
481 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
482 MPU_MOD,
483 CM_AUTOIDLE2);
484 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
485 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
486 PLL_MOD,
487 CM_AUTOIDLE);
488 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
489 PLL_MOD,
490 CM_AUTOIDLE2);
491
492 /*
493 * Enable control of expternal oscillator through
494 * sys_clkreq. In the long run clock framework should
495 * take care of this.
496 */
497 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
498 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
499 OMAP3430_GR_MOD,
500 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
501
502 /* setup wakup source */
503 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
504 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
505 WKUP_MOD, PM_WKEN);
506 /* No need to write EN_IO, that is always enabled */
507 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
508 OMAP3430_EN_GPT12,
509 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
510 /* For some reason IO doesn't generate wakeup event even if
511 * it is selected to mpu wakeup goup */
512 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
513 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
514}
515
516static int __init pwrdms_setup(struct powerdomain *pwrdm)
517{
518 struct power_state *pwrst;
519
520 if (!pwrdm->pwrsts)
521 return 0;
522
523 pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
524 if (!pwrst)
525 return -ENOMEM;
526 pwrst->pwrdm = pwrdm;
527 pwrst->next_state = PWRDM_POWER_RET;
528 list_add(&pwrst->node, &pwrst_list);
529
530 if (pwrdm_has_hdwr_sar(pwrdm))
531 pwrdm_enable_hdwr_sar(pwrdm);
532
533 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
534}
535
536/*
537 * Enable hw supervised mode for all clockdomains if it's
538 * supported. Initiate sleep transition for other clockdomains, if
539 * they are not used
540 */
541static int __init clkdms_setup(struct clockdomain *clkdm)
542{
543 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
544 omap2_clkdm_allow_idle(clkdm);
545 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
546 atomic_read(&clkdm->usecount) == 0)
547 omap2_clkdm_sleep(clkdm);
548 return 0;
549}
550
551int __init omap3_pm_init(void)
552{
553 struct power_state *pwrst, *tmp;
554 int ret;
555
556 if (!cpu_is_omap34xx())
557 return -ENODEV;
558
559 printk(KERN_ERR "Power Management for TI OMAP3.\n");
560
561 /* XXX prcm_setup_regs needs to be before enabling hw
562 * supervised mode for powerdomains */
563 prcm_setup_regs();
564
565 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
566 (irq_handler_t)prcm_interrupt_handler,
567 IRQF_DISABLED, "prcm", NULL);
568 if (ret) {
569 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
570 INT_34XX_PRCM_MPU_IRQ);
571 goto err1;
572 }
573
574 ret = pwrdm_for_each(pwrdms_setup);
575 if (ret) {
576 printk(KERN_ERR "Failed to setup powerdomains\n");
577 goto err2;
578 }
579
580 (void) clkdm_for_each(clkdms_setup);
581
582 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
583 if (mpu_pwrdm == NULL) {
584 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
585 goto err2;
586 }
587
588 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
589 omap34xx_cpu_suspend_sz);
590
591 suspend_set_ops(&omap_pm_ops);
592
593 pm_idle = omap3_pm_idle;
594
595err1:
596 return ret;
597err2:
598 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
599 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
600 list_del(&pwrst->node);
601 kfree(pwrst);
602 }
603 return ret;
604}
605
606late_initcall(omap3_pm_init);