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authorKevin Hilman <khilman@deeprootsystems.com>2009-05-28 13:56:16 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-05-28 13:58:50 -0400
commit8bd229492209c0c7d050e2f9a600c12f035d72f7 (patch)
treec76039df215b1c3ba58adb23845baa4af40f25fe /arch/arm/mach-omap2/pm24xx.c
parenta330bd4750bc84aebb28faddd525d0bcbdde262d (diff)
OMAP2/3: PM: push core PM code from linux-omap
This patch is to sync the core linux-omap PM code with mainline. This code has evolved and been used for a while the linux-omap tree, but the attempt here is to finally get this into mainline. Following this will be a series of patches from the 'PM branch' of the linux-omap tree to add full PM hardware support from the linux-omap tree. Much of this PM core code was written by Jouni Hogander with significant contributions from Paul Walmsley as well as many others from Nokia, Texas Instruments and linux-omap community. Signed-off-by: Jouni Hogander <jouni.hogander@nokia.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm/mach-omap2/pm24xx.c')
-rw-r--r--arch/arm/mach-omap2/pm24xx.c548
1 files changed, 548 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
new file mode 100644
index 000000000000..232b9f6032e8
--- /dev/null
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -0,0 +1,548 @@
1/*
2 * OMAP2 Power Management Routines
3 *
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 * Copyright (C) 2006-2008 Nokia Corporation
6 *
7 * Written by:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Tony Lindgren
10 * Juha Yrjola
11 * Amit Kucheria <amit.kucheria@nokia.com>
12 * Igor Stoppa <igor.stoppa@nokia.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/suspend.h>
22#include <linux/sched.h>
23#include <linux/proc_fs.h>
24#include <linux/interrupt.h>
25#include <linux/sysfs.h>
26#include <linux/module.h>
27#include <linux/delay.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/irq.h>
31#include <linux/time.h>
32#include <linux/gpio.h>
33
34#include <asm/mach/time.h>
35#include <asm/mach/irq.h>
36#include <asm/mach-types.h>
37
38#include <mach/irqs.h>
39#include <mach/clock.h>
40#include <mach/sram.h>
41#include <mach/control.h>
42#include <mach/mux.h>
43#include <mach/dma.h>
44#include <mach/board.h>
45
46#include "prm.h"
47#include "prm-regbits-24xx.h"
48#include "cm.h"
49#include "cm-regbits-24xx.h"
50#include "sdrc.h"
51#include "pm.h"
52
53#include <mach/powerdomain.h>
54#include <mach/clockdomain.h>
55
56static void (*omap2_sram_idle)(void);
57static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
58 void __iomem *sdrc_power);
59
60static struct powerdomain *mpu_pwrdm;
61static struct powerdomain *core_pwrdm;
62
63static struct clockdomain *dsp_clkdm;
64static struct clockdomain *gfx_clkdm;
65
66static struct clk *osc_ck, *emul_ck;
67
68static int omap2_fclks_active(void)
69{
70 u32 f1, f2;
71
72 f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
73 f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
74 if (f1 | f2)
75 return 1;
76 return 0;
77}
78
79static int omap2_irq_pending(void)
80{
81 u32 pending_reg = 0x480fe098;
82 int i;
83
84 for (i = 0; i < 4; i++) {
85 if (omap_readl(pending_reg))
86 return 1;
87 pending_reg += 0x20;
88 }
89 return 0;
90}
91
92static void omap2_enter_full_retention(void)
93{
94 u32 l;
95 struct timespec ts_preidle, ts_postidle, ts_idle;
96
97 /* There is 1 reference hold for all children of the oscillator
98 * clock, the following will remove it. If no one else uses the
99 * oscillator itself it will be disabled if/when we enter retention
100 * mode.
101 */
102 clk_disable(osc_ck);
103
104 /* Clear old wake-up events */
105 /* REVISIT: These write to reserved bits? */
106 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
107 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
108 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
109
110 /*
111 * Set MPU powerdomain's next power state to RETENTION;
112 * preserve logic state during retention
113 */
114 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
115 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
116
117 /* Workaround to kill USB */
118 l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
119 omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
120
121 omap2_gpio_prepare_for_retention();
122
123 if (omap2_pm_debug) {
124 omap2_pm_dump(0, 0, 0);
125 getnstimeofday(&ts_preidle);
126 }
127
128 /* One last check for pending IRQs to avoid extra latency due
129 * to sleeping unnecessarily. */
130 if (omap2_irq_pending())
131 goto no_sleep;
132
133 /* Jump to SRAM suspend code */
134 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
135 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
136 OMAP_SDRC_REGADDR(SDRC_POWER));
137no_sleep:
138
139 if (omap2_pm_debug) {
140 unsigned long long tmp;
141
142 getnstimeofday(&ts_postidle);
143 ts_idle = timespec_sub(ts_postidle, ts_preidle);
144 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
145 omap2_pm_dump(0, 1, tmp);
146 }
147 omap2_gpio_resume_after_retention();
148
149 clk_enable(osc_ck);
150
151 /* clear CORE wake-up events */
152 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
153 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
154
155 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
156 prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
157
158 /* MPU domain wake events */
159 l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
160 if (l & 0x01)
161 prm_write_mod_reg(0x01, OCP_MOD,
162 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
163 if (l & 0x20)
164 prm_write_mod_reg(0x20, OCP_MOD,
165 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
166
167 /* Mask future PRCM-to-MPU interrupts */
168 prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
169}
170
171static int omap2_i2c_active(void)
172{
173 u32 l;
174
175 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
176 return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
177}
178
179static int sti_console_enabled;
180
181static int omap2_allow_mpu_retention(void)
182{
183 u32 l;
184
185 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
186 l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
187 if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
188 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
189 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
190 return 0;
191 /* Check for UART3. */
192 l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
193 if (l & OMAP24XX_EN_UART3)
194 return 0;
195 if (sti_console_enabled)
196 return 0;
197
198 return 1;
199}
200
201static void omap2_enter_mpu_retention(void)
202{
203 int only_idle = 0;
204 struct timespec ts_preidle, ts_postidle, ts_idle;
205
206 /* Putting MPU into the WFI state while a transfer is active
207 * seems to cause the I2C block to timeout. Why? Good question. */
208 if (omap2_i2c_active())
209 return;
210
211 /* The peripherals seem not to be able to wake up the MPU when
212 * it is in retention mode. */
213 if (omap2_allow_mpu_retention()) {
214 /* REVISIT: These write to reserved bits? */
215 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
216 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
217 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
218
219 /* Try to enter MPU retention */
220 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
221 OMAP_LOGICRETSTATE,
222 MPU_MOD, PM_PWSTCTRL);
223 } else {
224 /* Block MPU retention */
225
226 prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
227 only_idle = 1;
228 }
229
230 if (omap2_pm_debug) {
231 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
232 getnstimeofday(&ts_preidle);
233 }
234
235 omap2_sram_idle();
236
237 if (omap2_pm_debug) {
238 unsigned long long tmp;
239
240 getnstimeofday(&ts_postidle);
241 ts_idle = timespec_sub(ts_postidle, ts_preidle);
242 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
243 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
244 }
245}
246
247static int omap2_can_sleep(void)
248{
249 if (omap2_fclks_active())
250 return 0;
251 if (osc_ck->usecount > 1)
252 return 0;
253 if (omap_dma_running())
254 return 0;
255
256 return 1;
257}
258
259static void omap2_pm_idle(void)
260{
261 local_irq_disable();
262 local_fiq_disable();
263
264 if (!omap2_can_sleep()) {
265 if (omap2_irq_pending())
266 goto out;
267 omap2_enter_mpu_retention();
268 goto out;
269 }
270
271 if (omap2_irq_pending())
272 goto out;
273
274 omap2_enter_full_retention();
275
276out:
277 local_fiq_enable();
278 local_irq_enable();
279}
280
281static int omap2_pm_prepare(void)
282{
283 /* We cannot sleep in idle until we have resumed */
284 disable_hlt();
285 return 0;
286}
287
288static int omap2_pm_suspend(void)
289{
290 u32 wken_wkup, mir1;
291
292 wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
293 prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
294
295 /* Mask GPT1 */
296 mir1 = omap_readl(0x480fe0a4);
297 omap_writel(1 << 5, 0x480fe0ac);
298
299 omap2_enter_full_retention();
300
301 omap_writel(mir1, 0x480fe0a4);
302 prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
303
304 return 0;
305}
306
307static int omap2_pm_enter(suspend_state_t state)
308{
309 int ret = 0;
310
311 switch (state) {
312 case PM_SUSPEND_STANDBY:
313 case PM_SUSPEND_MEM:
314 ret = omap2_pm_suspend();
315 break;
316 default:
317 ret = -EINVAL;
318 }
319
320 return ret;
321}
322
323static void omap2_pm_finish(void)
324{
325 enable_hlt();
326}
327
328static struct platform_suspend_ops omap_pm_ops = {
329 .prepare = omap2_pm_prepare,
330 .enter = omap2_pm_enter,
331 .finish = omap2_pm_finish,
332 .valid = suspend_valid_only_mem,
333};
334
335static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm)
336{
337 omap2_clkdm_allow_idle(clkdm);
338 return 0;
339}
340
341static void __init prcm_setup_regs(void)
342{
343 int i, num_mem_banks;
344 struct powerdomain *pwrdm;
345
346 /* Enable autoidle */
347 prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
348 OMAP2_PRCM_SYSCONFIG_OFFSET);
349
350 /* Set all domain wakeup dependencies */
351 prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
352 prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
353 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
354 prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
355 if (cpu_is_omap2430())
356 prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
357
358 /*
359 * Set CORE powerdomain memory banks to retain their contents
360 * during RETENTION
361 */
362 num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
363 for (i = 0; i < num_mem_banks; i++)
364 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
365
366 /* Set CORE powerdomain's next power state to RETENTION */
367 pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
368
369 /*
370 * Set MPU powerdomain's next power state to RETENTION;
371 * preserve logic state during retention
372 */
373 pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
374 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
375
376 /* Force-power down DSP, GFX powerdomains */
377
378 pwrdm = clkdm_get_pwrdm(dsp_clkdm);
379 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
380 omap2_clkdm_sleep(dsp_clkdm);
381
382 pwrdm = clkdm_get_pwrdm(gfx_clkdm);
383 pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
384 omap2_clkdm_sleep(gfx_clkdm);
385
386 /* Enable clockdomain hardware-supervised control for all clkdms */
387 clkdm_for_each(_pm_clkdm_enable_hwsup);
388
389 /* Enable clock autoidle for all domains */
390 cm_write_mod_reg(OMAP24XX_AUTO_CAM |
391 OMAP24XX_AUTO_MAILBOXES |
392 OMAP24XX_AUTO_WDT4 |
393 OMAP2420_AUTO_WDT3 |
394 OMAP24XX_AUTO_MSPRO |
395 OMAP2420_AUTO_MMC |
396 OMAP24XX_AUTO_FAC |
397 OMAP2420_AUTO_EAC |
398 OMAP24XX_AUTO_HDQ |
399 OMAP24XX_AUTO_UART2 |
400 OMAP24XX_AUTO_UART1 |
401 OMAP24XX_AUTO_I2C2 |
402 OMAP24XX_AUTO_I2C1 |
403 OMAP24XX_AUTO_MCSPI2 |
404 OMAP24XX_AUTO_MCSPI1 |
405 OMAP24XX_AUTO_MCBSP2 |
406 OMAP24XX_AUTO_MCBSP1 |
407 OMAP24XX_AUTO_GPT12 |
408 OMAP24XX_AUTO_GPT11 |
409 OMAP24XX_AUTO_GPT10 |
410 OMAP24XX_AUTO_GPT9 |
411 OMAP24XX_AUTO_GPT8 |
412 OMAP24XX_AUTO_GPT7 |
413 OMAP24XX_AUTO_GPT6 |
414 OMAP24XX_AUTO_GPT5 |
415 OMAP24XX_AUTO_GPT4 |
416 OMAP24XX_AUTO_GPT3 |
417 OMAP24XX_AUTO_GPT2 |
418 OMAP2420_AUTO_VLYNQ |
419 OMAP24XX_AUTO_DSS,
420 CORE_MOD, CM_AUTOIDLE1);
421 cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
422 OMAP24XX_AUTO_SSI |
423 OMAP24XX_AUTO_USB,
424 CORE_MOD, CM_AUTOIDLE2);
425 cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
426 OMAP24XX_AUTO_GPMC |
427 OMAP24XX_AUTO_SDMA,
428 CORE_MOD, CM_AUTOIDLE3);
429 cm_write_mod_reg(OMAP24XX_AUTO_PKA |
430 OMAP24XX_AUTO_AES |
431 OMAP24XX_AUTO_RNG |
432 OMAP24XX_AUTO_SHA |
433 OMAP24XX_AUTO_DES,
434 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
435
436 cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
437
438 /* Put DPLL and both APLLs into autoidle mode */
439 cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
440 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
441 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
442 PLL_MOD, CM_AUTOIDLE);
443
444 cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
445 OMAP24XX_AUTO_WDT1 |
446 OMAP24XX_AUTO_MPU_WDT |
447 OMAP24XX_AUTO_GPIOS |
448 OMAP24XX_AUTO_32KSYNC |
449 OMAP24XX_AUTO_GPT1,
450 WKUP_MOD, CM_AUTOIDLE);
451
452 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
453 * stabilisation */
454 prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
455 OMAP2_PRCM_CLKSSETUP_OFFSET);
456
457 /* Configure automatic voltage transition */
458 prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
459 OMAP2_PRCM_VOLTSETUP_OFFSET);
460 prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT |
461 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
462 OMAP24XX_MEMRETCTRL |
463 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
464 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
465 OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
466
467 /* Enable wake-up events */
468 prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
469 WKUP_MOD, PM_WKEN);
470}
471
472int __init omap2_pm_init(void)
473{
474 u32 l;
475
476 if (!cpu_is_omap24xx())
477 return -ENODEV;
478
479 printk(KERN_INFO "Power Management for OMAP2 initializing\n");
480 l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
481 printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
482
483 /* Look up important powerdomains, clockdomains */
484
485 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
486 if (!mpu_pwrdm)
487 pr_err("PM: mpu_pwrdm not found\n");
488
489 core_pwrdm = pwrdm_lookup("core_pwrdm");
490 if (!core_pwrdm)
491 pr_err("PM: core_pwrdm not found\n");
492
493 dsp_clkdm = clkdm_lookup("dsp_clkdm");
494 if (!dsp_clkdm)
495 pr_err("PM: mpu_clkdm not found\n");
496
497 gfx_clkdm = clkdm_lookup("gfx_clkdm");
498 if (!gfx_clkdm)
499 pr_err("PM: gfx_clkdm not found\n");
500
501
502 osc_ck = clk_get(NULL, "osc_ck");
503 if (IS_ERR(osc_ck)) {
504 printk(KERN_ERR "could not get osc_ck\n");
505 return -ENODEV;
506 }
507
508 if (cpu_is_omap242x()) {
509 emul_ck = clk_get(NULL, "emul_ck");
510 if (IS_ERR(emul_ck)) {
511 printk(KERN_ERR "could not get emul_ck\n");
512 clk_put(osc_ck);
513 return -ENODEV;
514 }
515 }
516
517 prcm_setup_regs();
518
519 /* Hack to prevent MPU retention when STI console is enabled. */
520 {
521 const struct omap_sti_console_config *sti;
522
523 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
524 struct omap_sti_console_config);
525 if (sti != NULL && sti->enable)
526 sti_console_enabled = 1;
527 }
528
529 /*
530 * We copy the assembler sleep/wakeup routines to SRAM.
531 * These routines need to be in SRAM as that's the only
532 * memory the MPU can see when it wakes up.
533 */
534 if (cpu_is_omap24xx()) {
535 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
536 omap24xx_idle_loop_suspend_sz);
537
538 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
539 omap24xx_cpu_suspend_sz);
540 }
541
542 suspend_set_ops(&omap_pm_ops);
543 pm_idle = omap2_pm_idle;
544
545 return 0;
546}
547
548late_initcall(omap2_pm_init);