diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-02-21 18:27:22 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-02-21 18:27:22 -0500 |
commit | bab588fcfb6335c767d811a8955979f5440328e0 (patch) | |
tree | 2a862ddf47a82be885a8e7945a17cc3ff7a658b9 /arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |
parent | 3298a3511f1e73255a8dc023efd909e569eea037 (diff) | |
parent | 9cb0d1babfcb1b4ac248c09425f7d5de1e771133 (diff) |
Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC-specific updates from Arnd Bergmann:
"This is a larger set of new functionality for the existing SoC
families, including:
- vt8500 gains support for new CPU cores, notably the Cortex-A9 based
wm8850
- prima2 gains support for the "marco" SoC family, its SMP based
cousin
- tegra gains support for the new Tegra4 (Tegra114) family
- socfpga now supports a newer version of the hardware including SMP
- i.mx31 and bcm2835 are now using DT probing for their clocks
- lots of updates for sh-mobile
- OMAP updates for clocks, power management and USB
- i.mx6q and tegra now support cpuidle
- kirkwood now supports PCIe hot plugging
- tegra clock support is updated
- tegra USB PHY probing gets implemented diffently"
* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits)
ARM: prima2: remove duplicate v7_invalidate_l1
ARM: shmobile: r8a7779: Correct TMU clock support again
ARM: prima2: fix __init section for cpu hotplug
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3)
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3)
arm: socfpga: Add SMP support for actual socfpga harware
arm: Add v7_invalidate_l1 to cache-v7.S
arm: socfpga: Add entries to enable make dtbs socfpga
arm: socfpga: Add new device tree source for actual socfpga HW
ARM: tegra: sort Kconfig selects for Tegra114
ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114
ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC
ARM: tegra: Fix build error for gic update
ARM: tegra: remove empty tegra_smp_init_cpus()
ARM: shmobile: Register ARM architected timer
ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move
ARM: shmobile: r8a7779: Correct TMU clock support
ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT
ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles
ARM: mxs: use apbx bus clock to drive the timers on timrotv2
...
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_44xx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 99 |
1 files changed, 49 insertions, 50 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 624a7e84a685..7ec1083ff604 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
@@ -616,7 +616,7 @@ static struct omap_hwmod omap44xx_dmic_hwmod = { | |||
616 | .clkdm_name = "abe_clkdm", | 616 | .clkdm_name = "abe_clkdm", |
617 | .mpu_irqs = omap44xx_dmic_irqs, | 617 | .mpu_irqs = omap44xx_dmic_irqs, |
618 | .sdma_reqs = omap44xx_dmic_sdma_reqs, | 618 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
619 | .main_clk = "dmic_fck", | 619 | .main_clk = "func_dmic_abe_gfclk", |
620 | .prcm = { | 620 | .prcm = { |
621 | .omap4 = { | 621 | .omap4 = { |
622 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, | 622 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
@@ -1161,7 +1161,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = { | |||
1161 | .class = &omap44xx_gpio_hwmod_class, | 1161 | .class = &omap44xx_gpio_hwmod_class, |
1162 | .clkdm_name = "l4_wkup_clkdm", | 1162 | .clkdm_name = "l4_wkup_clkdm", |
1163 | .mpu_irqs = omap44xx_gpio1_irqs, | 1163 | .mpu_irqs = omap44xx_gpio1_irqs, |
1164 | .main_clk = "gpio1_ick", | 1164 | .main_clk = "l4_wkup_clk_mux_ck", |
1165 | .prcm = { | 1165 | .prcm = { |
1166 | .omap4 = { | 1166 | .omap4 = { |
1167 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, | 1167 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
@@ -1190,7 +1190,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = { | |||
1190 | .clkdm_name = "l4_per_clkdm", | 1190 | .clkdm_name = "l4_per_clkdm", |
1191 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1191 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
1192 | .mpu_irqs = omap44xx_gpio2_irqs, | 1192 | .mpu_irqs = omap44xx_gpio2_irqs, |
1193 | .main_clk = "gpio2_ick", | 1193 | .main_clk = "l4_div_ck", |
1194 | .prcm = { | 1194 | .prcm = { |
1195 | .omap4 = { | 1195 | .omap4 = { |
1196 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, | 1196 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
@@ -1219,7 +1219,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = { | |||
1219 | .clkdm_name = "l4_per_clkdm", | 1219 | .clkdm_name = "l4_per_clkdm", |
1220 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1220 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
1221 | .mpu_irqs = omap44xx_gpio3_irqs, | 1221 | .mpu_irqs = omap44xx_gpio3_irqs, |
1222 | .main_clk = "gpio3_ick", | 1222 | .main_clk = "l4_div_ck", |
1223 | .prcm = { | 1223 | .prcm = { |
1224 | .omap4 = { | 1224 | .omap4 = { |
1225 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, | 1225 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
@@ -1248,7 +1248,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = { | |||
1248 | .clkdm_name = "l4_per_clkdm", | 1248 | .clkdm_name = "l4_per_clkdm", |
1249 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1249 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
1250 | .mpu_irqs = omap44xx_gpio4_irqs, | 1250 | .mpu_irqs = omap44xx_gpio4_irqs, |
1251 | .main_clk = "gpio4_ick", | 1251 | .main_clk = "l4_div_ck", |
1252 | .prcm = { | 1252 | .prcm = { |
1253 | .omap4 = { | 1253 | .omap4 = { |
1254 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, | 1254 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
@@ -1277,7 +1277,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = { | |||
1277 | .clkdm_name = "l4_per_clkdm", | 1277 | .clkdm_name = "l4_per_clkdm", |
1278 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1278 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
1279 | .mpu_irqs = omap44xx_gpio5_irqs, | 1279 | .mpu_irqs = omap44xx_gpio5_irqs, |
1280 | .main_clk = "gpio5_ick", | 1280 | .main_clk = "l4_div_ck", |
1281 | .prcm = { | 1281 | .prcm = { |
1282 | .omap4 = { | 1282 | .omap4 = { |
1283 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, | 1283 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
@@ -1306,7 +1306,7 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = { | |||
1306 | .clkdm_name = "l4_per_clkdm", | 1306 | .clkdm_name = "l4_per_clkdm", |
1307 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | 1307 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
1308 | .mpu_irqs = omap44xx_gpio6_irqs, | 1308 | .mpu_irqs = omap44xx_gpio6_irqs, |
1309 | .main_clk = "gpio6_ick", | 1309 | .main_clk = "l4_div_ck", |
1310 | .prcm = { | 1310 | .prcm = { |
1311 | .omap4 = { | 1311 | .omap4 = { |
1312 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, | 1312 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
@@ -1405,7 +1405,7 @@ static struct omap_hwmod omap44xx_gpu_hwmod = { | |||
1405 | .class = &omap44xx_gpu_hwmod_class, | 1405 | .class = &omap44xx_gpu_hwmod_class, |
1406 | .clkdm_name = "l3_gfx_clkdm", | 1406 | .clkdm_name = "l3_gfx_clkdm", |
1407 | .mpu_irqs = omap44xx_gpu_irqs, | 1407 | .mpu_irqs = omap44xx_gpu_irqs, |
1408 | .main_clk = "gpu_fck", | 1408 | .main_clk = "sgx_clk_mux", |
1409 | .prcm = { | 1409 | .prcm = { |
1410 | .omap4 = { | 1410 | .omap4 = { |
1411 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, | 1411 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, |
@@ -1446,7 +1446,7 @@ static struct omap_hwmod omap44xx_hdq1w_hwmod = { | |||
1446 | .clkdm_name = "l4_per_clkdm", | 1446 | .clkdm_name = "l4_per_clkdm", |
1447 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ | 1447 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ |
1448 | .mpu_irqs = omap44xx_hdq1w_irqs, | 1448 | .mpu_irqs = omap44xx_hdq1w_irqs, |
1449 | .main_clk = "hdq1w_fck", | 1449 | .main_clk = "func_12m_fclk", |
1450 | .prcm = { | 1450 | .prcm = { |
1451 | .omap4 = { | 1451 | .omap4 = { |
1452 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, | 1452 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, |
@@ -1550,7 +1550,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = { | |||
1550 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | 1550 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
1551 | .mpu_irqs = omap44xx_i2c1_irqs, | 1551 | .mpu_irqs = omap44xx_i2c1_irqs, |
1552 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, | 1552 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
1553 | .main_clk = "i2c1_fck", | 1553 | .main_clk = "func_96m_fclk", |
1554 | .prcm = { | 1554 | .prcm = { |
1555 | .omap4 = { | 1555 | .omap4 = { |
1556 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, | 1556 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
@@ -1580,7 +1580,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = { | |||
1580 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | 1580 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
1581 | .mpu_irqs = omap44xx_i2c2_irqs, | 1581 | .mpu_irqs = omap44xx_i2c2_irqs, |
1582 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, | 1582 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
1583 | .main_clk = "i2c2_fck", | 1583 | .main_clk = "func_96m_fclk", |
1584 | .prcm = { | 1584 | .prcm = { |
1585 | .omap4 = { | 1585 | .omap4 = { |
1586 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, | 1586 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
@@ -1610,7 +1610,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = { | |||
1610 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | 1610 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
1611 | .mpu_irqs = omap44xx_i2c3_irqs, | 1611 | .mpu_irqs = omap44xx_i2c3_irqs, |
1612 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, | 1612 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
1613 | .main_clk = "i2c3_fck", | 1613 | .main_clk = "func_96m_fclk", |
1614 | .prcm = { | 1614 | .prcm = { |
1615 | .omap4 = { | 1615 | .omap4 = { |
1616 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, | 1616 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
@@ -1640,7 +1640,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = { | |||
1640 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, | 1640 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
1641 | .mpu_irqs = omap44xx_i2c4_irqs, | 1641 | .mpu_irqs = omap44xx_i2c4_irqs, |
1642 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, | 1642 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
1643 | .main_clk = "i2c4_fck", | 1643 | .main_clk = "func_96m_fclk", |
1644 | .prcm = { | 1644 | .prcm = { |
1645 | .omap4 = { | 1645 | .omap4 = { |
1646 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, | 1646 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
@@ -1743,7 +1743,7 @@ static struct omap_hwmod omap44xx_iss_hwmod = { | |||
1743 | .clkdm_name = "iss_clkdm", | 1743 | .clkdm_name = "iss_clkdm", |
1744 | .mpu_irqs = omap44xx_iss_irqs, | 1744 | .mpu_irqs = omap44xx_iss_irqs, |
1745 | .sdma_reqs = omap44xx_iss_sdma_reqs, | 1745 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
1746 | .main_clk = "iss_fck", | 1746 | .main_clk = "ducati_clk_mux_ck", |
1747 | .prcm = { | 1747 | .prcm = { |
1748 | .omap4 = { | 1748 | .omap4 = { |
1749 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, | 1749 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
@@ -1785,7 +1785,7 @@ static struct omap_hwmod omap44xx_iva_hwmod = { | |||
1785 | .mpu_irqs = omap44xx_iva_irqs, | 1785 | .mpu_irqs = omap44xx_iva_irqs, |
1786 | .rst_lines = omap44xx_iva_resets, | 1786 | .rst_lines = omap44xx_iva_resets, |
1787 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), | 1787 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), |
1788 | .main_clk = "iva_fck", | 1788 | .main_clk = "dpll_iva_m5x2_ck", |
1789 | .prcm = { | 1789 | .prcm = { |
1790 | .omap4 = { | 1790 | .omap4 = { |
1791 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, | 1791 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
@@ -1829,7 +1829,7 @@ static struct omap_hwmod omap44xx_kbd_hwmod = { | |||
1829 | .class = &omap44xx_kbd_hwmod_class, | 1829 | .class = &omap44xx_kbd_hwmod_class, |
1830 | .clkdm_name = "l4_wkup_clkdm", | 1830 | .clkdm_name = "l4_wkup_clkdm", |
1831 | .mpu_irqs = omap44xx_kbd_irqs, | 1831 | .mpu_irqs = omap44xx_kbd_irqs, |
1832 | .main_clk = "kbd_fck", | 1832 | .main_clk = "sys_32k_ck", |
1833 | .prcm = { | 1833 | .prcm = { |
1834 | .omap4 = { | 1834 | .omap4 = { |
1835 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, | 1835 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
@@ -1920,7 +1920,7 @@ static struct omap_hwmod omap44xx_mcasp_hwmod = { | |||
1920 | .clkdm_name = "abe_clkdm", | 1920 | .clkdm_name = "abe_clkdm", |
1921 | .mpu_irqs = omap44xx_mcasp_irqs, | 1921 | .mpu_irqs = omap44xx_mcasp_irqs, |
1922 | .sdma_reqs = omap44xx_mcasp_sdma_reqs, | 1922 | .sdma_reqs = omap44xx_mcasp_sdma_reqs, |
1923 | .main_clk = "mcasp_fck", | 1923 | .main_clk = "func_mcasp_abe_gfclk", |
1924 | .prcm = { | 1924 | .prcm = { |
1925 | .omap4 = { | 1925 | .omap4 = { |
1926 | .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, | 1926 | .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET, |
@@ -1972,7 +1972,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = { | |||
1972 | .clkdm_name = "abe_clkdm", | 1972 | .clkdm_name = "abe_clkdm", |
1973 | .mpu_irqs = omap44xx_mcbsp1_irqs, | 1973 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
1974 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, | 1974 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
1975 | .main_clk = "mcbsp1_fck", | 1975 | .main_clk = "func_mcbsp1_gfclk", |
1976 | .prcm = { | 1976 | .prcm = { |
1977 | .omap4 = { | 1977 | .omap4 = { |
1978 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, | 1978 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
@@ -2007,7 +2007,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = { | |||
2007 | .clkdm_name = "abe_clkdm", | 2007 | .clkdm_name = "abe_clkdm", |
2008 | .mpu_irqs = omap44xx_mcbsp2_irqs, | 2008 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
2009 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, | 2009 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
2010 | .main_clk = "mcbsp2_fck", | 2010 | .main_clk = "func_mcbsp2_gfclk", |
2011 | .prcm = { | 2011 | .prcm = { |
2012 | .omap4 = { | 2012 | .omap4 = { |
2013 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, | 2013 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
@@ -2042,7 +2042,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = { | |||
2042 | .clkdm_name = "abe_clkdm", | 2042 | .clkdm_name = "abe_clkdm", |
2043 | .mpu_irqs = omap44xx_mcbsp3_irqs, | 2043 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
2044 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, | 2044 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
2045 | .main_clk = "mcbsp3_fck", | 2045 | .main_clk = "func_mcbsp3_gfclk", |
2046 | .prcm = { | 2046 | .prcm = { |
2047 | .omap4 = { | 2047 | .omap4 = { |
2048 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, | 2048 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
@@ -2077,7 +2077,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = { | |||
2077 | .clkdm_name = "l4_per_clkdm", | 2077 | .clkdm_name = "l4_per_clkdm", |
2078 | .mpu_irqs = omap44xx_mcbsp4_irqs, | 2078 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
2079 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, | 2079 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
2080 | .main_clk = "mcbsp4_fck", | 2080 | .main_clk = "per_mcbsp4_gfclk", |
2081 | .prcm = { | 2081 | .prcm = { |
2082 | .omap4 = { | 2082 | .omap4 = { |
2083 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, | 2083 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
@@ -2140,7 +2140,7 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = { | |||
2140 | .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, | 2140 | .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE, |
2141 | .mpu_irqs = omap44xx_mcpdm_irqs, | 2141 | .mpu_irqs = omap44xx_mcpdm_irqs, |
2142 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, | 2142 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
2143 | .main_clk = "mcpdm_fck", | 2143 | .main_clk = "pad_clks_ck", |
2144 | .prcm = { | 2144 | .prcm = { |
2145 | .omap4 = { | 2145 | .omap4 = { |
2146 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, | 2146 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
@@ -2201,7 +2201,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = { | |||
2201 | .clkdm_name = "l4_per_clkdm", | 2201 | .clkdm_name = "l4_per_clkdm", |
2202 | .mpu_irqs = omap44xx_mcspi1_irqs, | 2202 | .mpu_irqs = omap44xx_mcspi1_irqs, |
2203 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, | 2203 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
2204 | .main_clk = "mcspi1_fck", | 2204 | .main_clk = "func_48m_fclk", |
2205 | .prcm = { | 2205 | .prcm = { |
2206 | .omap4 = { | 2206 | .omap4 = { |
2207 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, | 2207 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
@@ -2237,7 +2237,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = { | |||
2237 | .clkdm_name = "l4_per_clkdm", | 2237 | .clkdm_name = "l4_per_clkdm", |
2238 | .mpu_irqs = omap44xx_mcspi2_irqs, | 2238 | .mpu_irqs = omap44xx_mcspi2_irqs, |
2239 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, | 2239 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
2240 | .main_clk = "mcspi2_fck", | 2240 | .main_clk = "func_48m_fclk", |
2241 | .prcm = { | 2241 | .prcm = { |
2242 | .omap4 = { | 2242 | .omap4 = { |
2243 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, | 2243 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
@@ -2273,7 +2273,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = { | |||
2273 | .clkdm_name = "l4_per_clkdm", | 2273 | .clkdm_name = "l4_per_clkdm", |
2274 | .mpu_irqs = omap44xx_mcspi3_irqs, | 2274 | .mpu_irqs = omap44xx_mcspi3_irqs, |
2275 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, | 2275 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
2276 | .main_clk = "mcspi3_fck", | 2276 | .main_clk = "func_48m_fclk", |
2277 | .prcm = { | 2277 | .prcm = { |
2278 | .omap4 = { | 2278 | .omap4 = { |
2279 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, | 2279 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
@@ -2307,7 +2307,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = { | |||
2307 | .clkdm_name = "l4_per_clkdm", | 2307 | .clkdm_name = "l4_per_clkdm", |
2308 | .mpu_irqs = omap44xx_mcspi4_irqs, | 2308 | .mpu_irqs = omap44xx_mcspi4_irqs, |
2309 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, | 2309 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
2310 | .main_clk = "mcspi4_fck", | 2310 | .main_clk = "func_48m_fclk", |
2311 | .prcm = { | 2311 | .prcm = { |
2312 | .omap4 = { | 2312 | .omap4 = { |
2313 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, | 2313 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
@@ -2363,7 +2363,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = { | |||
2363 | .clkdm_name = "l3_init_clkdm", | 2363 | .clkdm_name = "l3_init_clkdm", |
2364 | .mpu_irqs = omap44xx_mmc1_irqs, | 2364 | .mpu_irqs = omap44xx_mmc1_irqs, |
2365 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, | 2365 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
2366 | .main_clk = "mmc1_fck", | 2366 | .main_clk = "hsmmc1_fclk", |
2367 | .prcm = { | 2367 | .prcm = { |
2368 | .omap4 = { | 2368 | .omap4 = { |
2369 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, | 2369 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
@@ -2392,7 +2392,7 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = { | |||
2392 | .clkdm_name = "l3_init_clkdm", | 2392 | .clkdm_name = "l3_init_clkdm", |
2393 | .mpu_irqs = omap44xx_mmc2_irqs, | 2393 | .mpu_irqs = omap44xx_mmc2_irqs, |
2394 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, | 2394 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
2395 | .main_clk = "mmc2_fck", | 2395 | .main_clk = "hsmmc2_fclk", |
2396 | .prcm = { | 2396 | .prcm = { |
2397 | .omap4 = { | 2397 | .omap4 = { |
2398 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, | 2398 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
@@ -2420,7 +2420,7 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = { | |||
2420 | .clkdm_name = "l4_per_clkdm", | 2420 | .clkdm_name = "l4_per_clkdm", |
2421 | .mpu_irqs = omap44xx_mmc3_irqs, | 2421 | .mpu_irqs = omap44xx_mmc3_irqs, |
2422 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, | 2422 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
2423 | .main_clk = "mmc3_fck", | 2423 | .main_clk = "func_48m_fclk", |
2424 | .prcm = { | 2424 | .prcm = { |
2425 | .omap4 = { | 2425 | .omap4 = { |
2426 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, | 2426 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
@@ -2448,7 +2448,7 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = { | |||
2448 | .clkdm_name = "l4_per_clkdm", | 2448 | .clkdm_name = "l4_per_clkdm", |
2449 | .mpu_irqs = omap44xx_mmc4_irqs, | 2449 | .mpu_irqs = omap44xx_mmc4_irqs, |
2450 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, | 2450 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
2451 | .main_clk = "mmc4_fck", | 2451 | .main_clk = "func_48m_fclk", |
2452 | .prcm = { | 2452 | .prcm = { |
2453 | .omap4 = { | 2453 | .omap4 = { |
2454 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, | 2454 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
@@ -2476,7 +2476,7 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = { | |||
2476 | .clkdm_name = "l4_per_clkdm", | 2476 | .clkdm_name = "l4_per_clkdm", |
2477 | .mpu_irqs = omap44xx_mmc5_irqs, | 2477 | .mpu_irqs = omap44xx_mmc5_irqs, |
2478 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, | 2478 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
2479 | .main_clk = "mmc5_fck", | 2479 | .main_clk = "func_48m_fclk", |
2480 | .prcm = { | 2480 | .prcm = { |
2481 | .omap4 = { | 2481 | .omap4 = { |
2482 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, | 2482 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
@@ -2718,7 +2718,7 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = { | |||
2718 | .name = "ocp2scp_usb_phy", | 2718 | .name = "ocp2scp_usb_phy", |
2719 | .class = &omap44xx_ocp2scp_hwmod_class, | 2719 | .class = &omap44xx_ocp2scp_hwmod_class, |
2720 | .clkdm_name = "l3_init_clkdm", | 2720 | .clkdm_name = "l3_init_clkdm", |
2721 | .main_clk = "ocp2scp_usb_phy_phy_48m", | 2721 | .main_clk = "func_48m_fclk", |
2722 | .prcm = { | 2722 | .prcm = { |
2723 | .omap4 = { | 2723 | .omap4 = { |
2724 | .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, | 2724 | .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET, |
@@ -3155,7 +3155,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = { | |||
3155 | .clkdm_name = "l4_wkup_clkdm", | 3155 | .clkdm_name = "l4_wkup_clkdm", |
3156 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | 3156 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
3157 | .mpu_irqs = omap44xx_timer1_irqs, | 3157 | .mpu_irqs = omap44xx_timer1_irqs, |
3158 | .main_clk = "timer1_fck", | 3158 | .main_clk = "dmt1_clk_mux", |
3159 | .prcm = { | 3159 | .prcm = { |
3160 | .omap4 = { | 3160 | .omap4 = { |
3161 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, | 3161 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
@@ -3178,7 +3178,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = { | |||
3178 | .clkdm_name = "l4_per_clkdm", | 3178 | .clkdm_name = "l4_per_clkdm", |
3179 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | 3179 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
3180 | .mpu_irqs = omap44xx_timer2_irqs, | 3180 | .mpu_irqs = omap44xx_timer2_irqs, |
3181 | .main_clk = "timer2_fck", | 3181 | .main_clk = "cm2_dm2_mux", |
3182 | .prcm = { | 3182 | .prcm = { |
3183 | .omap4 = { | 3183 | .omap4 = { |
3184 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, | 3184 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
@@ -3199,7 +3199,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = { | |||
3199 | .class = &omap44xx_timer_hwmod_class, | 3199 | .class = &omap44xx_timer_hwmod_class, |
3200 | .clkdm_name = "l4_per_clkdm", | 3200 | .clkdm_name = "l4_per_clkdm", |
3201 | .mpu_irqs = omap44xx_timer3_irqs, | 3201 | .mpu_irqs = omap44xx_timer3_irqs, |
3202 | .main_clk = "timer3_fck", | 3202 | .main_clk = "cm2_dm3_mux", |
3203 | .prcm = { | 3203 | .prcm = { |
3204 | .omap4 = { | 3204 | .omap4 = { |
3205 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, | 3205 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
@@ -3220,7 +3220,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = { | |||
3220 | .class = &omap44xx_timer_hwmod_class, | 3220 | .class = &omap44xx_timer_hwmod_class, |
3221 | .clkdm_name = "l4_per_clkdm", | 3221 | .clkdm_name = "l4_per_clkdm", |
3222 | .mpu_irqs = omap44xx_timer4_irqs, | 3222 | .mpu_irqs = omap44xx_timer4_irqs, |
3223 | .main_clk = "timer4_fck", | 3223 | .main_clk = "cm2_dm4_mux", |
3224 | .prcm = { | 3224 | .prcm = { |
3225 | .omap4 = { | 3225 | .omap4 = { |
3226 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, | 3226 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
@@ -3241,7 +3241,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = { | |||
3241 | .class = &omap44xx_timer_hwmod_class, | 3241 | .class = &omap44xx_timer_hwmod_class, |
3242 | .clkdm_name = "abe_clkdm", | 3242 | .clkdm_name = "abe_clkdm", |
3243 | .mpu_irqs = omap44xx_timer5_irqs, | 3243 | .mpu_irqs = omap44xx_timer5_irqs, |
3244 | .main_clk = "timer5_fck", | 3244 | .main_clk = "timer5_sync_mux", |
3245 | .prcm = { | 3245 | .prcm = { |
3246 | .omap4 = { | 3246 | .omap4 = { |
3247 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, | 3247 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
@@ -3263,8 +3263,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = { | |||
3263 | .class = &omap44xx_timer_hwmod_class, | 3263 | .class = &omap44xx_timer_hwmod_class, |
3264 | .clkdm_name = "abe_clkdm", | 3264 | .clkdm_name = "abe_clkdm", |
3265 | .mpu_irqs = omap44xx_timer6_irqs, | 3265 | .mpu_irqs = omap44xx_timer6_irqs, |
3266 | 3266 | .main_clk = "timer6_sync_mux", | |
3267 | .main_clk = "timer6_fck", | ||
3268 | .prcm = { | 3267 | .prcm = { |
3269 | .omap4 = { | 3268 | .omap4 = { |
3270 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, | 3269 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
@@ -3286,7 +3285,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = { | |||
3286 | .class = &omap44xx_timer_hwmod_class, | 3285 | .class = &omap44xx_timer_hwmod_class, |
3287 | .clkdm_name = "abe_clkdm", | 3286 | .clkdm_name = "abe_clkdm", |
3288 | .mpu_irqs = omap44xx_timer7_irqs, | 3287 | .mpu_irqs = omap44xx_timer7_irqs, |
3289 | .main_clk = "timer7_fck", | 3288 | .main_clk = "timer7_sync_mux", |
3290 | .prcm = { | 3289 | .prcm = { |
3291 | .omap4 = { | 3290 | .omap4 = { |
3292 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, | 3291 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
@@ -3308,7 +3307,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = { | |||
3308 | .class = &omap44xx_timer_hwmod_class, | 3307 | .class = &omap44xx_timer_hwmod_class, |
3309 | .clkdm_name = "abe_clkdm", | 3308 | .clkdm_name = "abe_clkdm", |
3310 | .mpu_irqs = omap44xx_timer8_irqs, | 3309 | .mpu_irqs = omap44xx_timer8_irqs, |
3311 | .main_clk = "timer8_fck", | 3310 | .main_clk = "timer8_sync_mux", |
3312 | .prcm = { | 3311 | .prcm = { |
3313 | .omap4 = { | 3312 | .omap4 = { |
3314 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, | 3313 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
@@ -3330,7 +3329,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = { | |||
3330 | .class = &omap44xx_timer_hwmod_class, | 3329 | .class = &omap44xx_timer_hwmod_class, |
3331 | .clkdm_name = "l4_per_clkdm", | 3330 | .clkdm_name = "l4_per_clkdm", |
3332 | .mpu_irqs = omap44xx_timer9_irqs, | 3331 | .mpu_irqs = omap44xx_timer9_irqs, |
3333 | .main_clk = "timer9_fck", | 3332 | .main_clk = "cm2_dm9_mux", |
3334 | .prcm = { | 3333 | .prcm = { |
3335 | .omap4 = { | 3334 | .omap4 = { |
3336 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, | 3335 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
@@ -3353,7 +3352,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = { | |||
3353 | .clkdm_name = "l4_per_clkdm", | 3352 | .clkdm_name = "l4_per_clkdm", |
3354 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, | 3353 | .flags = HWMOD_SET_DEFAULT_CLOCKACT, |
3355 | .mpu_irqs = omap44xx_timer10_irqs, | 3354 | .mpu_irqs = omap44xx_timer10_irqs, |
3356 | .main_clk = "timer10_fck", | 3355 | .main_clk = "cm2_dm10_mux", |
3357 | .prcm = { | 3356 | .prcm = { |
3358 | .omap4 = { | 3357 | .omap4 = { |
3359 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, | 3358 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
@@ -3375,7 +3374,7 @@ static struct omap_hwmod omap44xx_timer11_hwmod = { | |||
3375 | .class = &omap44xx_timer_hwmod_class, | 3374 | .class = &omap44xx_timer_hwmod_class, |
3376 | .clkdm_name = "l4_per_clkdm", | 3375 | .clkdm_name = "l4_per_clkdm", |
3377 | .mpu_irqs = omap44xx_timer11_irqs, | 3376 | .mpu_irqs = omap44xx_timer11_irqs, |
3378 | .main_clk = "timer11_fck", | 3377 | .main_clk = "cm2_dm11_mux", |
3379 | .prcm = { | 3378 | .prcm = { |
3380 | .omap4 = { | 3379 | .omap4 = { |
3381 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, | 3380 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
@@ -3426,7 +3425,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = { | |||
3426 | .clkdm_name = "l4_per_clkdm", | 3425 | .clkdm_name = "l4_per_clkdm", |
3427 | .mpu_irqs = omap44xx_uart1_irqs, | 3426 | .mpu_irqs = omap44xx_uart1_irqs, |
3428 | .sdma_reqs = omap44xx_uart1_sdma_reqs, | 3427 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
3429 | .main_clk = "uart1_fck", | 3428 | .main_clk = "func_48m_fclk", |
3430 | .prcm = { | 3429 | .prcm = { |
3431 | .omap4 = { | 3430 | .omap4 = { |
3432 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, | 3431 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
@@ -3454,7 +3453,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = { | |||
3454 | .clkdm_name = "l4_per_clkdm", | 3453 | .clkdm_name = "l4_per_clkdm", |
3455 | .mpu_irqs = omap44xx_uart2_irqs, | 3454 | .mpu_irqs = omap44xx_uart2_irqs, |
3456 | .sdma_reqs = omap44xx_uart2_sdma_reqs, | 3455 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
3457 | .main_clk = "uart2_fck", | 3456 | .main_clk = "func_48m_fclk", |
3458 | .prcm = { | 3457 | .prcm = { |
3459 | .omap4 = { | 3458 | .omap4 = { |
3460 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, | 3459 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
@@ -3483,7 +3482,7 @@ static struct omap_hwmod omap44xx_uart3_hwmod = { | |||
3483 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, | 3482 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
3484 | .mpu_irqs = omap44xx_uart3_irqs, | 3483 | .mpu_irqs = omap44xx_uart3_irqs, |
3485 | .sdma_reqs = omap44xx_uart3_sdma_reqs, | 3484 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
3486 | .main_clk = "uart3_fck", | 3485 | .main_clk = "func_48m_fclk", |
3487 | .prcm = { | 3486 | .prcm = { |
3488 | .omap4 = { | 3487 | .omap4 = { |
3489 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, | 3488 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
@@ -3511,7 +3510,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = { | |||
3511 | .clkdm_name = "l4_per_clkdm", | 3510 | .clkdm_name = "l4_per_clkdm", |
3512 | .mpu_irqs = omap44xx_uart4_irqs, | 3511 | .mpu_irqs = omap44xx_uart4_irqs, |
3513 | .sdma_reqs = omap44xx_uart4_sdma_reqs, | 3512 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
3514 | .main_clk = "uart4_fck", | 3513 | .main_clk = "func_48m_fclk", |
3515 | .prcm = { | 3514 | .prcm = { |
3516 | .omap4 = { | 3515 | .omap4 = { |
3517 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, | 3516 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
@@ -3790,7 +3789,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = { | |||
3790 | .class = &omap44xx_wd_timer_hwmod_class, | 3789 | .class = &omap44xx_wd_timer_hwmod_class, |
3791 | .clkdm_name = "l4_wkup_clkdm", | 3790 | .clkdm_name = "l4_wkup_clkdm", |
3792 | .mpu_irqs = omap44xx_wd_timer2_irqs, | 3791 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
3793 | .main_clk = "wd_timer2_fck", | 3792 | .main_clk = "sys_32k_ck", |
3794 | .prcm = { | 3793 | .prcm = { |
3795 | .omap4 = { | 3794 | .omap4 = { |
3796 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, | 3795 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
@@ -3811,7 +3810,7 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = { | |||
3811 | .class = &omap44xx_wd_timer_hwmod_class, | 3810 | .class = &omap44xx_wd_timer_hwmod_class, |
3812 | .clkdm_name = "abe_clkdm", | 3811 | .clkdm_name = "abe_clkdm", |
3813 | .mpu_irqs = omap44xx_wd_timer3_irqs, | 3812 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
3814 | .main_clk = "wd_timer3_fck", | 3813 | .main_clk = "sys_32k_ck", |
3815 | .prcm = { | 3814 | .prcm = { |
3816 | .omap4 = { | 3815 | .omap4 = { |
3817 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, | 3816 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |