diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-12-09 17:38:28 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-12-09 17:38:28 -0500 |
commit | 6cd94d5e57ab97ddd672b707ab4bb639672c1727 (patch) | |
tree | b1b301b16433d4deab6bd52e81d04a7b58c239d3 /arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |
parent | 6c9e92476bc924ede6d6d2f0bfed2c06ae148d29 (diff) | |
parent | 842f7d2c4d392c0571cf72e3eaca26742bebbd1e (diff) |
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform changes from Arnd Bergmann:
"New and updated SoC support, notable changes include:
- bcm:
brcmstb SMP support
initial iproc/cygnus support
- exynos:
Exynos4415 SoC support
PMU and suspend support for Exynos5420
PMU support for Exynos3250
pm related maintenance
- imx:
new LS1021A SoC support
vybrid 610 global timer support
- integrator:
convert to using multiplatform configuration
- mediatek:
earlyprintk support for mt8127/mt8135
- meson:
meson8 soc and l2 cache controller support
- mvebu:
Armada 38x CPU hotplug support
drop support for prerelease Armada 375 Z1 stepping
extended suspend support, now works on Armada 370/XP
- omap:
hwmod related maintenance
prcm cleanup
- pxa:
initial pxa27x DT handling
- rockchip:
SMP support for rk3288
add cpu frequency scaling support
- shmobile:
r8a7740 power domain support
various small restart, timer, pci apmu changes
- sunxi:
Allwinner A80 (sun9i) earlyprintk support
- ux500:
power domain support
Overall, a significant chunk of changes, coming mostly from the usual
suspects: omap, shmobile, samsung and mvebu, all of which already
contain a lot of platform specific code in arch/arm"
* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits)
ARM: mvebu: use the cpufreq-dt platform_data for independent clocks
soc: integrator: Add terminating entry for integrator_cm_match
ARM: mvebu: add SDRAM controller description for Armada XP
ARM: mvebu: adjust mbus controller description on Armada 370/XP
ARM: mvebu: add suspend/resume DT information for Armada XP GP
ARM: mvebu: synchronize secondary CPU clocks on resume
ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
ARM: mvebu: Armada XP GP specific suspend/resume code
ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
ARM: mvebu: implement suspend/resume support for Armada XP
clk: mvebu: add suspend/resume for gatable clocks
bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
bus: mvebu-mbus: suspend/resume support
clocksource: time-armada-370-xp: add suspend/resume support
irqchip: armada-370-xp: Add suspend/resume support
ARM: add lolevel debug support for asm9260
ARM: add mach-asm9260
ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
power: reset: imx-snvs-poweroff: add power off driver for i.mx6
ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
...
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_44xx_data.c')
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 25 |
1 files changed, 16 insertions, 9 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index d8a3cf1c1787..c314b3c31117 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
@@ -589,6 +589,7 @@ static struct omap_hwmod omap44xx_dss_hwmod = { | |||
589 | .omap4 = { | 589 | .omap4 = { |
590 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, | 590 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
591 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, | 591 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
592 | .modulemode = MODULEMODE_SWCTRL, | ||
592 | }, | 593 | }, |
593 | }, | 594 | }, |
594 | .opt_clks = dss_opt_clks, | 595 | .opt_clks = dss_opt_clks, |
@@ -647,7 +648,8 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = { | |||
647 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, | 648 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
648 | }, | 649 | }, |
649 | }, | 650 | }, |
650 | .dev_attr = &omap44xx_dss_dispc_dev_attr | 651 | .dev_attr = &omap44xx_dss_dispc_dev_attr, |
652 | .parent_hwmod = &omap44xx_dss_hwmod, | ||
651 | }; | 653 | }; |
652 | 654 | ||
653 | /* | 655 | /* |
@@ -701,6 +703,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { | |||
701 | }, | 703 | }, |
702 | .opt_clks = dss_dsi1_opt_clks, | 704 | .opt_clks = dss_dsi1_opt_clks, |
703 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), | 705 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), |
706 | .parent_hwmod = &omap44xx_dss_hwmod, | ||
704 | }; | 707 | }; |
705 | 708 | ||
706 | /* dss_dsi2 */ | 709 | /* dss_dsi2 */ |
@@ -733,6 +736,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { | |||
733 | }, | 736 | }, |
734 | .opt_clks = dss_dsi2_opt_clks, | 737 | .opt_clks = dss_dsi2_opt_clks, |
735 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), | 738 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), |
739 | .parent_hwmod = &omap44xx_dss_hwmod, | ||
736 | }; | 740 | }; |
737 | 741 | ||
738 | /* | 742 | /* |
@@ -790,6 +794,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { | |||
790 | }, | 794 | }, |
791 | .opt_clks = dss_hdmi_opt_clks, | 795 | .opt_clks = dss_hdmi_opt_clks, |
792 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), | 796 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), |
797 | .parent_hwmod = &omap44xx_dss_hwmod, | ||
793 | }; | 798 | }; |
794 | 799 | ||
795 | /* | 800 | /* |
@@ -819,7 +824,7 @@ static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { | |||
819 | }; | 824 | }; |
820 | 825 | ||
821 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { | 826 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
822 | { .role = "ick", .clk = "dss_fck" }, | 827 | { .role = "ick", .clk = "l3_div_ck" }, |
823 | }; | 828 | }; |
824 | 829 | ||
825 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { | 830 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
@@ -836,6 +841,7 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { | |||
836 | }, | 841 | }, |
837 | .opt_clks = dss_rfbi_opt_clks, | 842 | .opt_clks = dss_rfbi_opt_clks, |
838 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), | 843 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), |
844 | .parent_hwmod = &omap44xx_dss_hwmod, | ||
839 | }; | 845 | }; |
840 | 846 | ||
841 | /* | 847 | /* |
@@ -859,6 +865,7 @@ static struct omap_hwmod omap44xx_dss_venc_hwmod = { | |||
859 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, | 865 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
860 | }, | 866 | }, |
861 | }, | 867 | }, |
868 | .parent_hwmod = &omap44xx_dss_hwmod, | ||
862 | }; | 869 | }; |
863 | 870 | ||
864 | /* | 871 | /* |
@@ -3671,7 +3678,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { | |||
3671 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { | 3678 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { |
3672 | .master = &omap44xx_l3_main_2_hwmod, | 3679 | .master = &omap44xx_l3_main_2_hwmod, |
3673 | .slave = &omap44xx_dss_hwmod, | 3680 | .slave = &omap44xx_dss_hwmod, |
3674 | .clk = "dss_fck", | 3681 | .clk = "l3_div_ck", |
3675 | .addr = omap44xx_dss_dma_addrs, | 3682 | .addr = omap44xx_dss_dma_addrs, |
3676 | .user = OCP_USER_SDMA, | 3683 | .user = OCP_USER_SDMA, |
3677 | }; | 3684 | }; |
@@ -3707,7 +3714,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { | |||
3707 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { | 3714 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { |
3708 | .master = &omap44xx_l3_main_2_hwmod, | 3715 | .master = &omap44xx_l3_main_2_hwmod, |
3709 | .slave = &omap44xx_dss_dispc_hwmod, | 3716 | .slave = &omap44xx_dss_dispc_hwmod, |
3710 | .clk = "dss_fck", | 3717 | .clk = "l3_div_ck", |
3711 | .addr = omap44xx_dss_dispc_dma_addrs, | 3718 | .addr = omap44xx_dss_dispc_dma_addrs, |
3712 | .user = OCP_USER_SDMA, | 3719 | .user = OCP_USER_SDMA, |
3713 | }; | 3720 | }; |
@@ -3743,7 +3750,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { | |||
3743 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { | 3750 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { |
3744 | .master = &omap44xx_l3_main_2_hwmod, | 3751 | .master = &omap44xx_l3_main_2_hwmod, |
3745 | .slave = &omap44xx_dss_dsi1_hwmod, | 3752 | .slave = &omap44xx_dss_dsi1_hwmod, |
3746 | .clk = "dss_fck", | 3753 | .clk = "l3_div_ck", |
3747 | .addr = omap44xx_dss_dsi1_dma_addrs, | 3754 | .addr = omap44xx_dss_dsi1_dma_addrs, |
3748 | .user = OCP_USER_SDMA, | 3755 | .user = OCP_USER_SDMA, |
3749 | }; | 3756 | }; |
@@ -3779,7 +3786,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { | |||
3779 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { | 3786 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { |
3780 | .master = &omap44xx_l3_main_2_hwmod, | 3787 | .master = &omap44xx_l3_main_2_hwmod, |
3781 | .slave = &omap44xx_dss_dsi2_hwmod, | 3788 | .slave = &omap44xx_dss_dsi2_hwmod, |
3782 | .clk = "dss_fck", | 3789 | .clk = "l3_div_ck", |
3783 | .addr = omap44xx_dss_dsi2_dma_addrs, | 3790 | .addr = omap44xx_dss_dsi2_dma_addrs, |
3784 | .user = OCP_USER_SDMA, | 3791 | .user = OCP_USER_SDMA, |
3785 | }; | 3792 | }; |
@@ -3815,7 +3822,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { | |||
3815 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { | 3822 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { |
3816 | .master = &omap44xx_l3_main_2_hwmod, | 3823 | .master = &omap44xx_l3_main_2_hwmod, |
3817 | .slave = &omap44xx_dss_hdmi_hwmod, | 3824 | .slave = &omap44xx_dss_hdmi_hwmod, |
3818 | .clk = "dss_fck", | 3825 | .clk = "l3_div_ck", |
3819 | .addr = omap44xx_dss_hdmi_dma_addrs, | 3826 | .addr = omap44xx_dss_hdmi_dma_addrs, |
3820 | .user = OCP_USER_SDMA, | 3827 | .user = OCP_USER_SDMA, |
3821 | }; | 3828 | }; |
@@ -3851,7 +3858,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { | |||
3851 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { | 3858 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { |
3852 | .master = &omap44xx_l3_main_2_hwmod, | 3859 | .master = &omap44xx_l3_main_2_hwmod, |
3853 | .slave = &omap44xx_dss_rfbi_hwmod, | 3860 | .slave = &omap44xx_dss_rfbi_hwmod, |
3854 | .clk = "dss_fck", | 3861 | .clk = "l3_div_ck", |
3855 | .addr = omap44xx_dss_rfbi_dma_addrs, | 3862 | .addr = omap44xx_dss_rfbi_dma_addrs, |
3856 | .user = OCP_USER_SDMA, | 3863 | .user = OCP_USER_SDMA, |
3857 | }; | 3864 | }; |
@@ -3887,7 +3894,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { | |||
3887 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { | 3894 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { |
3888 | .master = &omap44xx_l3_main_2_hwmod, | 3895 | .master = &omap44xx_l3_main_2_hwmod, |
3889 | .slave = &omap44xx_dss_venc_hwmod, | 3896 | .slave = &omap44xx_dss_venc_hwmod, |
3890 | .clk = "dss_fck", | 3897 | .clk = "l3_div_ck", |
3891 | .addr = omap44xx_dss_venc_dma_addrs, | 3898 | .addr = omap44xx_dss_venc_dma_addrs, |
3892 | .user = OCP_USER_SDMA, | 3899 | .user = OCP_USER_SDMA, |
3893 | }; | 3900 | }; |