aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
diff options
context:
space:
mode:
authorTony Lindgren <tony@atomide.com>2013-11-25 18:17:12 -0500
committerTony Lindgren <tony@atomide.com>2013-11-25 18:31:18 -0500
commitb05ef2159dd373034332151ff7341d0231fae799 (patch)
tree1c3e26e6de18df2d1ece400428b8dda543d193b6 /arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
parentd6db0e7fa1de9559e09c141367740ecd97eb2fe6 (diff)
ARM: OMAP2+: Remove legacy hwmod entries for omap2
These now come from device tree except for DSS and DMA that still uses hwmod to initialize. That will get fixed when we DSS gets device tree bindings and we move completely to the dmaengine API. Cc: Paul Walmsley <paul@pwsan.com> [tony@atomide.com: updated to add trailing commas to structs] Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c72
1 files changed, 2 insertions, 70 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 56cebb05509e..8821b9d6bae4 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -20,14 +20,9 @@
20#include "prm-regbits-24xx.h" 20#include "prm-regbits-24xx.h"
21#include "wd_timer.h" 21#include "wd_timer.h"
22 22
23struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
24 { .irq = 48 + OMAP_INTC_START, },
25 { .irq = -1 },
26};
27
28struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { 23struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
29 { .name = "dispc", .dma_req = 5 }, 24 { .name = "dispc", .dma_req = 5 },
30 { .dma_req = -1 } 25 { .dma_req = -1, },
31}; 26};
32 27
33/* 28/*
@@ -219,14 +214,8 @@ struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
219}; 214};
220 215
221/* MPU */ 216/* MPU */
222static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
223 { .name = "pmu", .irq = 3 + OMAP_INTC_START },
224 { .irq = -1 }
225};
226
227struct omap_hwmod omap2xxx_mpu_hwmod = { 217struct omap_hwmod omap2xxx_mpu_hwmod = {
228 .name = "mpu", 218 .name = "mpu",
229 .mpu_irqs = omap2xxx_mpu_irqs,
230 .class = &mpu_hwmod_class, 219 .class = &mpu_hwmod_class,
231 .main_clk = "mpu_ck", 220 .main_clk = "mpu_ck",
232}; 221};
@@ -256,7 +245,6 @@ static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
256 245
257struct omap_hwmod omap2xxx_timer1_hwmod = { 246struct omap_hwmod omap2xxx_timer1_hwmod = {
258 .name = "timer1", 247 .name = "timer1",
259 .mpu_irqs = omap2_timer1_mpu_irqs,
260 .main_clk = "gpt1_fck", 248 .main_clk = "gpt1_fck",
261 .prcm = { 249 .prcm = {
262 .omap2 = { 250 .omap2 = {
@@ -276,7 +264,6 @@ struct omap_hwmod omap2xxx_timer1_hwmod = {
276 264
277struct omap_hwmod omap2xxx_timer2_hwmod = { 265struct omap_hwmod omap2xxx_timer2_hwmod = {
278 .name = "timer2", 266 .name = "timer2",
279 .mpu_irqs = omap2_timer2_mpu_irqs,
280 .main_clk = "gpt2_fck", 267 .main_clk = "gpt2_fck",
281 .prcm = { 268 .prcm = {
282 .omap2 = { 269 .omap2 = {
@@ -295,7 +282,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
295 282
296struct omap_hwmod omap2xxx_timer3_hwmod = { 283struct omap_hwmod omap2xxx_timer3_hwmod = {
297 .name = "timer3", 284 .name = "timer3",
298 .mpu_irqs = omap2_timer3_mpu_irqs,
299 .main_clk = "gpt3_fck", 285 .main_clk = "gpt3_fck",
300 .prcm = { 286 .prcm = {
301 .omap2 = { 287 .omap2 = {
@@ -314,7 +300,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
314 300
315struct omap_hwmod omap2xxx_timer4_hwmod = { 301struct omap_hwmod omap2xxx_timer4_hwmod = {
316 .name = "timer4", 302 .name = "timer4",
317 .mpu_irqs = omap2_timer4_mpu_irqs,
318 .main_clk = "gpt4_fck", 303 .main_clk = "gpt4_fck",
319 .prcm = { 304 .prcm = {
320 .omap2 = { 305 .omap2 = {
@@ -333,7 +318,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
333 318
334struct omap_hwmod omap2xxx_timer5_hwmod = { 319struct omap_hwmod omap2xxx_timer5_hwmod = {
335 .name = "timer5", 320 .name = "timer5",
336 .mpu_irqs = omap2_timer5_mpu_irqs,
337 .main_clk = "gpt5_fck", 321 .main_clk = "gpt5_fck",
338 .prcm = { 322 .prcm = {
339 .omap2 = { 323 .omap2 = {
@@ -353,7 +337,6 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
353 337
354struct omap_hwmod omap2xxx_timer6_hwmod = { 338struct omap_hwmod omap2xxx_timer6_hwmod = {
355 .name = "timer6", 339 .name = "timer6",
356 .mpu_irqs = omap2_timer6_mpu_irqs,
357 .main_clk = "gpt6_fck", 340 .main_clk = "gpt6_fck",
358 .prcm = { 341 .prcm = {
359 .omap2 = { 342 .omap2 = {
@@ -373,7 +356,6 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
373 356
374struct omap_hwmod omap2xxx_timer7_hwmod = { 357struct omap_hwmod omap2xxx_timer7_hwmod = {
375 .name = "timer7", 358 .name = "timer7",
376 .mpu_irqs = omap2_timer7_mpu_irqs,
377 .main_clk = "gpt7_fck", 359 .main_clk = "gpt7_fck",
378 .prcm = { 360 .prcm = {
379 .omap2 = { 361 .omap2 = {
@@ -393,7 +375,6 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
393 375
394struct omap_hwmod omap2xxx_timer8_hwmod = { 376struct omap_hwmod omap2xxx_timer8_hwmod = {
395 .name = "timer8", 377 .name = "timer8",
396 .mpu_irqs = omap2_timer8_mpu_irqs,
397 .main_clk = "gpt8_fck", 378 .main_clk = "gpt8_fck",
398 .prcm = { 379 .prcm = {
399 .omap2 = { 380 .omap2 = {
@@ -413,7 +394,6 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
413 394
414struct omap_hwmod omap2xxx_timer9_hwmod = { 395struct omap_hwmod omap2xxx_timer9_hwmod = {
415 .name = "timer9", 396 .name = "timer9",
416 .mpu_irqs = omap2_timer9_mpu_irqs,
417 .main_clk = "gpt9_fck", 397 .main_clk = "gpt9_fck",
418 .prcm = { 398 .prcm = {
419 .omap2 = { 399 .omap2 = {
@@ -433,7 +413,6 @@ struct omap_hwmod omap2xxx_timer9_hwmod = {
433 413
434struct omap_hwmod omap2xxx_timer10_hwmod = { 414struct omap_hwmod omap2xxx_timer10_hwmod = {
435 .name = "timer10", 415 .name = "timer10",
436 .mpu_irqs = omap2_timer10_mpu_irqs,
437 .main_clk = "gpt10_fck", 416 .main_clk = "gpt10_fck",
438 .prcm = { 417 .prcm = {
439 .omap2 = { 418 .omap2 = {
@@ -453,7 +432,6 @@ struct omap_hwmod omap2xxx_timer10_hwmod = {
453 432
454struct omap_hwmod omap2xxx_timer11_hwmod = { 433struct omap_hwmod omap2xxx_timer11_hwmod = {
455 .name = "timer11", 434 .name = "timer11",
456 .mpu_irqs = omap2_timer11_mpu_irqs,
457 .main_clk = "gpt11_fck", 435 .main_clk = "gpt11_fck",
458 .prcm = { 436 .prcm = {
459 .omap2 = { 437 .omap2 = {
@@ -473,7 +451,6 @@ struct omap_hwmod omap2xxx_timer11_hwmod = {
473 451
474struct omap_hwmod omap2xxx_timer12_hwmod = { 452struct omap_hwmod omap2xxx_timer12_hwmod = {
475 .name = "timer12", 453 .name = "timer12",
476 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
477 .main_clk = "gpt12_fck", 454 .main_clk = "gpt12_fck",
478 .prcm = { 455 .prcm = {
479 .omap2 = { 456 .omap2 = {
@@ -509,8 +486,6 @@ struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
509 486
510struct omap_hwmod omap2xxx_uart1_hwmod = { 487struct omap_hwmod omap2xxx_uart1_hwmod = {
511 .name = "uart1", 488 .name = "uart1",
512 .mpu_irqs = omap2_uart1_mpu_irqs,
513 .sdma_reqs = omap2_uart1_sdma_reqs,
514 .main_clk = "uart1_fck", 489 .main_clk = "uart1_fck",
515 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 490 .flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
516 .prcm = { 491 .prcm = {
@@ -529,8 +504,6 @@ struct omap_hwmod omap2xxx_uart1_hwmod = {
529 504
530struct omap_hwmod omap2xxx_uart2_hwmod = { 505struct omap_hwmod omap2xxx_uart2_hwmod = {
531 .name = "uart2", 506 .name = "uart2",
532 .mpu_irqs = omap2_uart2_mpu_irqs,
533 .sdma_reqs = omap2_uart2_sdma_reqs,
534 .main_clk = "uart2_fck", 507 .main_clk = "uart2_fck",
535 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 508 .flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
536 .prcm = { 509 .prcm = {
@@ -549,8 +522,6 @@ struct omap_hwmod omap2xxx_uart2_hwmod = {
549 522
550struct omap_hwmod omap2xxx_uart3_hwmod = { 523struct omap_hwmod omap2xxx_uart3_hwmod = {
551 .name = "uart3", 524 .name = "uart3",
552 .mpu_irqs = omap2_uart3_mpu_irqs,
553 .sdma_reqs = omap2_uart3_sdma_reqs,
554 .main_clk = "uart3_fck", 525 .main_clk = "uart3_fck",
555 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT, 526 .flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
556 .prcm = { 527 .prcm = {
@@ -610,7 +581,7 @@ struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
610 }, 581 },
611 }, 582 },
612 .flags = HWMOD_NO_IDLEST, 583 .flags = HWMOD_NO_IDLEST,
613 .dev_attr = &omap2_3_dss_dispc_dev_attr 584 .dev_attr = &omap2_3_dss_dispc_dev_attr,
614}; 585};
615 586
616static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { 587static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
@@ -657,7 +628,6 @@ struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
657struct omap_hwmod omap2xxx_gpio1_hwmod = { 628struct omap_hwmod omap2xxx_gpio1_hwmod = {
658 .name = "gpio1", 629 .name = "gpio1",
659 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 630 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
660 .mpu_irqs = omap2_gpio1_irqs,
661 .main_clk = "gpios_fck", 631 .main_clk = "gpios_fck",
662 .prcm = { 632 .prcm = {
663 .omap2 = { 633 .omap2 = {
@@ -676,7 +646,6 @@ struct omap_hwmod omap2xxx_gpio1_hwmod = {
676struct omap_hwmod omap2xxx_gpio2_hwmod = { 646struct omap_hwmod omap2xxx_gpio2_hwmod = {
677 .name = "gpio2", 647 .name = "gpio2",
678 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 648 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
679 .mpu_irqs = omap2_gpio2_irqs,
680 .main_clk = "gpios_fck", 649 .main_clk = "gpios_fck",
681 .prcm = { 650 .prcm = {
682 .omap2 = { 651 .omap2 = {
@@ -695,7 +664,6 @@ struct omap_hwmod omap2xxx_gpio2_hwmod = {
695struct omap_hwmod omap2xxx_gpio3_hwmod = { 664struct omap_hwmod omap2xxx_gpio3_hwmod = {
696 .name = "gpio3", 665 .name = "gpio3",
697 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 666 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
698 .mpu_irqs = omap2_gpio3_irqs,
699 .main_clk = "gpios_fck", 667 .main_clk = "gpios_fck",
700 .prcm = { 668 .prcm = {
701 .omap2 = { 669 .omap2 = {
@@ -714,7 +682,6 @@ struct omap_hwmod omap2xxx_gpio3_hwmod = {
714struct omap_hwmod omap2xxx_gpio4_hwmod = { 682struct omap_hwmod omap2xxx_gpio4_hwmod = {
715 .name = "gpio4", 683 .name = "gpio4",
716 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 684 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
717 .mpu_irqs = omap2_gpio4_irqs,
718 .main_clk = "gpios_fck", 685 .main_clk = "gpios_fck",
719 .prcm = { 686 .prcm = {
720 .omap2 = { 687 .omap2 = {
@@ -736,8 +703,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
736 703
737struct omap_hwmod omap2xxx_mcspi1_hwmod = { 704struct omap_hwmod omap2xxx_mcspi1_hwmod = {
738 .name = "mcspi1", 705 .name = "mcspi1",
739 .mpu_irqs = omap2_mcspi1_mpu_irqs,
740 .sdma_reqs = omap2_mcspi1_sdma_reqs,
741 .main_clk = "mcspi1_fck", 706 .main_clk = "mcspi1_fck",
742 .prcm = { 707 .prcm = {
743 .omap2 = { 708 .omap2 = {
@@ -759,8 +724,6 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
759 724
760struct omap_hwmod omap2xxx_mcspi2_hwmod = { 725struct omap_hwmod omap2xxx_mcspi2_hwmod = {
761 .name = "mcspi2", 726 .name = "mcspi2",
762 .mpu_irqs = omap2_mcspi2_mpu_irqs,
763 .sdma_reqs = omap2_mcspi2_sdma_reqs,
764 .main_clk = "mcspi2_fck", 727 .main_clk = "mcspi2_fck",
765 .prcm = { 728 .prcm = {
766 .omap2 = { 729 .omap2 = {
@@ -795,15 +758,9 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
795}; 758};
796 759
797/* gpmc */ 760/* gpmc */
798static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
799 { .irq = 20 },
800 { .irq = -1 }
801};
802
803struct omap_hwmod omap2xxx_gpmc_hwmod = { 761struct omap_hwmod omap2xxx_gpmc_hwmod = {
804 .name = "gpmc", 762 .name = "gpmc",
805 .class = &omap2xxx_gpmc_hwmod_class, 763 .class = &omap2xxx_gpmc_hwmod_class,
806 .mpu_irqs = omap2xxx_gpmc_irqs,
807 .main_clk = "gpmc_fck", 764 .main_clk = "gpmc_fck",
808 /* 765 /*
809 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP 766 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
@@ -840,14 +797,8 @@ static struct omap_hwmod_class omap2_rng_hwmod_class = {
840 .sysc = &omap2_rng_sysc, 797 .sysc = &omap2_rng_sysc,
841}; 798};
842 799
843static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
844 { .irq = 52 },
845 { .irq = -1 }
846};
847
848struct omap_hwmod omap2xxx_rng_hwmod = { 800struct omap_hwmod omap2xxx_rng_hwmod = {
849 .name = "rng", 801 .name = "rng",
850 .mpu_irqs = omap2_rng_mpu_irqs,
851 .main_clk = "l4_ck", 802 .main_clk = "l4_ck",
852 .prcm = { 803 .prcm = {
853 .omap2 = { 804 .omap2 = {
@@ -884,20 +835,8 @@ static struct omap_hwmod_class omap2xxx_sham_class = {
884 .sysc = &omap2_sham_sysc, 835 .sysc = &omap2_sham_sysc,
885}; 836};
886 837
887static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
888 { .irq = 51 + OMAP_INTC_START, },
889 { .irq = -1 }
890};
891
892static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
893 { .name = "rx", .dma_req = 13 },
894 { .dma_req = -1 }
895};
896
897struct omap_hwmod omap2xxx_sham_hwmod = { 838struct omap_hwmod omap2xxx_sham_hwmod = {
898 .name = "sham", 839 .name = "sham",
899 .mpu_irqs = omap2_sham_mpu_irqs,
900 .sdma_reqs = omap2_sham_sdma_chs,
901 .main_clk = "l4_ck", 840 .main_clk = "l4_ck",
902 .prcm = { 841 .prcm = {
903 .omap2 = { 842 .omap2 = {
@@ -927,15 +866,8 @@ static struct omap_hwmod_class omap2xxx_aes_class = {
927 .sysc = &omap2_aes_sysc, 866 .sysc = &omap2_aes_sysc,
928}; 867};
929 868
930static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = {
931 { .name = "tx", .dma_req = 9 },
932 { .name = "rx", .dma_req = 10 },
933 { .dma_req = -1 }
934};
935
936struct omap_hwmod omap2xxx_aes_hwmod = { 869struct omap_hwmod omap2xxx_aes_hwmod = {
937 .name = "aes", 870 .name = "aes",
938 .sdma_reqs = omap2_aes_sdma_chs,
939 .main_clk = "l4_ck", 871 .main_clk = "l4_ck",
940 .prcm = { 872 .prcm = {
941 .omap2 = { 873 .omap2 = {