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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2010-06-16 12:49:48 -0400
committerKevin Hilman <khilman@ti.com>2011-12-08 14:29:00 -0500
commitb2b9762f76981c16a8768255284efeae7f27e4f1 (patch)
tree3538b853da88eedeb2c64646b9555736000ba73a /arch/arm/mach-omap2/omap4-sar-layout.h
parentfcf6efa3ffbc3cc19e7abe39e0b90f497df2fc42 (diff)
ARM: OMAP4: PM: Add CPUX OFF mode support
This patch adds the CPU0 and CPU1 off mode support. CPUX close switch retention (CSWR) is not supported by hardware design. The CPUx OFF mode isn't supported on OMAP4430 ES1.0 CPUx sleep code is common for hotplug, suspend and CPUilde. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap4-sar-layout.h')
-rw-r--r--arch/arm/mach-omap2/omap4-sar-layout.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index 7781ea4dacbc..970a2eef3ab9 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -19,4 +19,13 @@
19#define SAR_BANK3_OFFSET 0x2000 19#define SAR_BANK3_OFFSET 0x2000
20#define SAR_BANK4_OFFSET 0x3000 20#define SAR_BANK4_OFFSET 0x3000
21 21
22/* Scratch pad memory offsets from SAR_BANK1 */
23#define SCU_OFFSET0 0xd00
24#define SCU_OFFSET1 0xd04
25#define OMAP_TYPE_OFFSET 0xd10
26
27/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
28#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04
29#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08
30
22#endif 31#endif