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authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /arch/arm/mach-omap2/include
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'arch/arm/mach-omap2/include')
-rw-r--r--arch/arm/mach-omap2/include/mach/am35xx.h26
-rw-r--r--arch/arm/mach-omap2/include/mach/board-sdp.h21
-rw-r--r--arch/arm/mach-omap2/include/mach/board-zoom.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/clkdev.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/debug-macro.S131
-rw-r--r--arch/arm/mach-omap2/include/mach/entry-macro.S212
-rw-r--r--arch/arm/mach-omap2/include/mach/gpio.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/hardware.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/io.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/memory.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/smp.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/system.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/timex.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/uncompress.h5
-rw-r--r--arch/arm/mach-omap2/include/mach/vmalloc.h20
16 files changed, 465 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h
new file mode 100644
index 000000000000..a705f946fc46
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/am35xx.h
@@ -0,0 +1,26 @@
1/*:
2 * Address mappings and base address for AM35XX specific interconnects
3 * and peripherals.
4 *
5 * Copyright (C) 2009 Texas Instruments
6 *
7 * Author: Sriramakrishnan <srk@ti.com>
8 * Vaibhav Hiremath <hvaibhav@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#ifndef __ASM_ARCH_AM35XX_H
15#define __ASM_ARCH_AM35XX_H
16
17/*
18 * Base addresses
19 * Note: OMAP3430 IVA2 memory space is being used for AM35xx IPSS modules
20 */
21#define AM35XX_IPSS_EMAC_BASE 0x5C000000
22#define AM35XX_IPSS_USBOTGSS_BASE 0x5C040000
23#define AM35XX_IPSS_HECC_BASE 0x5C050000
24#define AM35XX_IPSS_VPFE_BASE 0x5C060000
25
26#endif /* __ASM_ARCH_AM35XX_H */
diff --git a/arch/arm/mach-omap2/include/mach/board-sdp.h b/arch/arm/mach-omap2/include/mach/board-sdp.h
new file mode 100644
index 000000000000..465169c0908a
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/board-sdp.h
@@ -0,0 +1,21 @@
1/*
2 * board-sdp.h
3 *
4 * Information structures for SDP-specific board config data
5 *
6 * Copyright (C) 2009 Nokia Corporation
7 * Copyright (C) 2009 Texas Instruments
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/partitions.h>
15
16struct flash_partitions {
17 struct mtd_partition *parts;
18 int nr_parts;
19};
20
21extern void sdp_flash_init(struct flash_partitions []);
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
new file mode 100644
index 000000000000..c93b29e21b78
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -0,0 +1,5 @@
1/*
2 * Defines for zoom boards
3 */
4extern int __init zoom_debugboard_init(void);
5extern void __init zoom_peripherals_init(void);
diff --git a/arch/arm/mach-omap2/include/mach/clkdev.h b/arch/arm/mach-omap2/include/mach/clkdev.h
new file mode 100644
index 000000000000..53b027441c56
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/clkdev.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/clkdev.h
3 */
4
5#include <plat/clkdev.h>
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
new file mode 100644
index 000000000000..4a63a2ea484d
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -0,0 +1,131 @@
1/* arch/arm/mach-omap2/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/serial_reg.h>
15
16#include <plat/serial.h>
17
18#define UART_OFFSET(addr) ((addr) & 0x00ffffff)
19
20 .pushsection .data
21omap_uart_phys: .word 0
22omap_uart_virt: .word 0
23omap_uart_lsr: .word 0
24 .popsection
25
26 /*
27 * Note that this code won't work if the bootloader passes
28 * a wrong machine ID number in r1. To debug, just hardcode
29 * the desired UART phys and virt addresses temporarily into
30 * the omap_uart_phys and omap_uart_virt above.
31 */
32 .macro addruart, rx, tmp
33
34 /* Use omap_uart_phys/virt if already configured */
3510: mrc p15, 0, \rx, c1, c0
36 tst \rx, #1 @ MMU enabled?
37 ldreq \rx, =omap_uart_phys @ physical base address
38 ldrne \rx, =omap_uart_virt @ virtual base address
39 ldr \rx, [\rx, #0]
40 cmp \rx, #0 @ is port configured?
41 bne 99f @ already configured
42
43 /* Check UART1 scratchpad register for uart to use */
44 mrc p15, 0, \rx, c1, c0
45 tst \rx, #1 @ MMU enabled?
46 moveq \rx, #0x48000000 @ physical base address
47 movne \rx, #0xfa000000 @ virtual base
48 orr \rx, \rx, #0x0006a000 @ uart1 on omap2/3/4
49 ldrb \rx, [\rx, #(UART_SCR << OMAP_PORT_SHIFT)] @ scratchpad
50
51 /* Select the UART to use based on the UART1 scratchpad value */
52 cmp \rx, #0 @ no port configured?
53 beq 21f @ if none, try to use UART1
54 cmp \rx, #OMAP2UART1 @ OMAP2/3/4UART1
55 beq 21f @ configure OMAP2/3/4UART1
56 cmp \rx, #OMAP2UART2 @ OMAP2/3/4UART2
57 beq 22f @ configure OMAP2/3/4UART2
58 cmp \rx, #OMAP2UART3 @ only on 24xx
59 beq 23f @ configure OMAP2UART3
60 cmp \rx, #OMAP3UART3 @ only on 34xx
61 beq 33f @ configure OMAP3UART3
62 cmp \rx, #OMAP4UART3 @ only on 44xx
63 beq 43f @ configure OMAP4UART3
64 cmp \rx, #OMAP3UART4 @ only on 36xx
65 beq 34f @ configure OMAP3UART4
66 cmp \rx, #OMAP4UART4 @ only on 44xx
67 beq 44f @ configure OMAP4UART4
68 cmp \rx, #ZOOM_UART @ only on zoom2/3
69 beq 95f @ configure ZOOM_UART
70
71 /* Configure the UART offset from the phys/virt base */
7221: mov \rx, #UART_OFFSET(OMAP2_UART1_BASE) @ omap2/3/4
73 b 98f
7422: mov \rx, #UART_OFFSET(OMAP2_UART2_BASE) @ omap2/3/4
75 b 98f
7623: mov \rx, #UART_OFFSET(OMAP2_UART3_BASE)
77 b 98f
7833: mov \rx, #UART_OFFSET(OMAP3_UART1_BASE)
79 add \rx, \rx, #0x00fb0000
80 add \rx, \rx, #0x00006000 @ OMAP3_UART3_BASE
81 b 98f
8234: mov \rx, #UART_OFFSET(OMAP3_UART1_BASE)
83 add \rx, \rx, #0x00fb0000
84 add \rx, \rx, #0x00028000 @ OMAP3_UART4_BASE
85 b 98f
8643: mov \rx, #UART_OFFSET(OMAP4_UART3_BASE)
87 b 98f
8844: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE)
89 b 98f
9095: mov \rx, #ZOOM_UART_BASE
91 ldr \tmp, =omap_uart_phys
92 str \rx, [\tmp, #0]
93 mov \rx, #ZOOM_UART_VIRT
94 ldr \tmp, =omap_uart_virt
95 str \rx, [\tmp, #0]
96 mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT)
97 ldr \tmp, =omap_uart_lsr
98 str \rx, [\tmp, #0]
99 b 10b
100
101 /* Store both phys and virt address for the uart */
10298: add \rx, \rx, #0x48000000 @ phys base
103 ldr \tmp, =omap_uart_phys
104 str \rx, [\tmp, #0]
105 sub \rx, \rx, #0x48000000 @ phys base
106 add \rx, \rx, #0xfa000000 @ virt base
107 ldr \tmp, =omap_uart_virt
108 str \rx, [\tmp, #0]
109 mov \rx, #(UART_LSR << OMAP_PORT_SHIFT)
110 ldr \tmp, =omap_uart_lsr
111 str \rx, [\tmp, #0]
112
113 b 10b
11499:
115 .endm
116
117 .macro senduart,rd,rx
118 strb \rd, [\rx]
119 .endm
120
121 .macro busyuart,rd,rx
1221001: ldr \rd, =omap_uart_lsr
123 ldr \rd, [\rd, #0]
124 ldrb \rd, [\rx, \rd]
125 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
126 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
127 bne 1001b
128 .endm
129
130 .macro waituart,rd,rx
131 .endm
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
new file mode 100644
index 000000000000..50fd74916643
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -0,0 +1,212 @@
1/*
2 * arch/arm/plat-omap/include/mach/entry-macro.S
3 *
4 * Low-level IRQ helper macros for OMAP-based platforms
5 *
6 * Copyright (C) 2009 Texas Instruments
7 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13#include <mach/hardware.h>
14#include <mach/io.h>
15#include <mach/irqs.h>
16#include <asm/hardware/gic.h>
17
18#include <plat/omap24xx.h>
19#include <plat/omap34xx.h>
20#include <plat/omap44xx.h>
21
22#include <plat/multi.h>
23
24#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
25#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
26#define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
27#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
28#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
29
30 .macro disable_fiq
31 .endm
32
33 .macro arch_ret_to_user, tmp1, tmp2
34 .endm
35
36/*
37 * Unoptimized irq functions for multi-omap2, 3 and 4
38 */
39
40#ifdef MULTI_OMAP2
41 .pushsection .data
42omap_irq_base: .word 0
43 .popsection
44
45 /* Configure the interrupt base on the first interrupt */
46 .macro get_irqnr_preamble, base, tmp
479:
48 ldr \base, =omap_irq_base @ irq base address
49 ldr \base, [\base, #0] @ irq base value
50 cmp \base, #0 @ already configured?
51 bne 9997f @ nothing to do
52
53 mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision
54 and \tmp, \tmp, #0x000f0000 @ only check architecture
55 cmp \tmp, #0x00070000 @ is v6?
56 beq 2400f @ found v6 so it's omap24xx
57 mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision
58 and \tmp, \tmp, #0x000000f0 @ check cortex 8 or 9
59 cmp \tmp, #0x00000080 @ cortex A-8?
60 beq 3400f @ found A-8 so it's omap34xx
61 cmp \tmp, #0x00000090 @ cortex A-9?
62 beq 4400f @ found A-9 so it's omap44xx
632400: ldr \base, =OMAP2_IRQ_BASE
64 ldr \tmp, =omap_irq_base
65 str \base, [\tmp, #0]
66 b 9b
673400: ldr \base, =OMAP3_IRQ_BASE
68 ldr \tmp, =omap_irq_base
69 str \base, [\tmp, #0]
70 b 9b
714400: ldr \base, =OMAP4_IRQ_BASE
72 ldr \tmp, =omap_irq_base
73 str \base, [\tmp, #0]
74 b 9b
759997:
76 .endm
77
78 /* Check the pending interrupts. Note that base already set */
79 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
80 tst \base, #0x100 @ gic address?
81 bne 4401f @ found gic
82
83 /* Handle omap2 and omap3 */
84 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
85 cmp \irqnr, #0x0
86 bne 9998f
87 ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
88 cmp \irqnr, #0x0
89 bne 9998f
90 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
91 cmp \irqnr, #0x0
929998:
93 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
94 and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
95 b 9999f
96
97 /* Handle omap4 */
984401: ldr \irqstat, [\base, #GIC_CPU_INTACK]
99 ldr \tmp, =1021
100 bic \irqnr, \irqstat, #0x1c00
101 cmp \irqnr, #29
102 cmpcc \irqnr, \irqnr
103 cmpne \irqnr, \tmp
104 cmpcs \irqnr, \irqnr
1059999:
106 .endm
107
108
109#else /* MULTI_OMAP2 */
110
111
112/*
113 * Optimized irq functions for omap2, 3 and 4
114 */
115
116#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
117 .macro get_irqnr_preamble, base, tmp
118#ifdef CONFIG_ARCH_OMAP2
119 ldr \base, =OMAP2_IRQ_BASE
120#else
121 ldr \base, =OMAP3_IRQ_BASE
122#endif
123 .endm
124
125 /* Check the pending interrupts. Note that base already set */
126 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
127 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
128 cmp \irqnr, #0x0
129 bne 9999f
130 ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
131 cmp \irqnr, #0x0
132 bne 9999f
133 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
134 cmp \irqnr, #0x0
1359999:
136 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
137 and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
138
139 .endm
140#endif
141
142
143#ifdef CONFIG_ARCH_OMAP4
144
145 .macro get_irqnr_preamble, base, tmp
146 ldr \base, =OMAP4_IRQ_BASE
147 .endm
148
149 /*
150 * The interrupt numbering scheme is defined in the
151 * interrupt controller spec. To wit:
152 *
153 * Interrupts 0-15 are IPI
154 * 16-28 are reserved
155 * 29-31 are local. We allow 30 to be used for the watchdog.
156 * 32-1020 are global
157 * 1021-1022 are reserved
158 * 1023 is "spurious" (no interrupt)
159 *
160 * For now, we ignore all local interrupts so only return an
161 * interrupt if it's between 30 and 1020. The test_for_ipi
162 * routine below will pick up on IPIs.
163 * A simple read from the controller will tell us the number
164 * of the highest priority enabled interrupt.
165 * We then just need to check whether it is in the
166 * valid range for an IRQ (30-1020 inclusive).
167 */
168 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
169 ldr \irqstat, [\base, #GIC_CPU_INTACK]
170
171 ldr \tmp, =1021
172
173 bic \irqnr, \irqstat, #0x1c00
174
175 cmp \irqnr, #29
176 cmpcc \irqnr, \irqnr
177 cmpne \irqnr, \tmp
178 cmpcs \irqnr, \irqnr
179 .endm
180
181 /* We assume that irqstat (the raw value of the IRQ acknowledge
182 * register) is preserved from the macro above.
183 * If there is an IPI, we immediately signal end of interrupt
184 * on the controller, since this requires the original irqstat
185 * value which we won't easily be able to recreate later.
186 */
187
188 .macro test_for_ipi, irqnr, irqstat, base, tmp
189 bic \irqnr, \irqstat, #0x1c00
190 cmp \irqnr, #16
191 it cc
192 strcc \irqstat, [\base, #GIC_CPU_EOI]
193 it cs
194 cmpcs \irqnr, \irqnr
195 .endm
196
197 /* As above, this assumes that irqstat and base are preserved */
198
199 .macro test_for_ltirq, irqnr, irqstat, base, tmp
200 bic \irqnr, \irqstat, #0x1c00
201 mov \tmp, #0
202 cmp \irqnr, #29
203 itt eq
204 moveq \tmp, #1
205 streq \irqstat, [\base, #GIC_CPU_EOI]
206 cmp \tmp, #0
207 .endm
208#endif
209#endif /* MULTI_OMAP2 */
210
211 .macro irq_prio_table
212 .endm
diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h
new file mode 100644
index 000000000000..be4d290d57ee
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/gpio.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/gpio.h
3 */
4
5#include <plat/gpio.h>
diff --git a/arch/arm/mach-omap2/include/mach/hardware.h b/arch/arm/mach-omap2/include/mach/hardware.h
new file mode 100644
index 000000000000..78edf9d33f71
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/hardware.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/hardware.h
3 */
4
5#include <plat/hardware.h>
diff --git a/arch/arm/mach-omap2/include/mach/io.h b/arch/arm/mach-omap2/include/mach/io.h
new file mode 100644
index 000000000000..fd78f31aa1ad
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/io.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/io.h
3 */
4
5#include <plat/io.h>
diff --git a/arch/arm/mach-omap2/include/mach/irqs.h b/arch/arm/mach-omap2/include/mach/irqs.h
new file mode 100644
index 000000000000..44dab7725696
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/irqs.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/irqs.h
3 */
4
5#include <plat/irqs.h>
diff --git a/arch/arm/mach-omap2/include/mach/memory.h b/arch/arm/mach-omap2/include/mach/memory.h
new file mode 100644
index 000000000000..ca6d32a917dd
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/memory.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/memory.h
3 */
4
5#include <plat/memory.h>
diff --git a/arch/arm/mach-omap2/include/mach/smp.h b/arch/arm/mach-omap2/include/mach/smp.h
new file mode 100644
index 000000000000..323675f21b69
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/smp.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/smp.h
3 */
4
5#include <plat/smp.h>
diff --git a/arch/arm/mach-omap2/include/mach/system.h b/arch/arm/mach-omap2/include/mach/system.h
new file mode 100644
index 000000000000..d488721ab90b
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/system.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/system.h
3 */
4
5#include <plat/system.h>
diff --git a/arch/arm/mach-omap2/include/mach/timex.h b/arch/arm/mach-omap2/include/mach/timex.h
new file mode 100644
index 000000000000..de9f8fc40e7c
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/timex.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/timex.h
3 */
4
5#include <plat/timex.h>
diff --git a/arch/arm/mach-omap2/include/mach/uncompress.h b/arch/arm/mach-omap2/include/mach/uncompress.h
new file mode 100644
index 000000000000..78e0557bfd4e
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/uncompress.h
@@ -0,0 +1,5 @@
1/*
2 * arch/arm/mach-omap2/include/mach/uncompress.h
3 */
4
5#include <plat/uncompress.h>
diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h
new file mode 100644
index 000000000000..9ce9b6e8ad23
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
1/*
2 * arch/arm/plat-omap/include/mach/vmalloc.h
3 *
4 * Copyright (C) 2000 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x38000000)
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-02 18:57:15 -0400