diff options
author | Adrian Hunter <adrian.hunter@nokia.com> | 2010-12-09 03:48:27 -0500 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2010-12-21 15:05:25 -0500 |
commit | a3551f5b0c3ca7aaa053e554e3ee766983b5d713 (patch) | |
tree | 76fec6e7169219e26c67ff206713b2d09771e33b /arch/arm/mach-omap2/gpmc-onenand.c | |
parent | 4584acc3ee236424b5d0b52f143d980cae3c2be5 (diff) |
OMAP2/3: GPMC: put sync_clk value in picoseconds instead of nanoseconds
The calculations done with sync_clk are anyway in picoseconds
and switching to picoseconds allows sync_clk values that are
not a whole number of nanoseconds - which is sometimes the
case.
Signed-off-by: Adrian Hunter <adrian.hunter@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/gpmc-onenand.c')
-rw-r--r-- | arch/arm/mach-omap2/gpmc-onenand.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c index 7bb69220adfa..1db606ca007e 100644 --- a/arch/arm/mach-omap2/gpmc-onenand.c +++ b/arch/arm/mach-omap2/gpmc-onenand.c | |||
@@ -174,7 +174,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, | |||
174 | 174 | ||
175 | switch (freq) { | 175 | switch (freq) { |
176 | case 83: | 176 | case 83: |
177 | min_gpmc_clk_period = 12; /* 83 MHz */ | 177 | min_gpmc_clk_period = 12000; /* 83 MHz */ |
178 | t_ces = 5; | 178 | t_ces = 5; |
179 | t_avds = 4; | 179 | t_avds = 4; |
180 | t_avdh = 2; | 180 | t_avdh = 2; |
@@ -183,7 +183,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, | |||
183 | t_rdyo = 9; | 183 | t_rdyo = 9; |
184 | break; | 184 | break; |
185 | case 66: | 185 | case 66: |
186 | min_gpmc_clk_period = 15; /* 66 MHz */ | 186 | min_gpmc_clk_period = 15000; /* 66 MHz */ |
187 | t_ces = 6; | 187 | t_ces = 6; |
188 | t_avds = 5; | 188 | t_avds = 5; |
189 | t_avdh = 2; | 189 | t_avdh = 2; |
@@ -192,7 +192,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, | |||
192 | t_rdyo = 11; | 192 | t_rdyo = 11; |
193 | break; | 193 | break; |
194 | default: | 194 | default: |
195 | min_gpmc_clk_period = 18; /* 54 MHz */ | 195 | min_gpmc_clk_period = 18500; /* 54 MHz */ |
196 | t_ces = 7; | 196 | t_ces = 7; |
197 | t_avds = 7; | 197 | t_avds = 7; |
198 | t_avdh = 7; | 198 | t_avdh = 7; |
@@ -271,8 +271,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg, | |||
271 | t.wr_cycle = t.rd_cycle; | 271 | t.wr_cycle = t.rd_cycle; |
272 | if (cpu_is_omap34xx()) { | 272 | if (cpu_is_omap34xx()) { |
273 | t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset + | 273 | t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset + |
274 | gpmc_ns_to_ticks(min_gpmc_clk_period + | 274 | gpmc_ps_to_ticks(min_gpmc_clk_period + |
275 | t_rdyo)); | 275 | t_rdyo * 1000)); |
276 | t.wr_access = t.access; | 276 | t.wr_access = t.access; |
277 | } | 277 | } |
278 | } else { | 278 | } else { |