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authorRussell King <rmk+kernel@arm.linux.org.uk>2013-11-08 13:04:06 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-04-03 19:31:44 -0400
commit64a2dc3d3de4235eb73921d870a674a23d9888f0 (patch)
tree02be605c9a07a76952dc8678d7e7a4e0c2bac2f3 /arch/arm/mach-omap2/dma.c
parentad0c381a8b3a15b8edfca0996729ea45692470ca (diff)
ARM: omap: clean up DMA register accesses
We can do much better with this by using a structure to describe each register, rather than code. Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-omap2/dma.c')
-rw-r--r--arch/arm/mach-omap2/dma.c99
1 files changed, 48 insertions, 51 deletions
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index e4ac7ac9a228..e633b48a3fcb 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -35,80 +35,77 @@
35#include "omap_hwmod.h" 35#include "omap_hwmod.h"
36#include "omap_device.h" 36#include "omap_device.h"
37 37
38#define OMAP2_DMA_STRIDE 0x60
39
40static u32 errata; 38static u32 errata;
41 39
42static struct omap_dma_dev_attr *d; 40static struct omap_dma_dev_attr *d;
43 41
44static enum omap_reg_offsets dma_common_ch_end; 42static enum omap_reg_offsets dma_common_ch_end;
45 43
46static u16 reg_map[] = { 44static const struct omap_dma_reg reg_map[] = {
47 [REVISION] = 0x00, 45 [REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
48 [GCR] = 0x78, 46 [GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
49 [IRQSTATUS_L0] = 0x08, 47 [IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
50 [IRQSTATUS_L1] = 0x0c, 48 [IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
51 [IRQSTATUS_L2] = 0x10, 49 [IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
52 [IRQSTATUS_L3] = 0x14, 50 [IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
53 [IRQENABLE_L0] = 0x18, 51 [IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
54 [IRQENABLE_L1] = 0x1c, 52 [IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
55 [IRQENABLE_L2] = 0x20, 53 [IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
56 [IRQENABLE_L3] = 0x24, 54 [IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
57 [SYSSTATUS] = 0x28, 55 [SYSSTATUS] = { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
58 [OCP_SYSCONFIG] = 0x2c, 56 [OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
59 [CAPS_0] = 0x64, 57 [CAPS_0] = { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
60 [CAPS_2] = 0x6c, 58 [CAPS_2] = { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
61 [CAPS_3] = 0x70, 59 [CAPS_3] = { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
62 [CAPS_4] = 0x74, 60 [CAPS_4] = { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
63 61
64 /* Common register offsets */ 62 /* Common register offsets */
65 [CCR] = 0x80, 63 [CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
66 [CLNK_CTRL] = 0x84, 64 [CLNK_CTRL] = { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
67 [CICR] = 0x88, 65 [CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
68 [CSR] = 0x8c, 66 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
69 [CSDP] = 0x90, 67 [CSDP] = { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
70 [CEN] = 0x94, 68 [CEN] = { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
71 [CFN] = 0x98, 69 [CFN] = { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
72 [CSEI] = 0xa4, 70 [CSEI] = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
73 [CSFI] = 0xa8, 71 [CSFI] = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
74 [CDEI] = 0xac, 72 [CDEI] = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
75 [CDFI] = 0xb0, 73 [CDFI] = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
76 [CSAC] = 0xb4, 74 [CSAC] = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
77 [CDAC] = 0xb8, 75 [CDAC] = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
78 76
79 /* Channel specific register offsets */ 77 /* Channel specific register offsets */
80 [CSSA] = 0x9c, 78 [CSSA] = { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
81 [CDSA] = 0xa0, 79 [CDSA] = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
82 [CCEN] = 0xbc, 80 [CCEN] = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
83 [CCFN] = 0xc0, 81 [CCFN] = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
84 [COLOR] = 0xc4, 82 [COLOR] = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
85 83
86 /* OMAP4 specific registers */ 84 /* OMAP4 specific registers */
87 [CDP] = 0xd0, 85 [CDP] = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
88 [CNDP] = 0xd4, 86 [CNDP] = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
89 [CCDN] = 0xd8, 87 [CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
90}; 88};
91 89
92static void __iomem *dma_base; 90static void __iomem *dma_base;
93static inline void dma_write(u32 val, int reg, int lch) 91static inline void dma_write(u32 val, int reg, int lch)
94{ 92{
95 u8 stride; 93 void __iomem *addr = dma_base;
96 u32 offset; 94
95 addr += reg_map[reg].offset;
96 addr += reg_map[reg].stride * lch;
97 97
98 stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0; 98 __raw_writel(val, addr);
99 offset = reg_map[reg] + (stride * lch);
100 __raw_writel(val, dma_base + offset);
101} 99}
102 100
103static inline u32 dma_read(int reg, int lch) 101static inline u32 dma_read(int reg, int lch)
104{ 102{
105 u8 stride; 103 void __iomem *addr = dma_base;
106 u32 offset, val; 104
105 addr += reg_map[reg].offset;
106 addr += reg_map[reg].stride * lch;
107 107
108 stride = (reg >= CSDP) ? OMAP2_DMA_STRIDE : 0; 108 return __raw_readl(addr);
109 offset = reg_map[reg] + (stride * lch);
110 val = __raw_readl(dma_base + offset);
111 return val;
112} 109}
113 110
114static void omap2_clear_dma(int lch) 111static void omap2_clear_dma(int lch)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-17 01:50:22 -0500