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authorSantosh Shilimkar <santosh.shilimkar@ti.com>2011-01-23 12:21:09 -0500
committerKevin Hilman <khilman@ti.com>2011-03-10 15:23:13 -0500
commit9062511097683b4422f023d181b4a8b2db1a7a72 (patch)
tree9e46fb8c0491a26bb25464d90b6cd4caf92edf5b /arch/arm/mach-omap2/common.c
parent46f557cb453b9f3b6dc36b8179c2c36932a2ea64 (diff)
OMAP3: PM: Clear the SCTLR C bit in asm code to prevent data cache allocation
On the newer ARM processors like CortexA8, CortexA9, the caches can be speculatively loaded while they are getting flushed. Clear the SCTLR C bit to prevent further data cache allocation as part of cache clean routine Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/common.c')
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