diff options
author | Paul Walmsley <paul@pwsan.com> | 2011-02-25 17:39:27 -0500 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2011-03-07 22:02:13 -0500 |
commit | 92618ff8b025419960e2e845983f0f49b0cb57a9 (patch) | |
tree | ac747c8eafb7cdd6fee8399464cf79aa1b8e1f00 /arch/arm/mach-omap2/cm2xxx_3xxx.h | |
parent | 0fd0c21be71293d8a54d9075b18b5a25a1868057 (diff) |
OMAP2xxx: clock: add clockfw autoidle support for APLLs
OMAP2xxx devices have two on-chip APLLs. These APLLs can
automatically enter idle when not in use. Connect the APLL autoidle
code to the clock code, so that the clock framework can handle this
process. As part of this patch, remove the code in mach-omap2/pm24xx.c
that previously handled APLL autoidle control.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Tested-by: Rajendra Nayak <rnayak@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/cm2xxx_3xxx.h')
-rw-r--r-- | arch/arm/mach-omap2/cm2xxx_3xxx.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h index 5f4df1ceafad..088bbad73db5 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h | |||
@@ -125,6 +125,11 @@ extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask); | |||
125 | extern void omap2xxx_cm_set_dpll_disable_autoidle(void); | 125 | extern void omap2xxx_cm_set_dpll_disable_autoidle(void); |
126 | extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void); | 126 | extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void); |
127 | 127 | ||
128 | extern void omap2xxx_cm_set_apll54_disable_autoidle(void); | ||
129 | extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void); | ||
130 | extern void omap2xxx_cm_set_apll96_disable_autoidle(void); | ||
131 | extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void); | ||
132 | |||
128 | #endif | 133 | #endif |
129 | 134 | ||
130 | /* CM register bits shared between 24XX and 3430 */ | 135 | /* CM register bits shared between 24XX and 3430 */ |