aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/clockdomains44xx_data.c
diff options
context:
space:
mode:
authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/arm/mach-omap2/clockdomains44xx_data.c
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'arch/arm/mach-omap2/clockdomains44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c689
1 files changed, 689 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
new file mode 100644
index 000000000000..a607ec196e8b
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -0,0 +1,689 @@
1/*
2 * OMAP4 Clock domains framework
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation
6 *
7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/kernel.h>
22#include <linux/io.h>
23
24#include "clockdomain.h"
25#include "cm1_44xx.h"
26#include "cm2_44xx.h"
27
28#include "cm-regbits-44xx.h"
29#include "prm44xx.h"
30#include "prcm44xx.h"
31#include "prcm_mpu44xx.h"
32
33/* Static Dependencies for OMAP4 Clock Domains */
34
35static struct clkdm_dep ducati_wkup_sleep_deps[] = {
36 {
37 .clkdm_name = "abe_clkdm",
38 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
39 },
40 {
41 .clkdm_name = "ivahd_clkdm",
42 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
43 },
44 {
45 .clkdm_name = "l3_1_clkdm",
46 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
47 },
48 {
49 .clkdm_name = "l3_2_clkdm",
50 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
51 },
52 {
53 .clkdm_name = "l3_dss_clkdm",
54 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
55 },
56 {
57 .clkdm_name = "l3_emif_clkdm",
58 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
59 },
60 {
61 .clkdm_name = "l3_gfx_clkdm",
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
63 },
64 {
65 .clkdm_name = "l3_init_clkdm",
66 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
67 },
68 {
69 .clkdm_name = "l4_cfg_clkdm",
70 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
71 },
72 {
73 .clkdm_name = "l4_per_clkdm",
74 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
75 },
76 {
77 .clkdm_name = "l4_secure_clkdm",
78 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
79 },
80 {
81 .clkdm_name = "l4_wkup_clkdm",
82 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
83 },
84 {
85 .clkdm_name = "tesla_clkdm",
86 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
87 },
88 { NULL },
89};
90
91static struct clkdm_dep iss_wkup_sleep_deps[] = {
92 {
93 .clkdm_name = "ivahd_clkdm",
94 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
95 },
96 {
97 .clkdm_name = "l3_1_clkdm",
98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
99 },
100 {
101 .clkdm_name = "l3_emif_clkdm",
102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
103 },
104 { NULL },
105};
106
107static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
108 {
109 .clkdm_name = "l3_1_clkdm",
110 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
111 },
112 {
113 .clkdm_name = "l3_emif_clkdm",
114 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
115 },
116 { NULL },
117};
118
119static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
120 {
121 .clkdm_name = "abe_clkdm",
122 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
123 },
124 {
125 .clkdm_name = "ivahd_clkdm",
126 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
127 },
128 {
129 .clkdm_name = "l3_1_clkdm",
130 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
131 },
132 {
133 .clkdm_name = "l3_2_clkdm",
134 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
135 },
136 {
137 .clkdm_name = "l3_emif_clkdm",
138 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
139 },
140 {
141 .clkdm_name = "l3_init_clkdm",
142 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
143 },
144 {
145 .clkdm_name = "l4_cfg_clkdm",
146 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
147 },
148 {
149 .clkdm_name = "l4_per_clkdm",
150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
151 },
152 { NULL },
153};
154
155static struct clkdm_dep l3_dma_wkup_sleep_deps[] = {
156 {
157 .clkdm_name = "abe_clkdm",
158 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
159 },
160 {
161 .clkdm_name = "ducati_clkdm",
162 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
163 },
164 {
165 .clkdm_name = "ivahd_clkdm",
166 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
167 },
168 {
169 .clkdm_name = "l3_1_clkdm",
170 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
171 },
172 {
173 .clkdm_name = "l3_dss_clkdm",
174 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
175 },
176 {
177 .clkdm_name = "l3_emif_clkdm",
178 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
179 },
180 {
181 .clkdm_name = "l3_init_clkdm",
182 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
183 },
184 {
185 .clkdm_name = "l4_cfg_clkdm",
186 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
187 },
188 {
189 .clkdm_name = "l4_per_clkdm",
190 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
191 },
192 {
193 .clkdm_name = "l4_secure_clkdm",
194 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
195 },
196 {
197 .clkdm_name = "l4_wkup_clkdm",
198 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
199 },
200 { NULL },
201};
202
203static struct clkdm_dep l3_dss_wkup_sleep_deps[] = {
204 {
205 .clkdm_name = "ivahd_clkdm",
206 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
207 },
208 {
209 .clkdm_name = "l3_2_clkdm",
210 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
211 },
212 {
213 .clkdm_name = "l3_emif_clkdm",
214 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
215 },
216 { NULL },
217};
218
219static struct clkdm_dep l3_gfx_wkup_sleep_deps[] = {
220 {
221 .clkdm_name = "ivahd_clkdm",
222 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
223 },
224 {
225 .clkdm_name = "l3_1_clkdm",
226 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
227 },
228 {
229 .clkdm_name = "l3_emif_clkdm",
230 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
231 },
232 { NULL },
233};
234
235static struct clkdm_dep l3_init_wkup_sleep_deps[] = {
236 {
237 .clkdm_name = "abe_clkdm",
238 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
239 },
240 {
241 .clkdm_name = "ivahd_clkdm",
242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
243 },
244 {
245 .clkdm_name = "l3_emif_clkdm",
246 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
247 },
248 {
249 .clkdm_name = "l4_cfg_clkdm",
250 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
251 },
252 {
253 .clkdm_name = "l4_per_clkdm",
254 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
255 },
256 {
257 .clkdm_name = "l4_secure_clkdm",
258 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
259 },
260 {
261 .clkdm_name = "l4_wkup_clkdm",
262 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
263 },
264 { NULL },
265};
266
267static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
268 {
269 .clkdm_name = "l3_1_clkdm",
270 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
271 },
272 {
273 .clkdm_name = "l3_emif_clkdm",
274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
275 },
276 {
277 .clkdm_name = "l4_per_clkdm",
278 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
279 },
280 { NULL },
281};
282
283static struct clkdm_dep mpuss_wkup_sleep_deps[] = {
284 {
285 .clkdm_name = "abe_clkdm",
286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
287 },
288 {
289 .clkdm_name = "ducati_clkdm",
290 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
291 },
292 {
293 .clkdm_name = "ivahd_clkdm",
294 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
295 },
296 {
297 .clkdm_name = "l3_1_clkdm",
298 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
299 },
300 {
301 .clkdm_name = "l3_2_clkdm",
302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
303 },
304 {
305 .clkdm_name = "l3_dss_clkdm",
306 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
307 },
308 {
309 .clkdm_name = "l3_emif_clkdm",
310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
311 },
312 {
313 .clkdm_name = "l3_gfx_clkdm",
314 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
315 },
316 {
317 .clkdm_name = "l3_init_clkdm",
318 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
319 },
320 {
321 .clkdm_name = "l4_cfg_clkdm",
322 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
323 },
324 {
325 .clkdm_name = "l4_per_clkdm",
326 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
327 },
328 {
329 .clkdm_name = "l4_secure_clkdm",
330 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
331 },
332 {
333 .clkdm_name = "l4_wkup_clkdm",
334 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
335 },
336 {
337 .clkdm_name = "tesla_clkdm",
338 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
339 },
340 { NULL },
341};
342
343static struct clkdm_dep tesla_wkup_sleep_deps[] = {
344 {
345 .clkdm_name = "abe_clkdm",
346 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
347 },
348 {
349 .clkdm_name = "ivahd_clkdm",
350 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
351 },
352 {
353 .clkdm_name = "l3_1_clkdm",
354 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
355 },
356 {
357 .clkdm_name = "l3_2_clkdm",
358 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
359 },
360 {
361 .clkdm_name = "l3_emif_clkdm",
362 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
363 },
364 {
365 .clkdm_name = "l3_init_clkdm",
366 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
367 },
368 {
369 .clkdm_name = "l4_cfg_clkdm",
370 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
371 },
372 {
373 .clkdm_name = "l4_per_clkdm",
374 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
375 },
376 {
377 .clkdm_name = "l4_wkup_clkdm",
378 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
379 },
380 { NULL },
381};
382
383static struct clockdomain l4_cefuse_44xx_clkdm = {
384 .name = "l4_cefuse_clkdm",
385 .pwrdm = { .name = "cefuse_pwrdm" },
386 .prcm_partition = OMAP4430_CM2_PARTITION,
387 .cm_inst = OMAP4430_CM2_CEFUSE_INST,
388 .clkdm_offs = OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS,
389 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
390 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
391};
392
393static struct clockdomain l4_cfg_44xx_clkdm = {
394 .name = "l4_cfg_clkdm",
395 .pwrdm = { .name = "core_pwrdm" },
396 .prcm_partition = OMAP4430_CM2_PARTITION,
397 .cm_inst = OMAP4430_CM2_CORE_INST,
398 .clkdm_offs = OMAP4430_CM2_CORE_L4CFG_CDOFFS,
399 .dep_bit = OMAP4430_L4CFG_STATDEP_SHIFT,
400 .flags = CLKDM_CAN_HWSUP,
401 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
402};
403
404static struct clockdomain tesla_44xx_clkdm = {
405 .name = "tesla_clkdm",
406 .pwrdm = { .name = "tesla_pwrdm" },
407 .prcm_partition = OMAP4430_CM1_PARTITION,
408 .cm_inst = OMAP4430_CM1_TESLA_INST,
409 .clkdm_offs = OMAP4430_CM1_TESLA_TESLA_CDOFFS,
410 .dep_bit = OMAP4430_TESLA_STATDEP_SHIFT,
411 .wkdep_srcs = tesla_wkup_sleep_deps,
412 .sleepdep_srcs = tesla_wkup_sleep_deps,
413 .flags = CLKDM_CAN_HWSUP_SWSUP,
414 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
415};
416
417static struct clockdomain l3_gfx_44xx_clkdm = {
418 .name = "l3_gfx_clkdm",
419 .pwrdm = { .name = "gfx_pwrdm" },
420 .prcm_partition = OMAP4430_CM2_PARTITION,
421 .cm_inst = OMAP4430_CM2_GFX_INST,
422 .clkdm_offs = OMAP4430_CM2_GFX_GFX_CDOFFS,
423 .dep_bit = OMAP4430_GFX_STATDEP_SHIFT,
424 .wkdep_srcs = l3_gfx_wkup_sleep_deps,
425 .sleepdep_srcs = l3_gfx_wkup_sleep_deps,
426 .flags = CLKDM_CAN_HWSUP_SWSUP,
427 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
428};
429
430static struct clockdomain ivahd_44xx_clkdm = {
431 .name = "ivahd_clkdm",
432 .pwrdm = { .name = "ivahd_pwrdm" },
433 .prcm_partition = OMAP4430_CM2_PARTITION,
434 .cm_inst = OMAP4430_CM2_IVAHD_INST,
435 .clkdm_offs = OMAP4430_CM2_IVAHD_IVAHD_CDOFFS,
436 .dep_bit = OMAP4430_IVAHD_STATDEP_SHIFT,
437 .wkdep_srcs = ivahd_wkup_sleep_deps,
438 .sleepdep_srcs = ivahd_wkup_sleep_deps,
439 .flags = CLKDM_CAN_HWSUP_SWSUP,
440 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
441};
442
443static struct clockdomain l4_secure_44xx_clkdm = {
444 .name = "l4_secure_clkdm",
445 .pwrdm = { .name = "l4per_pwrdm" },
446 .prcm_partition = OMAP4430_CM2_PARTITION,
447 .cm_inst = OMAP4430_CM2_L4PER_INST,
448 .clkdm_offs = OMAP4430_CM2_L4PER_L4SEC_CDOFFS,
449 .dep_bit = OMAP4430_L4SEC_STATDEP_SHIFT,
450 .wkdep_srcs = l4_secure_wkup_sleep_deps,
451 .sleepdep_srcs = l4_secure_wkup_sleep_deps,
452 .flags = CLKDM_CAN_HWSUP_SWSUP,
453 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
454};
455
456static struct clockdomain l4_per_44xx_clkdm = {
457 .name = "l4_per_clkdm",
458 .pwrdm = { .name = "l4per_pwrdm" },
459 .prcm_partition = OMAP4430_CM2_PARTITION,
460 .cm_inst = OMAP4430_CM2_L4PER_INST,
461 .clkdm_offs = OMAP4430_CM2_L4PER_L4PER_CDOFFS,
462 .dep_bit = OMAP4430_L4PER_STATDEP_SHIFT,
463 .flags = CLKDM_CAN_HWSUP_SWSUP,
464 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
465};
466
467static struct clockdomain abe_44xx_clkdm = {
468 .name = "abe_clkdm",
469 .pwrdm = { .name = "abe_pwrdm" },
470 .prcm_partition = OMAP4430_CM1_PARTITION,
471 .cm_inst = OMAP4430_CM1_ABE_INST,
472 .clkdm_offs = OMAP4430_CM1_ABE_ABE_CDOFFS,
473 .dep_bit = OMAP4430_ABE_STATDEP_SHIFT,
474 .flags = CLKDM_CAN_HWSUP_SWSUP,
475 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
476};
477
478static struct clockdomain l3_instr_44xx_clkdm = {
479 .name = "l3_instr_clkdm",
480 .pwrdm = { .name = "core_pwrdm" },
481 .prcm_partition = OMAP4430_CM2_PARTITION,
482 .cm_inst = OMAP4430_CM2_CORE_INST,
483 .clkdm_offs = OMAP4430_CM2_CORE_L3INSTR_CDOFFS,
484 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
485};
486
487static struct clockdomain l3_init_44xx_clkdm = {
488 .name = "l3_init_clkdm",
489 .pwrdm = { .name = "l3init_pwrdm" },
490 .prcm_partition = OMAP4430_CM2_PARTITION,
491 .cm_inst = OMAP4430_CM2_L3INIT_INST,
492 .clkdm_offs = OMAP4430_CM2_L3INIT_L3INIT_CDOFFS,
493 .dep_bit = OMAP4430_L3INIT_STATDEP_SHIFT,
494 .wkdep_srcs = l3_init_wkup_sleep_deps,
495 .sleepdep_srcs = l3_init_wkup_sleep_deps,
496 .flags = CLKDM_CAN_HWSUP_SWSUP,
497 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
498};
499
500static struct clockdomain mpuss_44xx_clkdm = {
501 .name = "mpuss_clkdm",
502 .pwrdm = { .name = "mpu_pwrdm" },
503 .prcm_partition = OMAP4430_CM1_PARTITION,
504 .cm_inst = OMAP4430_CM1_MPU_INST,
505 .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
506 .wkdep_srcs = mpuss_wkup_sleep_deps,
507 .sleepdep_srcs = mpuss_wkup_sleep_deps,
508 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
510};
511
512static struct clockdomain mpu0_44xx_clkdm = {
513 .name = "mpu0_clkdm",
514 .pwrdm = { .name = "cpu0_pwrdm" },
515 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
516 .cm_inst = OMAP4430_PRCM_MPU_CPU0_INST,
517 .clkdm_offs = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
518 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
519 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
520};
521
522static struct clockdomain mpu1_44xx_clkdm = {
523 .name = "mpu1_clkdm",
524 .pwrdm = { .name = "cpu1_pwrdm" },
525 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
526 .cm_inst = OMAP4430_PRCM_MPU_CPU1_INST,
527 .clkdm_offs = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
528 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
529 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
530};
531
532static struct clockdomain l3_emif_44xx_clkdm = {
533 .name = "l3_emif_clkdm",
534 .pwrdm = { .name = "core_pwrdm" },
535 .prcm_partition = OMAP4430_CM2_PARTITION,
536 .cm_inst = OMAP4430_CM2_CORE_INST,
537 .clkdm_offs = OMAP4430_CM2_CORE_MEMIF_CDOFFS,
538 .dep_bit = OMAP4430_MEMIF_STATDEP_SHIFT,
539 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
540 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
541};
542
543static struct clockdomain l4_ao_44xx_clkdm = {
544 .name = "l4_ao_clkdm",
545 .pwrdm = { .name = "always_on_core_pwrdm" },
546 .prcm_partition = OMAP4430_CM2_PARTITION,
547 .cm_inst = OMAP4430_CM2_ALWAYS_ON_INST,
548 .clkdm_offs = OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS,
549 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
550 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
551};
552
553static struct clockdomain ducati_44xx_clkdm = {
554 .name = "ducati_clkdm",
555 .pwrdm = { .name = "core_pwrdm" },
556 .prcm_partition = OMAP4430_CM2_PARTITION,
557 .cm_inst = OMAP4430_CM2_CORE_INST,
558 .clkdm_offs = OMAP4430_CM2_CORE_DUCATI_CDOFFS,
559 .dep_bit = OMAP4430_DUCATI_STATDEP_SHIFT,
560 .wkdep_srcs = ducati_wkup_sleep_deps,
561 .sleepdep_srcs = ducati_wkup_sleep_deps,
562 .flags = CLKDM_CAN_HWSUP_SWSUP,
563 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
564};
565
566static struct clockdomain l3_2_44xx_clkdm = {
567 .name = "l3_2_clkdm",
568 .pwrdm = { .name = "core_pwrdm" },
569 .prcm_partition = OMAP4430_CM2_PARTITION,
570 .cm_inst = OMAP4430_CM2_CORE_INST,
571 .clkdm_offs = OMAP4430_CM2_CORE_L3_2_CDOFFS,
572 .dep_bit = OMAP4430_L3_2_STATDEP_SHIFT,
573 .flags = CLKDM_CAN_HWSUP,
574 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
575};
576
577static struct clockdomain l3_1_44xx_clkdm = {
578 .name = "l3_1_clkdm",
579 .pwrdm = { .name = "core_pwrdm" },
580 .prcm_partition = OMAP4430_CM2_PARTITION,
581 .cm_inst = OMAP4430_CM2_CORE_INST,
582 .clkdm_offs = OMAP4430_CM2_CORE_L3_1_CDOFFS,
583 .dep_bit = OMAP4430_L3_1_STATDEP_SHIFT,
584 .flags = CLKDM_CAN_HWSUP,
585 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
586};
587
588static struct clockdomain l3_d2d_44xx_clkdm = {
589 .name = "l3_d2d_clkdm",
590 .pwrdm = { .name = "core_pwrdm" },
591 .prcm_partition = OMAP4430_CM2_PARTITION,
592 .cm_inst = OMAP4430_CM2_CORE_INST,
593 .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
594 .wkdep_srcs = l3_d2d_wkup_sleep_deps,
595 .sleepdep_srcs = l3_d2d_wkup_sleep_deps,
596 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
597 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
598};
599
600static struct clockdomain iss_44xx_clkdm = {
601 .name = "iss_clkdm",
602 .pwrdm = { .name = "cam_pwrdm" },
603 .prcm_partition = OMAP4430_CM2_PARTITION,
604 .cm_inst = OMAP4430_CM2_CAM_INST,
605 .clkdm_offs = OMAP4430_CM2_CAM_CAM_CDOFFS,
606 .wkdep_srcs = iss_wkup_sleep_deps,
607 .sleepdep_srcs = iss_wkup_sleep_deps,
608 .flags = CLKDM_CAN_HWSUP_SWSUP,
609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
610};
611
612static struct clockdomain l3_dss_44xx_clkdm = {
613 .name = "l3_dss_clkdm",
614 .pwrdm = { .name = "dss_pwrdm" },
615 .prcm_partition = OMAP4430_CM2_PARTITION,
616 .cm_inst = OMAP4430_CM2_DSS_INST,
617 .clkdm_offs = OMAP4430_CM2_DSS_DSS_CDOFFS,
618 .dep_bit = OMAP4430_DSS_STATDEP_SHIFT,
619 .wkdep_srcs = l3_dss_wkup_sleep_deps,
620 .sleepdep_srcs = l3_dss_wkup_sleep_deps,
621 .flags = CLKDM_CAN_HWSUP_SWSUP,
622 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
623};
624
625static struct clockdomain l4_wkup_44xx_clkdm = {
626 .name = "l4_wkup_clkdm",
627 .pwrdm = { .name = "wkup_pwrdm" },
628 .prcm_partition = OMAP4430_PRM_PARTITION,
629 .cm_inst = OMAP4430_PRM_WKUP_CM_INST,
630 .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
631 .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT,
632 .flags = CLKDM_CAN_HWSUP,
633 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
634};
635
636static struct clockdomain emu_sys_44xx_clkdm = {
637 .name = "emu_sys_clkdm",
638 .pwrdm = { .name = "emu_pwrdm" },
639 .prcm_partition = OMAP4430_PRM_PARTITION,
640 .cm_inst = OMAP4430_PRM_EMU_CM_INST,
641 .clkdm_offs = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
642 .flags = CLKDM_CAN_HWSUP,
643 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
644};
645
646static struct clockdomain l3_dma_44xx_clkdm = {
647 .name = "l3_dma_clkdm",
648 .pwrdm = { .name = "core_pwrdm" },
649 .prcm_partition = OMAP4430_CM2_PARTITION,
650 .cm_inst = OMAP4430_CM2_CORE_INST,
651 .clkdm_offs = OMAP4430_CM2_CORE_SDMA_CDOFFS,
652 .wkdep_srcs = l3_dma_wkup_sleep_deps,
653 .sleepdep_srcs = l3_dma_wkup_sleep_deps,
654 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
655 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
656};
657
658static struct clockdomain *clockdomains_omap44xx[] __initdata = {
659 &l4_cefuse_44xx_clkdm,
660 &l4_cfg_44xx_clkdm,
661 &tesla_44xx_clkdm,
662 &l3_gfx_44xx_clkdm,
663 &ivahd_44xx_clkdm,
664 &l4_secure_44xx_clkdm,
665 &l4_per_44xx_clkdm,
666 &abe_44xx_clkdm,
667 &l3_instr_44xx_clkdm,
668 &l3_init_44xx_clkdm,
669 &mpuss_44xx_clkdm,
670 &mpu0_44xx_clkdm,
671 &mpu1_44xx_clkdm,
672 &l3_emif_44xx_clkdm,
673 &l4_ao_44xx_clkdm,
674 &ducati_44xx_clkdm,
675 &l3_2_44xx_clkdm,
676 &l3_1_44xx_clkdm,
677 &l3_d2d_44xx_clkdm,
678 &iss_44xx_clkdm,
679 &l3_dss_44xx_clkdm,
680 &l4_wkup_44xx_clkdm,
681 &emu_sys_44xx_clkdm,
682 &l3_dma_44xx_clkdm,
683 NULL,
684};
685
686void __init omap44xx_clockdomains_init(void)
687{
688 clkdm_init(clockdomains_omap44xx, NULL, &omap4_clkdm_operations);
689}
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-12 16:30:50 -0400