aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-omap2/clock44xx_data.c
diff options
context:
space:
mode:
authorAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
committerAndrea Bastoni <bastoni@cs.unc.edu>2010-05-30 19:16:45 -0400
commitada47b5fe13d89735805b566185f4885f5a3f750 (patch)
tree644b88f8a71896307d71438e9b3af49126ffb22b /arch/arm/mach-omap2/clock44xx_data.c
parent43e98717ad40a4ae64545b5ba047c7b86aa44f4f (diff)
parent3280f21d43ee541f97f8cda5792150d2dbec20d5 (diff)
Merge branch 'wip-2.6.34' into old-private-masterarchived-private-master
Diffstat (limited to 'arch/arm/mach-omap2/clock44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c2718
1 files changed, 2718 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
new file mode 100644
index 000000000000..a5c0c9c8e496
--- /dev/null
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -0,0 +1,2718 @@
1/*
2 * OMAP4 Clock data
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#include <linux/kernel.h>
23#include <linux/list.h>
24#include <linux/clk.h>
25
26#include <plat/control.h>
27#include <plat/clkdev_omap.h>
28
29#include "clock.h"
30#include "clock44xx.h"
31#include "cm.h"
32#include "cm-regbits-44xx.h"
33#include "prm.h"
34#include "prm-regbits-44xx.h"
35
36/* Root clocks */
37
38static struct clk extalt_clkin_ck = {
39 .name = "extalt_clkin_ck",
40 .rate = 59000000,
41 .ops = &clkops_null,
42};
43
44static struct clk pad_clks_ck = {
45 .name = "pad_clks_ck",
46 .rate = 12000000,
47 .ops = &clkops_null,
48};
49
50static struct clk pad_slimbus_core_clks_ck = {
51 .name = "pad_slimbus_core_clks_ck",
52 .rate = 12000000,
53 .ops = &clkops_null,
54};
55
56static struct clk secure_32k_clk_src_ck = {
57 .name = "secure_32k_clk_src_ck",
58 .rate = 32768,
59 .ops = &clkops_null,
60};
61
62static struct clk slimbus_clk = {
63 .name = "slimbus_clk",
64 .rate = 12000000,
65 .ops = &clkops_null,
66};
67
68static struct clk sys_32k_ck = {
69 .name = "sys_32k_ck",
70 .rate = 32768,
71 .ops = &clkops_null,
72};
73
74static struct clk virt_12000000_ck = {
75 .name = "virt_12000000_ck",
76 .ops = &clkops_null,
77 .rate = 12000000,
78};
79
80static struct clk virt_13000000_ck = {
81 .name = "virt_13000000_ck",
82 .ops = &clkops_null,
83 .rate = 13000000,
84};
85
86static struct clk virt_16800000_ck = {
87 .name = "virt_16800000_ck",
88 .ops = &clkops_null,
89 .rate = 16800000,
90};
91
92static struct clk virt_19200000_ck = {
93 .name = "virt_19200000_ck",
94 .ops = &clkops_null,
95 .rate = 19200000,
96};
97
98static struct clk virt_26000000_ck = {
99 .name = "virt_26000000_ck",
100 .ops = &clkops_null,
101 .rate = 26000000,
102};
103
104static struct clk virt_27000000_ck = {
105 .name = "virt_27000000_ck",
106 .ops = &clkops_null,
107 .rate = 27000000,
108};
109
110static struct clk virt_38400000_ck = {
111 .name = "virt_38400000_ck",
112 .ops = &clkops_null,
113 .rate = 38400000,
114};
115
116static const struct clksel_rate div_1_0_rates[] = {
117 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
118 { .div = 0 },
119};
120
121static const struct clksel_rate div_1_1_rates[] = {
122 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
123 { .div = 0 },
124};
125
126static const struct clksel_rate div_1_2_rates[] = {
127 { .div = 1, .val = 2, .flags = RATE_IN_4430 },
128 { .div = 0 },
129};
130
131static const struct clksel_rate div_1_3_rates[] = {
132 { .div = 1, .val = 3, .flags = RATE_IN_4430 },
133 { .div = 0 },
134};
135
136static const struct clksel_rate div_1_4_rates[] = {
137 { .div = 1, .val = 4, .flags = RATE_IN_4430 },
138 { .div = 0 },
139};
140
141static const struct clksel_rate div_1_5_rates[] = {
142 { .div = 1, .val = 5, .flags = RATE_IN_4430 },
143 { .div = 0 },
144};
145
146static const struct clksel_rate div_1_6_rates[] = {
147 { .div = 1, .val = 6, .flags = RATE_IN_4430 },
148 { .div = 0 },
149};
150
151static const struct clksel_rate div_1_7_rates[] = {
152 { .div = 1, .val = 7, .flags = RATE_IN_4430 },
153 { .div = 0 },
154};
155
156static const struct clksel sys_clkin_sel[] = {
157 { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
158 { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
159 { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
160 { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
161 { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
162 { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
163 { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
164 { .parent = NULL },
165};
166
167static struct clk sys_clkin_ck = {
168 .name = "sys_clkin_ck",
169 .rate = 38400000,
170 .clksel = sys_clkin_sel,
171 .init = &omap2_init_clksel_parent,
172 .clksel_reg = OMAP4430_CM_SYS_CLKSEL,
173 .clksel_mask = OMAP4430_SYS_CLKSEL_MASK,
174 .ops = &clkops_null,
175 .recalc = &omap2_clksel_recalc,
176};
177
178static struct clk utmi_phy_clkout_ck = {
179 .name = "utmi_phy_clkout_ck",
180 .rate = 12000000,
181 .ops = &clkops_null,
182};
183
184static struct clk xclk60mhsp1_ck = {
185 .name = "xclk60mhsp1_ck",
186 .rate = 12000000,
187 .ops = &clkops_null,
188};
189
190static struct clk xclk60mhsp2_ck = {
191 .name = "xclk60mhsp2_ck",
192 .rate = 12000000,
193 .ops = &clkops_null,
194};
195
196static struct clk xclk60motg_ck = {
197 .name = "xclk60motg_ck",
198 .rate = 60000000,
199 .ops = &clkops_null,
200};
201
202/* Module clocks and DPLL outputs */
203
204static const struct clksel_rate div2_1to2_rates[] = {
205 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
206 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
207 { .div = 0 },
208};
209
210static const struct clksel dpll_sys_ref_clk_div[] = {
211 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
212 { .parent = NULL },
213};
214
215static struct clk dpll_sys_ref_clk = {
216 .name = "dpll_sys_ref_clk",
217 .parent = &sys_clkin_ck,
218 .clksel = dpll_sys_ref_clk_div,
219 .clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
220 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
221 .ops = &clkops_null,
222 .recalc = &omap2_clksel_recalc,
223 .round_rate = &omap2_clksel_round_rate,
224 .set_rate = &omap2_clksel_set_rate,
225};
226
227static const struct clksel abe_dpll_refclk_mux_sel[] = {
228 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
229 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
230 { .parent = NULL },
231};
232
233static struct clk abe_dpll_refclk_mux_ck = {
234 .name = "abe_dpll_refclk_mux_ck",
235 .parent = &dpll_sys_ref_clk,
236 .clksel = abe_dpll_refclk_mux_sel,
237 .init = &omap2_init_clksel_parent,
238 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
239 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
240 .ops = &clkops_null,
241 .recalc = &omap2_clksel_recalc,
242};
243
244/* DPLL_ABE */
245static struct dpll_data dpll_abe_dd = {
246 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
247 .clk_bypass = &sys_clkin_ck,
248 .clk_ref = &abe_dpll_refclk_mux_ck,
249 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
250 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
251 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
252 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
253 .mult_mask = OMAP4430_DPLL_MULT_MASK,
254 .div1_mask = OMAP4430_DPLL_DIV_MASK,
255 .enable_mask = OMAP4430_DPLL_EN_MASK,
256 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
257 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
258 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
259 .max_divider = OMAP4430_MAX_DPLL_DIV,
260 .min_divider = 1,
261};
262
263
264static struct clk dpll_abe_ck = {
265 .name = "dpll_abe_ck",
266 .parent = &abe_dpll_refclk_mux_ck,
267 .dpll_data = &dpll_abe_dd,
268 .init = &omap2_init_dpll_parent,
269 .ops = &clkops_omap3_noncore_dpll_ops,
270 .recalc = &omap3_dpll_recalc,
271 .round_rate = &omap2_dpll_round_rate,
272 .set_rate = &omap3_noncore_dpll_set_rate,
273};
274
275static struct clk dpll_abe_m2x2_ck = {
276 .name = "dpll_abe_m2x2_ck",
277 .parent = &dpll_abe_ck,
278 .ops = &clkops_null,
279 .recalc = &followparent_recalc,
280};
281
282static struct clk abe_24m_fclk = {
283 .name = "abe_24m_fclk",
284 .parent = &dpll_abe_m2x2_ck,
285 .ops = &clkops_null,
286 .recalc = &followparent_recalc,
287};
288
289static const struct clksel_rate div3_1to4_rates[] = {
290 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
291 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
292 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
293 { .div = 0 },
294};
295
296static const struct clksel abe_clk_div[] = {
297 { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
298 { .parent = NULL },
299};
300
301static struct clk abe_clk = {
302 .name = "abe_clk",
303 .parent = &dpll_abe_m2x2_ck,
304 .clksel = abe_clk_div,
305 .clksel_reg = OMAP4430_CM_CLKSEL_ABE,
306 .clksel_mask = OMAP4430_CLKSEL_OPP_MASK,
307 .ops = &clkops_null,
308 .recalc = &omap2_clksel_recalc,
309 .round_rate = &omap2_clksel_round_rate,
310 .set_rate = &omap2_clksel_set_rate,
311};
312
313static const struct clksel aess_fclk_div[] = {
314 { .parent = &abe_clk, .rates = div2_1to2_rates },
315 { .parent = NULL },
316};
317
318static struct clk aess_fclk = {
319 .name = "aess_fclk",
320 .parent = &abe_clk,
321 .clksel = aess_fclk_div,
322 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
323 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
324 .ops = &clkops_null,
325 .recalc = &omap2_clksel_recalc,
326 .round_rate = &omap2_clksel_round_rate,
327 .set_rate = &omap2_clksel_set_rate,
328};
329
330static const struct clksel_rate div31_1to31_rates[] = {
331 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
332 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
333 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
334 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
335 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
336 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
337 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
338 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
339 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
340 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
341 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
342 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
343 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
344 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
345 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
346 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
347 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
348 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
349 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
350 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
351 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
352 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
353 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
354 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
355 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
356 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
357 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
358 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
359 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
360 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
361 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
362 { .div = 0 },
363};
364
365static const struct clksel dpll_abe_m3_div[] = {
366 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
367 { .parent = NULL },
368};
369
370static struct clk dpll_abe_m3_ck = {
371 .name = "dpll_abe_m3_ck",
372 .parent = &dpll_abe_ck,
373 .clksel = dpll_abe_m3_div,
374 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
375 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
376 .ops = &clkops_null,
377 .recalc = &omap2_clksel_recalc,
378 .round_rate = &omap2_clksel_round_rate,
379 .set_rate = &omap2_clksel_set_rate,
380};
381
382static const struct clksel core_hsd_byp_clk_mux_sel[] = {
383 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
384 { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
385 { .parent = NULL },
386};
387
388static struct clk core_hsd_byp_clk_mux_ck = {
389 .name = "core_hsd_byp_clk_mux_ck",
390 .parent = &dpll_sys_ref_clk,
391 .clksel = core_hsd_byp_clk_mux_sel,
392 .init = &omap2_init_clksel_parent,
393 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
394 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
395 .ops = &clkops_null,
396 .recalc = &omap2_clksel_recalc,
397};
398
399/* DPLL_CORE */
400static struct dpll_data dpll_core_dd = {
401 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
402 .clk_bypass = &core_hsd_byp_clk_mux_ck,
403 .clk_ref = &dpll_sys_ref_clk,
404 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
405 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
406 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
407 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
408 .mult_mask = OMAP4430_DPLL_MULT_MASK,
409 .div1_mask = OMAP4430_DPLL_DIV_MASK,
410 .enable_mask = OMAP4430_DPLL_EN_MASK,
411 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
412 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
413 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
414 .max_divider = OMAP4430_MAX_DPLL_DIV,
415 .min_divider = 1,
416};
417
418
419static struct clk dpll_core_ck = {
420 .name = "dpll_core_ck",
421 .parent = &dpll_sys_ref_clk,
422 .dpll_data = &dpll_core_dd,
423 .init = &omap2_init_dpll_parent,
424 .ops = &clkops_null,
425 .recalc = &omap3_dpll_recalc,
426};
427
428static const struct clksel dpll_core_m6_div[] = {
429 { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
430 { .parent = NULL },
431};
432
433static struct clk dpll_core_m6_ck = {
434 .name = "dpll_core_m6_ck",
435 .parent = &dpll_core_ck,
436 .clksel = dpll_core_m6_div,
437 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
438 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
439 .ops = &clkops_null,
440 .recalc = &omap2_clksel_recalc,
441 .round_rate = &omap2_clksel_round_rate,
442 .set_rate = &omap2_clksel_set_rate,
443};
444
445static const struct clksel dbgclk_mux_sel[] = {
446 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
447 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
448 { .parent = NULL },
449};
450
451static struct clk dbgclk_mux_ck = {
452 .name = "dbgclk_mux_ck",
453 .parent = &sys_clkin_ck,
454 .ops = &clkops_null,
455 .recalc = &followparent_recalc,
456};
457
458static struct clk dpll_core_m2_ck = {
459 .name = "dpll_core_m2_ck",
460 .parent = &dpll_core_ck,
461 .clksel = dpll_core_m6_div,
462 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
463 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
464 .ops = &clkops_null,
465 .recalc = &omap2_clksel_recalc,
466 .round_rate = &omap2_clksel_round_rate,
467 .set_rate = &omap2_clksel_set_rate,
468};
469
470static struct clk ddrphy_ck = {
471 .name = "ddrphy_ck",
472 .parent = &dpll_core_m2_ck,
473 .ops = &clkops_null,
474 .recalc = &followparent_recalc,
475};
476
477static struct clk dpll_core_m5_ck = {
478 .name = "dpll_core_m5_ck",
479 .parent = &dpll_core_ck,
480 .clksel = dpll_core_m6_div,
481 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
482 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
483 .ops = &clkops_null,
484 .recalc = &omap2_clksel_recalc,
485 .round_rate = &omap2_clksel_round_rate,
486 .set_rate = &omap2_clksel_set_rate,
487};
488
489static const struct clksel div_core_div[] = {
490 { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
491 { .parent = NULL },
492};
493
494static struct clk div_core_ck = {
495 .name = "div_core_ck",
496 .parent = &dpll_core_m5_ck,
497 .clksel = div_core_div,
498 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
499 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
500 .ops = &clkops_null,
501 .recalc = &omap2_clksel_recalc,
502 .round_rate = &omap2_clksel_round_rate,
503 .set_rate = &omap2_clksel_set_rate,
504};
505
506static const struct clksel_rate div4_1to8_rates[] = {
507 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
508 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
509 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
510 { .div = 8, .val = 3, .flags = RATE_IN_4430 },
511 { .div = 0 },
512};
513
514static const struct clksel div_iva_hs_clk_div[] = {
515 { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
516 { .parent = NULL },
517};
518
519static struct clk div_iva_hs_clk = {
520 .name = "div_iva_hs_clk",
521 .parent = &dpll_core_m5_ck,
522 .clksel = div_iva_hs_clk_div,
523 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
524 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
525 .ops = &clkops_null,
526 .recalc = &omap2_clksel_recalc,
527 .round_rate = &omap2_clksel_round_rate,
528 .set_rate = &omap2_clksel_set_rate,
529};
530
531static struct clk div_mpu_hs_clk = {
532 .name = "div_mpu_hs_clk",
533 .parent = &dpll_core_m5_ck,
534 .clksel = div_iva_hs_clk_div,
535 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
536 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
537 .ops = &clkops_null,
538 .recalc = &omap2_clksel_recalc,
539 .round_rate = &omap2_clksel_round_rate,
540 .set_rate = &omap2_clksel_set_rate,
541};
542
543static struct clk dpll_core_m4_ck = {
544 .name = "dpll_core_m4_ck",
545 .parent = &dpll_core_ck,
546 .clksel = dpll_core_m6_div,
547 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
548 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
549 .ops = &clkops_null,
550 .recalc = &omap2_clksel_recalc,
551 .round_rate = &omap2_clksel_round_rate,
552 .set_rate = &omap2_clksel_set_rate,
553};
554
555static struct clk dll_clk_div_ck = {
556 .name = "dll_clk_div_ck",
557 .parent = &dpll_core_m4_ck,
558 .ops = &clkops_null,
559 .recalc = &followparent_recalc,
560};
561
562static struct clk dpll_abe_m2_ck = {
563 .name = "dpll_abe_m2_ck",
564 .parent = &dpll_abe_ck,
565 .clksel = dpll_abe_m3_div,
566 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
567 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
568 .ops = &clkops_null,
569 .recalc = &omap2_clksel_recalc,
570 .round_rate = &omap2_clksel_round_rate,
571 .set_rate = &omap2_clksel_set_rate,
572};
573
574static struct clk dpll_core_m3_ck = {
575 .name = "dpll_core_m3_ck",
576 .parent = &dpll_core_ck,
577 .clksel = dpll_core_m6_div,
578 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
579 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
580 .ops = &clkops_null,
581 .recalc = &omap2_clksel_recalc,
582 .round_rate = &omap2_clksel_round_rate,
583 .set_rate = &omap2_clksel_set_rate,
584};
585
586static struct clk dpll_core_m7_ck = {
587 .name = "dpll_core_m7_ck",
588 .parent = &dpll_core_ck,
589 .clksel = dpll_core_m6_div,
590 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
591 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
592 .ops = &clkops_null,
593 .recalc = &omap2_clksel_recalc,
594 .round_rate = &omap2_clksel_round_rate,
595 .set_rate = &omap2_clksel_set_rate,
596};
597
598static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
599 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
600 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
601 { .parent = NULL },
602};
603
604static struct clk iva_hsd_byp_clk_mux_ck = {
605 .name = "iva_hsd_byp_clk_mux_ck",
606 .parent = &dpll_sys_ref_clk,
607 .ops = &clkops_null,
608 .recalc = &followparent_recalc,
609};
610
611/* DPLL_IVA */
612static struct dpll_data dpll_iva_dd = {
613 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
614 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
615 .clk_ref = &dpll_sys_ref_clk,
616 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
617 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
618 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
619 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
620 .mult_mask = OMAP4430_DPLL_MULT_MASK,
621 .div1_mask = OMAP4430_DPLL_DIV_MASK,
622 .enable_mask = OMAP4430_DPLL_EN_MASK,
623 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
624 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
625 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
626 .max_divider = OMAP4430_MAX_DPLL_DIV,
627 .min_divider = 1,
628};
629
630
631static struct clk dpll_iva_ck = {
632 .name = "dpll_iva_ck",
633 .parent = &dpll_sys_ref_clk,
634 .dpll_data = &dpll_iva_dd,
635 .init = &omap2_init_dpll_parent,
636 .ops = &clkops_omap3_noncore_dpll_ops,
637 .recalc = &omap3_dpll_recalc,
638 .round_rate = &omap2_dpll_round_rate,
639 .set_rate = &omap3_noncore_dpll_set_rate,
640};
641
642static const struct clksel dpll_iva_m4_div[] = {
643 { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
644 { .parent = NULL },
645};
646
647static struct clk dpll_iva_m4_ck = {
648 .name = "dpll_iva_m4_ck",
649 .parent = &dpll_iva_ck,
650 .clksel = dpll_iva_m4_div,
651 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
652 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
653 .ops = &clkops_null,
654 .recalc = &omap2_clksel_recalc,
655 .round_rate = &omap2_clksel_round_rate,
656 .set_rate = &omap2_clksel_set_rate,
657};
658
659static struct clk dpll_iva_m5_ck = {
660 .name = "dpll_iva_m5_ck",
661 .parent = &dpll_iva_ck,
662 .clksel = dpll_iva_m4_div,
663 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
664 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
665 .ops = &clkops_null,
666 .recalc = &omap2_clksel_recalc,
667 .round_rate = &omap2_clksel_round_rate,
668 .set_rate = &omap2_clksel_set_rate,
669};
670
671/* DPLL_MPU */
672static struct dpll_data dpll_mpu_dd = {
673 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
674 .clk_bypass = &div_mpu_hs_clk,
675 .clk_ref = &dpll_sys_ref_clk,
676 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
677 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
678 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
679 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
680 .mult_mask = OMAP4430_DPLL_MULT_MASK,
681 .div1_mask = OMAP4430_DPLL_DIV_MASK,
682 .enable_mask = OMAP4430_DPLL_EN_MASK,
683 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
684 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
685 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
686 .max_divider = OMAP4430_MAX_DPLL_DIV,
687 .min_divider = 1,
688};
689
690
691static struct clk dpll_mpu_ck = {
692 .name = "dpll_mpu_ck",
693 .parent = &dpll_sys_ref_clk,
694 .dpll_data = &dpll_mpu_dd,
695 .init = &omap2_init_dpll_parent,
696 .ops = &clkops_omap3_noncore_dpll_ops,
697 .recalc = &omap3_dpll_recalc,
698 .round_rate = &omap2_dpll_round_rate,
699 .set_rate = &omap3_noncore_dpll_set_rate,
700};
701
702static const struct clksel dpll_mpu_m2_div[] = {
703 { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
704 { .parent = NULL },
705};
706
707static struct clk dpll_mpu_m2_ck = {
708 .name = "dpll_mpu_m2_ck",
709 .parent = &dpll_mpu_ck,
710 .clksel = dpll_mpu_m2_div,
711 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
712 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
713 .ops = &clkops_null,
714 .recalc = &omap2_clksel_recalc,
715 .round_rate = &omap2_clksel_round_rate,
716 .set_rate = &omap2_clksel_set_rate,
717};
718
719static struct clk per_hs_clk_div_ck = {
720 .name = "per_hs_clk_div_ck",
721 .parent = &dpll_abe_m3_ck,
722 .ops = &clkops_null,
723 .recalc = &followparent_recalc,
724};
725
726static const struct clksel per_hsd_byp_clk_mux_sel[] = {
727 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
728 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
729 { .parent = NULL },
730};
731
732static struct clk per_hsd_byp_clk_mux_ck = {
733 .name = "per_hsd_byp_clk_mux_ck",
734 .parent = &dpll_sys_ref_clk,
735 .clksel = per_hsd_byp_clk_mux_sel,
736 .init = &omap2_init_clksel_parent,
737 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
738 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
739 .ops = &clkops_null,
740 .recalc = &omap2_clksel_recalc,
741};
742
743/* DPLL_PER */
744static struct dpll_data dpll_per_dd = {
745 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
746 .clk_bypass = &per_hsd_byp_clk_mux_ck,
747 .clk_ref = &dpll_sys_ref_clk,
748 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
749 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
750 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
751 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
752 .mult_mask = OMAP4430_DPLL_MULT_MASK,
753 .div1_mask = OMAP4430_DPLL_DIV_MASK,
754 .enable_mask = OMAP4430_DPLL_EN_MASK,
755 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
756 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
757 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
758 .max_divider = OMAP4430_MAX_DPLL_DIV,
759 .min_divider = 1,
760};
761
762
763static struct clk dpll_per_ck = {
764 .name = "dpll_per_ck",
765 .parent = &dpll_sys_ref_clk,
766 .dpll_data = &dpll_per_dd,
767 .init = &omap2_init_dpll_parent,
768 .ops = &clkops_omap3_noncore_dpll_ops,
769 .recalc = &omap3_dpll_recalc,
770 .round_rate = &omap2_dpll_round_rate,
771 .set_rate = &omap3_noncore_dpll_set_rate,
772};
773
774static const struct clksel dpll_per_m2_div[] = {
775 { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
776 { .parent = NULL },
777};
778
779static struct clk dpll_per_m2_ck = {
780 .name = "dpll_per_m2_ck",
781 .parent = &dpll_per_ck,
782 .clksel = dpll_per_m2_div,
783 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
784 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
785 .ops = &clkops_null,
786 .recalc = &omap2_clksel_recalc,
787 .round_rate = &omap2_clksel_round_rate,
788 .set_rate = &omap2_clksel_set_rate,
789};
790
791static struct clk dpll_per_m2x2_ck = {
792 .name = "dpll_per_m2x2_ck",
793 .parent = &dpll_per_ck,
794 .ops = &clkops_null,
795 .recalc = &followparent_recalc,
796};
797
798static struct clk dpll_per_m3_ck = {
799 .name = "dpll_per_m3_ck",
800 .parent = &dpll_per_ck,
801 .clksel = dpll_per_m2_div,
802 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
803 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
804 .ops = &clkops_null,
805 .recalc = &omap2_clksel_recalc,
806 .round_rate = &omap2_clksel_round_rate,
807 .set_rate = &omap2_clksel_set_rate,
808};
809
810static struct clk dpll_per_m4_ck = {
811 .name = "dpll_per_m4_ck",
812 .parent = &dpll_per_ck,
813 .clksel = dpll_per_m2_div,
814 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
815 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
816 .ops = &clkops_null,
817 .recalc = &omap2_clksel_recalc,
818 .round_rate = &omap2_clksel_round_rate,
819 .set_rate = &omap2_clksel_set_rate,
820};
821
822static struct clk dpll_per_m5_ck = {
823 .name = "dpll_per_m5_ck",
824 .parent = &dpll_per_ck,
825 .clksel = dpll_per_m2_div,
826 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
827 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
828 .ops = &clkops_null,
829 .recalc = &omap2_clksel_recalc,
830 .round_rate = &omap2_clksel_round_rate,
831 .set_rate = &omap2_clksel_set_rate,
832};
833
834static struct clk dpll_per_m6_ck = {
835 .name = "dpll_per_m6_ck",
836 .parent = &dpll_per_ck,
837 .clksel = dpll_per_m2_div,
838 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
839 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
840 .ops = &clkops_null,
841 .recalc = &omap2_clksel_recalc,
842 .round_rate = &omap2_clksel_round_rate,
843 .set_rate = &omap2_clksel_set_rate,
844};
845
846static struct clk dpll_per_m7_ck = {
847 .name = "dpll_per_m7_ck",
848 .parent = &dpll_per_ck,
849 .clksel = dpll_per_m2_div,
850 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
851 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
852 .ops = &clkops_null,
853 .recalc = &omap2_clksel_recalc,
854 .round_rate = &omap2_clksel_round_rate,
855 .set_rate = &omap2_clksel_set_rate,
856};
857
858/* DPLL_UNIPRO */
859static struct dpll_data dpll_unipro_dd = {
860 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
861 .clk_bypass = &dpll_sys_ref_clk,
862 .clk_ref = &dpll_sys_ref_clk,
863 .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
864 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
865 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
866 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
867 .mult_mask = OMAP4430_DPLL_MULT_MASK,
868 .div1_mask = OMAP4430_DPLL_DIV_MASK,
869 .enable_mask = OMAP4430_DPLL_EN_MASK,
870 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
871 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
872 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
873 .max_divider = OMAP4430_MAX_DPLL_DIV,
874 .min_divider = 1,
875};
876
877
878static struct clk dpll_unipro_ck = {
879 .name = "dpll_unipro_ck",
880 .parent = &dpll_sys_ref_clk,
881 .dpll_data = &dpll_unipro_dd,
882 .init = &omap2_init_dpll_parent,
883 .ops = &clkops_omap3_noncore_dpll_ops,
884 .recalc = &omap3_dpll_recalc,
885 .round_rate = &omap2_dpll_round_rate,
886 .set_rate = &omap3_noncore_dpll_set_rate,
887};
888
889static const struct clksel dpll_unipro_m2x2_div[] = {
890 { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
891 { .parent = NULL },
892};
893
894static struct clk dpll_unipro_m2x2_ck = {
895 .name = "dpll_unipro_m2x2_ck",
896 .parent = &dpll_unipro_ck,
897 .clksel = dpll_unipro_m2x2_div,
898 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
899 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
900 .ops = &clkops_null,
901 .recalc = &omap2_clksel_recalc,
902 .round_rate = &omap2_clksel_round_rate,
903 .set_rate = &omap2_clksel_set_rate,
904};
905
906static struct clk usb_hs_clk_div_ck = {
907 .name = "usb_hs_clk_div_ck",
908 .parent = &dpll_abe_m3_ck,
909 .ops = &clkops_null,
910 .recalc = &followparent_recalc,
911};
912
913/* DPLL_USB */
914static struct dpll_data dpll_usb_dd = {
915 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
916 .clk_bypass = &usb_hs_clk_div_ck,
917 .clk_ref = &dpll_sys_ref_clk,
918 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
919 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
920 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
921 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
922 .mult_mask = OMAP4430_DPLL_MULT_MASK,
923 .div1_mask = OMAP4430_DPLL_DIV_MASK,
924 .enable_mask = OMAP4430_DPLL_EN_MASK,
925 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
926 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
927 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
928 .max_divider = OMAP4430_MAX_DPLL_DIV,
929 .min_divider = 1,
930 .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL
931};
932
933
934static struct clk dpll_usb_ck = {
935 .name = "dpll_usb_ck",
936 .parent = &dpll_sys_ref_clk,
937 .dpll_data = &dpll_usb_dd,
938 .init = &omap2_init_dpll_parent,
939 .ops = &clkops_omap3_noncore_dpll_ops,
940 .recalc = &omap3_dpll_recalc,
941 .round_rate = &omap2_dpll_round_rate,
942 .set_rate = &omap3_noncore_dpll_set_rate,
943};
944
945static struct clk dpll_usb_clkdcoldo_ck = {
946 .name = "dpll_usb_clkdcoldo_ck",
947 .parent = &dpll_usb_ck,
948 .ops = &clkops_null,
949 .recalc = &followparent_recalc,
950};
951
952static const struct clksel dpll_usb_m2_div[] = {
953 { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
954 { .parent = NULL },
955};
956
957static struct clk dpll_usb_m2_ck = {
958 .name = "dpll_usb_m2_ck",
959 .parent = &dpll_usb_ck,
960 .clksel = dpll_usb_m2_div,
961 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
962 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
963 .ops = &clkops_null,
964 .recalc = &omap2_clksel_recalc,
965 .round_rate = &omap2_clksel_round_rate,
966 .set_rate = &omap2_clksel_set_rate,
967};
968
969static const struct clksel ducati_clk_mux_sel[] = {
970 { .parent = &div_core_ck, .rates = div_1_0_rates },
971 { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
972 { .parent = NULL },
973};
974
975static struct clk ducati_clk_mux_ck = {
976 .name = "ducati_clk_mux_ck",
977 .parent = &div_core_ck,
978 .clksel = ducati_clk_mux_sel,
979 .init = &omap2_init_clksel_parent,
980 .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
981 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
982 .ops = &clkops_null,
983 .recalc = &omap2_clksel_recalc,
984};
985
986static struct clk func_12m_fclk = {
987 .name = "func_12m_fclk",
988 .parent = &dpll_per_m2x2_ck,
989 .ops = &clkops_null,
990 .recalc = &followparent_recalc,
991};
992
993static struct clk func_24m_clk = {
994 .name = "func_24m_clk",
995 .parent = &dpll_per_m2_ck,
996 .ops = &clkops_null,
997 .recalc = &followparent_recalc,
998};
999
1000static struct clk func_24mc_fclk = {
1001 .name = "func_24mc_fclk",
1002 .parent = &dpll_per_m2x2_ck,
1003 .ops = &clkops_null,
1004 .recalc = &followparent_recalc,
1005};
1006
1007static const struct clksel_rate div2_4to8_rates[] = {
1008 { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1009 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1010 { .div = 0 },
1011};
1012
1013static const struct clksel func_48m_fclk_div[] = {
1014 { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1015 { .parent = NULL },
1016};
1017
1018static struct clk func_48m_fclk = {
1019 .name = "func_48m_fclk",
1020 .parent = &dpll_per_m2x2_ck,
1021 .clksel = func_48m_fclk_div,
1022 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1023 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1024 .ops = &clkops_null,
1025 .recalc = &omap2_clksel_recalc,
1026 .round_rate = &omap2_clksel_round_rate,
1027 .set_rate = &omap2_clksel_set_rate,
1028};
1029
1030static struct clk func_48mc_fclk = {
1031 .name = "func_48mc_fclk",
1032 .parent = &dpll_per_m2x2_ck,
1033 .ops = &clkops_null,
1034 .recalc = &followparent_recalc,
1035};
1036
1037static const struct clksel_rate div2_2to4_rates[] = {
1038 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1039 { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1040 { .div = 0 },
1041};
1042
1043static const struct clksel func_64m_fclk_div[] = {
1044 { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
1045 { .parent = NULL },
1046};
1047
1048static struct clk func_64m_fclk = {
1049 .name = "func_64m_fclk",
1050 .parent = &dpll_per_m4_ck,
1051 .clksel = func_64m_fclk_div,
1052 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1053 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1054 .ops = &clkops_null,
1055 .recalc = &omap2_clksel_recalc,
1056 .round_rate = &omap2_clksel_round_rate,
1057 .set_rate = &omap2_clksel_set_rate,
1058};
1059
1060static const struct clksel func_96m_fclk_div[] = {
1061 { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1062 { .parent = NULL },
1063};
1064
1065static struct clk func_96m_fclk = {
1066 .name = "func_96m_fclk",
1067 .parent = &dpll_per_m2x2_ck,
1068 .clksel = func_96m_fclk_div,
1069 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1070 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1071 .ops = &clkops_null,
1072 .recalc = &omap2_clksel_recalc,
1073 .round_rate = &omap2_clksel_round_rate,
1074 .set_rate = &omap2_clksel_set_rate,
1075};
1076
1077static const struct clksel hsmmc6_fclk_sel[] = {
1078 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1079 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1080 { .parent = NULL },
1081};
1082
1083static struct clk hsmmc6_fclk = {
1084 .name = "hsmmc6_fclk",
1085 .parent = &func_64m_fclk,
1086 .ops = &clkops_null,
1087 .recalc = &followparent_recalc,
1088};
1089
1090static const struct clksel_rate div2_1to8_rates[] = {
1091 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1092 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1093 { .div = 0 },
1094};
1095
1096static const struct clksel init_60m_fclk_div[] = {
1097 { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1098 { .parent = NULL },
1099};
1100
1101static struct clk init_60m_fclk = {
1102 .name = "init_60m_fclk",
1103 .parent = &dpll_usb_m2_ck,
1104 .clksel = init_60m_fclk_div,
1105 .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ,
1106 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1107 .ops = &clkops_null,
1108 .recalc = &omap2_clksel_recalc,
1109 .round_rate = &omap2_clksel_round_rate,
1110 .set_rate = &omap2_clksel_set_rate,
1111};
1112
1113static const struct clksel l3_div_div[] = {
1114 { .parent = &div_core_ck, .rates = div2_1to2_rates },
1115 { .parent = NULL },
1116};
1117
1118static struct clk l3_div_ck = {
1119 .name = "l3_div_ck",
1120 .parent = &div_core_ck,
1121 .clksel = l3_div_div,
1122 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1123 .clksel_mask = OMAP4430_CLKSEL_L3_MASK,
1124 .ops = &clkops_null,
1125 .recalc = &omap2_clksel_recalc,
1126 .round_rate = &omap2_clksel_round_rate,
1127 .set_rate = &omap2_clksel_set_rate,
1128};
1129
1130static const struct clksel l4_div_div[] = {
1131 { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1132 { .parent = NULL },
1133};
1134
1135static struct clk l4_div_ck = {
1136 .name = "l4_div_ck",
1137 .parent = &l3_div_ck,
1138 .clksel = l4_div_div,
1139 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1140 .clksel_mask = OMAP4430_CLKSEL_L4_MASK,
1141 .ops = &clkops_null,
1142 .recalc = &omap2_clksel_recalc,
1143 .round_rate = &omap2_clksel_round_rate,
1144 .set_rate = &omap2_clksel_set_rate,
1145};
1146
1147static struct clk lp_clk_div_ck = {
1148 .name = "lp_clk_div_ck",
1149 .parent = &dpll_abe_m2x2_ck,
1150 .ops = &clkops_null,
1151 .recalc = &followparent_recalc,
1152};
1153
1154static const struct clksel l4_wkup_clk_mux_sel[] = {
1155 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1156 { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1157 { .parent = NULL },
1158};
1159
1160static struct clk l4_wkup_clk_mux_ck = {
1161 .name = "l4_wkup_clk_mux_ck",
1162 .parent = &sys_clkin_ck,
1163 .clksel = l4_wkup_clk_mux_sel,
1164 .init = &omap2_init_clksel_parent,
1165 .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL,
1166 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1167 .ops = &clkops_null,
1168 .recalc = &omap2_clksel_recalc,
1169};
1170
1171static const struct clksel per_abe_nc_fclk_div[] = {
1172 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1173 { .parent = NULL },
1174};
1175
1176static struct clk per_abe_nc_fclk = {
1177 .name = "per_abe_nc_fclk",
1178 .parent = &dpll_abe_m2_ck,
1179 .clksel = per_abe_nc_fclk_div,
1180 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1181 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1182 .ops = &clkops_null,
1183 .recalc = &omap2_clksel_recalc,
1184 .round_rate = &omap2_clksel_round_rate,
1185 .set_rate = &omap2_clksel_set_rate,
1186};
1187
1188static const struct clksel mcasp2_fclk_sel[] = {
1189 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1190 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1191 { .parent = NULL },
1192};
1193
1194static struct clk mcasp2_fclk = {
1195 .name = "mcasp2_fclk",
1196 .parent = &func_96m_fclk,
1197 .ops = &clkops_null,
1198 .recalc = &followparent_recalc,
1199};
1200
1201static struct clk mcasp3_fclk = {
1202 .name = "mcasp3_fclk",
1203 .parent = &func_96m_fclk,
1204 .ops = &clkops_null,
1205 .recalc = &followparent_recalc,
1206};
1207
1208static struct clk ocp_abe_iclk = {
1209 .name = "ocp_abe_iclk",
1210 .parent = &aess_fclk,
1211 .ops = &clkops_null,
1212 .recalc = &followparent_recalc,
1213};
1214
1215static struct clk per_abe_24m_fclk = {
1216 .name = "per_abe_24m_fclk",
1217 .parent = &dpll_abe_m2_ck,
1218 .ops = &clkops_null,
1219 .recalc = &followparent_recalc,
1220};
1221
1222static const struct clksel pmd_stm_clock_mux_sel[] = {
1223 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1224 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
1225 { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates },
1226 { .parent = NULL },
1227};
1228
1229static struct clk pmd_stm_clock_mux_ck = {
1230 .name = "pmd_stm_clock_mux_ck",
1231 .parent = &sys_clkin_ck,
1232 .ops = &clkops_null,
1233 .recalc = &followparent_recalc,
1234};
1235
1236static struct clk pmd_trace_clk_mux_ck = {
1237 .name = "pmd_trace_clk_mux_ck",
1238 .parent = &sys_clkin_ck,
1239 .ops = &clkops_null,
1240 .recalc = &followparent_recalc,
1241};
1242
1243static struct clk syc_clk_div_ck = {
1244 .name = "syc_clk_div_ck",
1245 .parent = &sys_clkin_ck,
1246 .clksel = dpll_sys_ref_clk_div,
1247 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1248 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1249 .ops = &clkops_null,
1250 .recalc = &omap2_clksel_recalc,
1251 .round_rate = &omap2_clksel_round_rate,
1252 .set_rate = &omap2_clksel_set_rate,
1253};
1254
1255/* Leaf clocks controlled by modules */
1256
1257static struct clk aes1_fck = {
1258 .name = "aes1_fck",
1259 .ops = &clkops_omap2_dflt,
1260 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1261 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1262 .clkdm_name = "l4_secure_clkdm",
1263 .parent = &l3_div_ck,
1264 .recalc = &followparent_recalc,
1265};
1266
1267static struct clk aes2_fck = {
1268 .name = "aes2_fck",
1269 .ops = &clkops_omap2_dflt,
1270 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1271 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1272 .clkdm_name = "l4_secure_clkdm",
1273 .parent = &l3_div_ck,
1274 .recalc = &followparent_recalc,
1275};
1276
1277static struct clk aess_fck = {
1278 .name = "aess_fck",
1279 .ops = &clkops_omap2_dflt,
1280 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1281 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1282 .clkdm_name = "abe_clkdm",
1283 .parent = &aess_fclk,
1284 .recalc = &followparent_recalc,
1285};
1286
1287static struct clk cust_efuse_fck = {
1288 .name = "cust_efuse_fck",
1289 .ops = &clkops_omap2_dflt,
1290 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1291 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1292 .clkdm_name = "l4_cefuse_clkdm",
1293 .parent = &sys_clkin_ck,
1294 .recalc = &followparent_recalc,
1295};
1296
1297static struct clk des3des_fck = {
1298 .name = "des3des_fck",
1299 .ops = &clkops_omap2_dflt,
1300 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1301 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1302 .clkdm_name = "l4_secure_clkdm",
1303 .parent = &l4_div_ck,
1304 .recalc = &followparent_recalc,
1305};
1306
1307static const struct clksel dmic_sync_mux_sel[] = {
1308 { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1309 { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1310 { .parent = &func_24m_clk, .rates = div_1_2_rates },
1311 { .parent = NULL },
1312};
1313
1314static struct clk dmic_sync_mux_ck = {
1315 .name = "dmic_sync_mux_ck",
1316 .parent = &abe_24m_fclk,
1317 .clksel = dmic_sync_mux_sel,
1318 .init = &omap2_init_clksel_parent,
1319 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1320 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1321 .ops = &clkops_null,
1322 .recalc = &omap2_clksel_recalc,
1323};
1324
1325static const struct clksel func_dmic_abe_gfclk_sel[] = {
1326 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1327 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1328 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1329 { .parent = NULL },
1330};
1331
1332/* Merged func_dmic_abe_gfclk into dmic */
1333static struct clk dmic_fck = {
1334 .name = "dmic_fck",
1335 .parent = &dmic_sync_mux_ck,
1336 .clksel = func_dmic_abe_gfclk_sel,
1337 .init = &omap2_init_clksel_parent,
1338 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1339 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1340 .ops = &clkops_omap2_dflt,
1341 .recalc = &omap2_clksel_recalc,
1342 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1343 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1344 .clkdm_name = "abe_clkdm",
1345};
1346
1347static struct clk dss_fck = {
1348 .name = "dss_fck",
1349 .ops = &clkops_omap2_dflt,
1350 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1351 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1352 .clkdm_name = "l3_dss_clkdm",
1353 .parent = &l3_div_ck,
1354 .recalc = &followparent_recalc,
1355};
1356
1357static struct clk ducati_ick = {
1358 .name = "ducati_ick",
1359 .ops = &clkops_omap2_dflt,
1360 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1361 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1362 .clkdm_name = "ducati_clkdm",
1363 .parent = &ducati_clk_mux_ck,
1364 .recalc = &followparent_recalc,
1365};
1366
1367static struct clk emif1_ick = {
1368 .name = "emif1_ick",
1369 .ops = &clkops_omap2_dflt,
1370 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1371 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1372 .clkdm_name = "l3_emif_clkdm",
1373 .parent = &ddrphy_ck,
1374 .recalc = &followparent_recalc,
1375};
1376
1377static struct clk emif2_ick = {
1378 .name = "emif2_ick",
1379 .ops = &clkops_omap2_dflt,
1380 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1381 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1382 .clkdm_name = "l3_emif_clkdm",
1383 .parent = &ddrphy_ck,
1384 .recalc = &followparent_recalc,
1385};
1386
1387static const struct clksel fdif_fclk_div[] = {
1388 { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
1389 { .parent = NULL },
1390};
1391
1392/* Merged fdif_fclk into fdif */
1393static struct clk fdif_fck = {
1394 .name = "fdif_fck",
1395 .parent = &dpll_per_m4_ck,
1396 .clksel = fdif_fclk_div,
1397 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1398 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
1399 .ops = &clkops_omap2_dflt,
1400 .recalc = &omap2_clksel_recalc,
1401 .round_rate = &omap2_clksel_round_rate,
1402 .set_rate = &omap2_clksel_set_rate,
1403 .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1404 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1405 .clkdm_name = "iss_clkdm",
1406};
1407
1408static const struct clksel per_sgx_fclk_div[] = {
1409 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1410 { .parent = NULL },
1411};
1412
1413static struct clk per_sgx_fclk = {
1414 .name = "per_sgx_fclk",
1415 .parent = &dpll_per_m2x2_ck,
1416 .clksel = per_sgx_fclk_div,
1417 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1418 .clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK,
1419 .ops = &clkops_null,
1420 .recalc = &omap2_clksel_recalc,
1421 .round_rate = &omap2_clksel_round_rate,
1422 .set_rate = &omap2_clksel_set_rate,
1423};
1424
1425static const struct clksel sgx_clk_mux_sel[] = {
1426 { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
1427 { .parent = &per_sgx_fclk, .rates = div_1_1_rates },
1428 { .parent = NULL },
1429};
1430
1431/* Merged sgx_clk_mux into gfx */
1432static struct clk gfx_fck = {
1433 .name = "gfx_fck",
1434 .parent = &dpll_core_m7_ck,
1435 .clksel = sgx_clk_mux_sel,
1436 .init = &omap2_init_clksel_parent,
1437 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1438 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1439 .ops = &clkops_omap2_dflt,
1440 .recalc = &omap2_clksel_recalc,
1441 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1442 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1443 .clkdm_name = "l3_gfx_clkdm",
1444};
1445
1446static struct clk gpio1_ick = {
1447 .name = "gpio1_ick",
1448 .ops = &clkops_omap2_dflt,
1449 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1450 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1451 .clkdm_name = "l4_wkup_clkdm",
1452 .parent = &l4_wkup_clk_mux_ck,
1453 .recalc = &followparent_recalc,
1454};
1455
1456static struct clk gpio2_ick = {
1457 .name = "gpio2_ick",
1458 .ops = &clkops_omap2_dflt,
1459 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1460 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1461 .clkdm_name = "l4_per_clkdm",
1462 .parent = &l4_div_ck,
1463 .recalc = &followparent_recalc,
1464};
1465
1466static struct clk gpio3_ick = {
1467 .name = "gpio3_ick",
1468 .ops = &clkops_omap2_dflt,
1469 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1470 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1471 .clkdm_name = "l4_per_clkdm",
1472 .parent = &l4_div_ck,
1473 .recalc = &followparent_recalc,
1474};
1475
1476static struct clk gpio4_ick = {
1477 .name = "gpio4_ick",
1478 .ops = &clkops_omap2_dflt,
1479 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1480 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1481 .clkdm_name = "l4_per_clkdm",
1482 .parent = &l4_div_ck,
1483 .recalc = &followparent_recalc,
1484};
1485
1486static struct clk gpio5_ick = {
1487 .name = "gpio5_ick",
1488 .ops = &clkops_omap2_dflt,
1489 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1490 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1491 .clkdm_name = "l4_per_clkdm",
1492 .parent = &l4_div_ck,
1493 .recalc = &followparent_recalc,
1494};
1495
1496static struct clk gpio6_ick = {
1497 .name = "gpio6_ick",
1498 .ops = &clkops_omap2_dflt,
1499 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1500 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1501 .clkdm_name = "l4_per_clkdm",
1502 .parent = &l4_div_ck,
1503 .recalc = &followparent_recalc,
1504};
1505
1506static struct clk gpmc_ick = {
1507 .name = "gpmc_ick",
1508 .ops = &clkops_omap2_dflt,
1509 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1510 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1511 .clkdm_name = "l3_2_clkdm",
1512 .parent = &l3_div_ck,
1513 .recalc = &followparent_recalc,
1514};
1515
1516static const struct clksel dmt1_clk_mux_sel[] = {
1517 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1518 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1519 { .parent = NULL },
1520};
1521
1522/*
1523 * Merged dmt1_clk_mux into gptimer1
1524 * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention
1525 */
1526static struct clk gpt1_fck = {
1527 .name = "gpt1_fck",
1528 .parent = &sys_clkin_ck,
1529 .clksel = dmt1_clk_mux_sel,
1530 .init = &omap2_init_clksel_parent,
1531 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1532 .clksel_mask = OMAP4430_CLKSEL_MASK,
1533 .ops = &clkops_omap2_dflt,
1534 .recalc = &omap2_clksel_recalc,
1535 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1536 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1537 .clkdm_name = "l4_wkup_clkdm",
1538};
1539
1540/*
1541 * Merged cm2_dm10_mux into gptimer10
1542 * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention
1543 */
1544static struct clk gpt10_fck = {
1545 .name = "gpt10_fck",
1546 .parent = &sys_clkin_ck,
1547 .clksel = dmt1_clk_mux_sel,
1548 .init = &omap2_init_clksel_parent,
1549 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1550 .clksel_mask = OMAP4430_CLKSEL_MASK,
1551 .ops = &clkops_omap2_dflt,
1552 .recalc = &omap2_clksel_recalc,
1553 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1554 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1555 .clkdm_name = "l4_per_clkdm",
1556};
1557
1558/*
1559 * Merged cm2_dm11_mux into gptimer11
1560 * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention
1561 */
1562static struct clk gpt11_fck = {
1563 .name = "gpt11_fck",
1564 .parent = &sys_clkin_ck,
1565 .clksel = dmt1_clk_mux_sel,
1566 .init = &omap2_init_clksel_parent,
1567 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1568 .clksel_mask = OMAP4430_CLKSEL_MASK,
1569 .ops = &clkops_omap2_dflt,
1570 .recalc = &omap2_clksel_recalc,
1571 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1572 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1573 .clkdm_name = "l4_per_clkdm",
1574};
1575
1576/*
1577 * Merged cm2_dm2_mux into gptimer2
1578 * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention
1579 */
1580static struct clk gpt2_fck = {
1581 .name = "gpt2_fck",
1582 .parent = &sys_clkin_ck,
1583 .clksel = dmt1_clk_mux_sel,
1584 .init = &omap2_init_clksel_parent,
1585 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1586 .clksel_mask = OMAP4430_CLKSEL_MASK,
1587 .ops = &clkops_omap2_dflt,
1588 .recalc = &omap2_clksel_recalc,
1589 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1590 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1591 .clkdm_name = "l4_per_clkdm",
1592};
1593
1594/*
1595 * Merged cm2_dm3_mux into gptimer3
1596 * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention
1597 */
1598static struct clk gpt3_fck = {
1599 .name = "gpt3_fck",
1600 .parent = &sys_clkin_ck,
1601 .clksel = dmt1_clk_mux_sel,
1602 .init = &omap2_init_clksel_parent,
1603 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1604 .clksel_mask = OMAP4430_CLKSEL_MASK,
1605 .ops = &clkops_omap2_dflt,
1606 .recalc = &omap2_clksel_recalc,
1607 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1608 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1609 .clkdm_name = "l4_per_clkdm",
1610};
1611
1612/*
1613 * Merged cm2_dm4_mux into gptimer4
1614 * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention
1615 */
1616static struct clk gpt4_fck = {
1617 .name = "gpt4_fck",
1618 .parent = &sys_clkin_ck,
1619 .clksel = dmt1_clk_mux_sel,
1620 .init = &omap2_init_clksel_parent,
1621 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1622 .clksel_mask = OMAP4430_CLKSEL_MASK,
1623 .ops = &clkops_omap2_dflt,
1624 .recalc = &omap2_clksel_recalc,
1625 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1626 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1627 .clkdm_name = "l4_per_clkdm",
1628};
1629
1630static const struct clksel timer5_sync_mux_sel[] = {
1631 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1632 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1633 { .parent = NULL },
1634};
1635
1636/*
1637 * Merged timer5_sync_mux into gptimer5
1638 * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention
1639 */
1640static struct clk gpt5_fck = {
1641 .name = "gpt5_fck",
1642 .parent = &syc_clk_div_ck,
1643 .clksel = timer5_sync_mux_sel,
1644 .init = &omap2_init_clksel_parent,
1645 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1646 .clksel_mask = OMAP4430_CLKSEL_MASK,
1647 .ops = &clkops_omap2_dflt,
1648 .recalc = &omap2_clksel_recalc,
1649 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1650 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1651 .clkdm_name = "abe_clkdm",
1652};
1653
1654/*
1655 * Merged timer6_sync_mux into gptimer6
1656 * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention
1657 */
1658static struct clk gpt6_fck = {
1659 .name = "gpt6_fck",
1660 .parent = &syc_clk_div_ck,
1661 .clksel = timer5_sync_mux_sel,
1662 .init = &omap2_init_clksel_parent,
1663 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1664 .clksel_mask = OMAP4430_CLKSEL_MASK,
1665 .ops = &clkops_omap2_dflt,
1666 .recalc = &omap2_clksel_recalc,
1667 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1668 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1669 .clkdm_name = "abe_clkdm",
1670};
1671
1672/*
1673 * Merged timer7_sync_mux into gptimer7
1674 * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention
1675 */
1676static struct clk gpt7_fck = {
1677 .name = "gpt7_fck",
1678 .parent = &syc_clk_div_ck,
1679 .clksel = timer5_sync_mux_sel,
1680 .init = &omap2_init_clksel_parent,
1681 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1682 .clksel_mask = OMAP4430_CLKSEL_MASK,
1683 .ops = &clkops_omap2_dflt,
1684 .recalc = &omap2_clksel_recalc,
1685 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1686 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1687 .clkdm_name = "abe_clkdm",
1688};
1689
1690/*
1691 * Merged timer8_sync_mux into gptimer8
1692 * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention
1693 */
1694static struct clk gpt8_fck = {
1695 .name = "gpt8_fck",
1696 .parent = &syc_clk_div_ck,
1697 .clksel = timer5_sync_mux_sel,
1698 .init = &omap2_init_clksel_parent,
1699 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1700 .clksel_mask = OMAP4430_CLKSEL_MASK,
1701 .ops = &clkops_omap2_dflt,
1702 .recalc = &omap2_clksel_recalc,
1703 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1704 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1705 .clkdm_name = "abe_clkdm",
1706};
1707
1708/*
1709 * Merged cm2_dm9_mux into gptimer9
1710 * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention
1711 */
1712static struct clk gpt9_fck = {
1713 .name = "gpt9_fck",
1714 .parent = &sys_clkin_ck,
1715 .clksel = dmt1_clk_mux_sel,
1716 .init = &omap2_init_clksel_parent,
1717 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1718 .clksel_mask = OMAP4430_CLKSEL_MASK,
1719 .ops = &clkops_omap2_dflt,
1720 .recalc = &omap2_clksel_recalc,
1721 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1722 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1723 .clkdm_name = "l4_per_clkdm",
1724};
1725
1726static struct clk hdq1w_fck = {
1727 .name = "hdq1w_fck",
1728 .ops = &clkops_omap2_dflt,
1729 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1730 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1731 .clkdm_name = "l4_per_clkdm",
1732 .parent = &func_12m_fclk,
1733 .recalc = &followparent_recalc,
1734};
1735
1736/* Merged hsi_fclk into hsi */
1737static struct clk hsi_ick = {
1738 .name = "hsi_ick",
1739 .parent = &dpll_per_m2x2_ck,
1740 .clksel = per_sgx_fclk_div,
1741 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1742 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1743 .ops = &clkops_omap2_dflt,
1744 .recalc = &omap2_clksel_recalc,
1745 .round_rate = &omap2_clksel_round_rate,
1746 .set_rate = &omap2_clksel_set_rate,
1747 .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1748 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1749 .clkdm_name = "l3_init_clkdm",
1750};
1751
1752static struct clk i2c1_fck = {
1753 .name = "i2c1_fck",
1754 .ops = &clkops_omap2_dflt,
1755 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1756 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1757 .clkdm_name = "l4_per_clkdm",
1758 .parent = &func_96m_fclk,
1759 .recalc = &followparent_recalc,
1760};
1761
1762static struct clk i2c2_fck = {
1763 .name = "i2c2_fck",
1764 .ops = &clkops_omap2_dflt,
1765 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1766 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1767 .clkdm_name = "l4_per_clkdm",
1768 .parent = &func_96m_fclk,
1769 .recalc = &followparent_recalc,
1770};
1771
1772static struct clk i2c3_fck = {
1773 .name = "i2c3_fck",
1774 .ops = &clkops_omap2_dflt,
1775 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1776 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1777 .clkdm_name = "l4_per_clkdm",
1778 .parent = &func_96m_fclk,
1779 .recalc = &followparent_recalc,
1780};
1781
1782static struct clk i2c4_fck = {
1783 .name = "i2c4_fck",
1784 .ops = &clkops_omap2_dflt,
1785 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1786 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1787 .clkdm_name = "l4_per_clkdm",
1788 .parent = &func_96m_fclk,
1789 .recalc = &followparent_recalc,
1790};
1791
1792static struct clk iss_fck = {
1793 .name = "iss_fck",
1794 .ops = &clkops_omap2_dflt,
1795 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1796 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1797 .clkdm_name = "iss_clkdm",
1798 .parent = &ducati_clk_mux_ck,
1799 .recalc = &followparent_recalc,
1800};
1801
1802static struct clk ivahd_ick = {
1803 .name = "ivahd_ick",
1804 .ops = &clkops_omap2_dflt,
1805 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1806 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1807 .clkdm_name = "ivahd_clkdm",
1808 .parent = &dpll_iva_m5_ck,
1809 .recalc = &followparent_recalc,
1810};
1811
1812static struct clk keyboard_fck = {
1813 .name = "keyboard_fck",
1814 .ops = &clkops_omap2_dflt,
1815 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1816 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1817 .clkdm_name = "l4_wkup_clkdm",
1818 .parent = &sys_32k_ck,
1819 .recalc = &followparent_recalc,
1820};
1821
1822static struct clk l3_instr_interconnect_ick = {
1823 .name = "l3_instr_interconnect_ick",
1824 .ops = &clkops_omap2_dflt,
1825 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1826 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1827 .clkdm_name = "l3_instr_clkdm",
1828 .parent = &l3_div_ck,
1829 .recalc = &followparent_recalc,
1830};
1831
1832static struct clk l3_interconnect_3_ick = {
1833 .name = "l3_interconnect_3_ick",
1834 .ops = &clkops_omap2_dflt,
1835 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1836 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1837 .clkdm_name = "l3_instr_clkdm",
1838 .parent = &l3_div_ck,
1839 .recalc = &followparent_recalc,
1840};
1841
1842static struct clk mcasp_sync_mux_ck = {
1843 .name = "mcasp_sync_mux_ck",
1844 .parent = &abe_24m_fclk,
1845 .clksel = dmic_sync_mux_sel,
1846 .init = &omap2_init_clksel_parent,
1847 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1848 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1849 .ops = &clkops_null,
1850 .recalc = &omap2_clksel_recalc,
1851};
1852
1853static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1854 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1855 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1856 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1857 { .parent = NULL },
1858};
1859
1860/* Merged func_mcasp_abe_gfclk into mcasp */
1861static struct clk mcasp_fck = {
1862 .name = "mcasp_fck",
1863 .parent = &mcasp_sync_mux_ck,
1864 .clksel = func_mcasp_abe_gfclk_sel,
1865 .init = &omap2_init_clksel_parent,
1866 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1867 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1868 .ops = &clkops_omap2_dflt,
1869 .recalc = &omap2_clksel_recalc,
1870 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1871 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1872 .clkdm_name = "abe_clkdm",
1873};
1874
1875static struct clk mcbsp1_sync_mux_ck = {
1876 .name = "mcbsp1_sync_mux_ck",
1877 .parent = &abe_24m_fclk,
1878 .clksel = dmic_sync_mux_sel,
1879 .init = &omap2_init_clksel_parent,
1880 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1881 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1882 .ops = &clkops_null,
1883 .recalc = &omap2_clksel_recalc,
1884};
1885
1886static const struct clksel func_mcbsp1_gfclk_sel[] = {
1887 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1888 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1889 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1890 { .parent = NULL },
1891};
1892
1893/* Merged func_mcbsp1_gfclk into mcbsp1 */
1894static struct clk mcbsp1_fck = {
1895 .name = "mcbsp1_fck",
1896 .parent = &mcbsp1_sync_mux_ck,
1897 .clksel = func_mcbsp1_gfclk_sel,
1898 .init = &omap2_init_clksel_parent,
1899 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1900 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1901 .ops = &clkops_omap2_dflt,
1902 .recalc = &omap2_clksel_recalc,
1903 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1904 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1905 .clkdm_name = "abe_clkdm",
1906};
1907
1908static struct clk mcbsp2_sync_mux_ck = {
1909 .name = "mcbsp2_sync_mux_ck",
1910 .parent = &abe_24m_fclk,
1911 .clksel = dmic_sync_mux_sel,
1912 .init = &omap2_init_clksel_parent,
1913 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1914 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1915 .ops = &clkops_null,
1916 .recalc = &omap2_clksel_recalc,
1917};
1918
1919static const struct clksel func_mcbsp2_gfclk_sel[] = {
1920 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1921 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1922 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1923 { .parent = NULL },
1924};
1925
1926/* Merged func_mcbsp2_gfclk into mcbsp2 */
1927static struct clk mcbsp2_fck = {
1928 .name = "mcbsp2_fck",
1929 .parent = &mcbsp2_sync_mux_ck,
1930 .clksel = func_mcbsp2_gfclk_sel,
1931 .init = &omap2_init_clksel_parent,
1932 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1933 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1934 .ops = &clkops_omap2_dflt,
1935 .recalc = &omap2_clksel_recalc,
1936 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1937 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1938 .clkdm_name = "abe_clkdm",
1939};
1940
1941static struct clk mcbsp3_sync_mux_ck = {
1942 .name = "mcbsp3_sync_mux_ck",
1943 .parent = &abe_24m_fclk,
1944 .clksel = dmic_sync_mux_sel,
1945 .init = &omap2_init_clksel_parent,
1946 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1947 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1948 .ops = &clkops_null,
1949 .recalc = &omap2_clksel_recalc,
1950};
1951
1952static const struct clksel func_mcbsp3_gfclk_sel[] = {
1953 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1954 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1955 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1956 { .parent = NULL },
1957};
1958
1959/* Merged func_mcbsp3_gfclk into mcbsp3 */
1960static struct clk mcbsp3_fck = {
1961 .name = "mcbsp3_fck",
1962 .parent = &mcbsp3_sync_mux_ck,
1963 .clksel = func_mcbsp3_gfclk_sel,
1964 .init = &omap2_init_clksel_parent,
1965 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1966 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1967 .ops = &clkops_omap2_dflt,
1968 .recalc = &omap2_clksel_recalc,
1969 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1970 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1971 .clkdm_name = "abe_clkdm",
1972};
1973
1974static struct clk mcbsp4_sync_mux_ck = {
1975 .name = "mcbsp4_sync_mux_ck",
1976 .parent = &func_96m_fclk,
1977 .clksel = mcasp2_fclk_sel,
1978 .init = &omap2_init_clksel_parent,
1979 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1980 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1981 .ops = &clkops_null,
1982 .recalc = &omap2_clksel_recalc,
1983};
1984
1985static const struct clksel per_mcbsp4_gfclk_sel[] = {
1986 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1987 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1988 { .parent = NULL },
1989};
1990
1991/* Merged per_mcbsp4_gfclk into mcbsp4 */
1992static struct clk mcbsp4_fck = {
1993 .name = "mcbsp4_fck",
1994 .parent = &mcbsp4_sync_mux_ck,
1995 .clksel = per_mcbsp4_gfclk_sel,
1996 .init = &omap2_init_clksel_parent,
1997 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1998 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1999 .ops = &clkops_omap2_dflt,
2000 .recalc = &omap2_clksel_recalc,
2001 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2002 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2003 .clkdm_name = "l4_per_clkdm",
2004};
2005
2006static struct clk mcspi1_fck = {
2007 .name = "mcspi1_fck",
2008 .ops = &clkops_omap2_dflt,
2009 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2010 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2011 .clkdm_name = "l4_per_clkdm",
2012 .parent = &func_48m_fclk,
2013 .recalc = &followparent_recalc,
2014};
2015
2016static struct clk mcspi2_fck = {
2017 .name = "mcspi2_fck",
2018 .ops = &clkops_omap2_dflt,
2019 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2020 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2021 .clkdm_name = "l4_per_clkdm",
2022 .parent = &func_48m_fclk,
2023 .recalc = &followparent_recalc,
2024};
2025
2026static struct clk mcspi3_fck = {
2027 .name = "mcspi3_fck",
2028 .ops = &clkops_omap2_dflt,
2029 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2030 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2031 .clkdm_name = "l4_per_clkdm",
2032 .parent = &func_48m_fclk,
2033 .recalc = &followparent_recalc,
2034};
2035
2036static struct clk mcspi4_fck = {
2037 .name = "mcspi4_fck",
2038 .ops = &clkops_omap2_dflt,
2039 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2040 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2041 .clkdm_name = "l4_per_clkdm",
2042 .parent = &func_48m_fclk,
2043 .recalc = &followparent_recalc,
2044};
2045
2046/* Merged hsmmc1_fclk into mmc1 */
2047static struct clk mmc1_fck = {
2048 .name = "mmc1_fck",
2049 .parent = &func_64m_fclk,
2050 .clksel = hsmmc6_fclk_sel,
2051 .init = &omap2_init_clksel_parent,
2052 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2053 .clksel_mask = OMAP4430_CLKSEL_MASK,
2054 .ops = &clkops_omap2_dflt,
2055 .recalc = &omap2_clksel_recalc,
2056 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2057 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2058 .clkdm_name = "l3_init_clkdm",
2059};
2060
2061/* Merged hsmmc2_fclk into mmc2 */
2062static struct clk mmc2_fck = {
2063 .name = "mmc2_fck",
2064 .parent = &func_64m_fclk,
2065 .clksel = hsmmc6_fclk_sel,
2066 .init = &omap2_init_clksel_parent,
2067 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2068 .clksel_mask = OMAP4430_CLKSEL_MASK,
2069 .ops = &clkops_omap2_dflt,
2070 .recalc = &omap2_clksel_recalc,
2071 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2072 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2073 .clkdm_name = "l3_init_clkdm",
2074};
2075
2076static struct clk mmc3_fck = {
2077 .name = "mmc3_fck",
2078 .ops = &clkops_omap2_dflt,
2079 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2080 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2081 .clkdm_name = "l4_per_clkdm",
2082 .parent = &func_48m_fclk,
2083 .recalc = &followparent_recalc,
2084};
2085
2086static struct clk mmc4_fck = {
2087 .name = "mmc4_fck",
2088 .ops = &clkops_omap2_dflt,
2089 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2090 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2091 .clkdm_name = "l4_per_clkdm",
2092 .parent = &func_48m_fclk,
2093 .recalc = &followparent_recalc,
2094};
2095
2096static struct clk mmc5_fck = {
2097 .name = "mmc5_fck",
2098 .ops = &clkops_omap2_dflt,
2099 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2100 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2101 .clkdm_name = "l4_per_clkdm",
2102 .parent = &func_48m_fclk,
2103 .recalc = &followparent_recalc,
2104};
2105
2106static struct clk ocp_wp1_ick = {
2107 .name = "ocp_wp1_ick",
2108 .ops = &clkops_omap2_dflt,
2109 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2110 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2111 .clkdm_name = "l3_instr_clkdm",
2112 .parent = &l3_div_ck,
2113 .recalc = &followparent_recalc,
2114};
2115
2116static struct clk pdm_fck = {
2117 .name = "pdm_fck",
2118 .ops = &clkops_omap2_dflt,
2119 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2120 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2121 .clkdm_name = "abe_clkdm",
2122 .parent = &pad_clks_ck,
2123 .recalc = &followparent_recalc,
2124};
2125
2126static struct clk pkaeip29_fck = {
2127 .name = "pkaeip29_fck",
2128 .ops = &clkops_omap2_dflt,
2129 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
2130 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2131 .clkdm_name = "l4_secure_clkdm",
2132 .parent = &l4_div_ck,
2133 .recalc = &followparent_recalc,
2134};
2135
2136static struct clk rng_ick = {
2137 .name = "rng_ick",
2138 .ops = &clkops_omap2_dflt,
2139 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2140 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2141 .clkdm_name = "l4_secure_clkdm",
2142 .parent = &l4_div_ck,
2143 .recalc = &followparent_recalc,
2144};
2145
2146static struct clk sha2md51_fck = {
2147 .name = "sha2md51_fck",
2148 .ops = &clkops_omap2_dflt,
2149 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2150 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2151 .clkdm_name = "l4_secure_clkdm",
2152 .parent = &l3_div_ck,
2153 .recalc = &followparent_recalc,
2154};
2155
2156static struct clk sl2_ick = {
2157 .name = "sl2_ick",
2158 .ops = &clkops_omap2_dflt,
2159 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2160 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2161 .clkdm_name = "ivahd_clkdm",
2162 .parent = &dpll_iva_m5_ck,
2163 .recalc = &followparent_recalc,
2164};
2165
2166static struct clk slimbus1_fck = {
2167 .name = "slimbus1_fck",
2168 .ops = &clkops_omap2_dflt,
2169 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2170 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2171 .clkdm_name = "abe_clkdm",
2172 .parent = &ocp_abe_iclk,
2173 .recalc = &followparent_recalc,
2174};
2175
2176static struct clk slimbus2_fck = {
2177 .name = "slimbus2_fck",
2178 .ops = &clkops_omap2_dflt,
2179 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2180 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2181 .clkdm_name = "l4_per_clkdm",
2182 .parent = &l4_div_ck,
2183 .recalc = &followparent_recalc,
2184};
2185
2186static struct clk sr_core_fck = {
2187 .name = "sr_core_fck",
2188 .ops = &clkops_omap2_dflt,
2189 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2190 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2191 .clkdm_name = "l4_ao_clkdm",
2192 .parent = &l4_wkup_clk_mux_ck,
2193 .recalc = &followparent_recalc,
2194};
2195
2196static struct clk sr_iva_fck = {
2197 .name = "sr_iva_fck",
2198 .ops = &clkops_omap2_dflt,
2199 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2200 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2201 .clkdm_name = "l4_ao_clkdm",
2202 .parent = &l4_wkup_clk_mux_ck,
2203 .recalc = &followparent_recalc,
2204};
2205
2206static struct clk sr_mpu_fck = {
2207 .name = "sr_mpu_fck",
2208 .ops = &clkops_omap2_dflt,
2209 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2210 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2211 .clkdm_name = "l4_ao_clkdm",
2212 .parent = &l4_wkup_clk_mux_ck,
2213 .recalc = &followparent_recalc,
2214};
2215
2216static struct clk tesla_ick = {
2217 .name = "tesla_ick",
2218 .ops = &clkops_omap2_dflt,
2219 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
2220 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2221 .clkdm_name = "tesla_clkdm",
2222 .parent = &dpll_iva_m4_ck,
2223 .recalc = &followparent_recalc,
2224};
2225
2226static struct clk uart1_fck = {
2227 .name = "uart1_fck",
2228 .ops = &clkops_omap2_dflt,
2229 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2230 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2231 .clkdm_name = "l4_per_clkdm",
2232 .parent = &func_48m_fclk,
2233 .recalc = &followparent_recalc,
2234};
2235
2236static struct clk uart2_fck = {
2237 .name = "uart2_fck",
2238 .ops = &clkops_omap2_dflt,
2239 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2240 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2241 .clkdm_name = "l4_per_clkdm",
2242 .parent = &func_48m_fclk,
2243 .recalc = &followparent_recalc,
2244};
2245
2246static struct clk uart3_fck = {
2247 .name = "uart3_fck",
2248 .ops = &clkops_omap2_dflt,
2249 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2250 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2251 .clkdm_name = "l4_per_clkdm",
2252 .parent = &func_48m_fclk,
2253 .recalc = &followparent_recalc,
2254};
2255
2256static struct clk uart4_fck = {
2257 .name = "uart4_fck",
2258 .ops = &clkops_omap2_dflt,
2259 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2260 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2261 .clkdm_name = "l4_per_clkdm",
2262 .parent = &func_48m_fclk,
2263 .recalc = &followparent_recalc,
2264};
2265
2266static struct clk unipro1_fck = {
2267 .name = "unipro1_fck",
2268 .ops = &clkops_omap2_dflt,
2269 .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL,
2270 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2271 .clkdm_name = "l3_init_clkdm",
2272 .parent = &func_96m_fclk,
2273 .recalc = &followparent_recalc,
2274};
2275
2276static struct clk usb_host_fck = {
2277 .name = "usb_host_fck",
2278 .ops = &clkops_omap2_dflt,
2279 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2280 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2281 .clkdm_name = "l3_init_clkdm",
2282 .parent = &init_60m_fclk,
2283 .recalc = &followparent_recalc,
2284};
2285
2286static struct clk usb_host_fs_fck = {
2287 .name = "usb_host_fs_fck",
2288 .ops = &clkops_omap2_dflt,
2289 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2290 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2291 .clkdm_name = "l3_init_clkdm",
2292 .parent = &func_48mc_fclk,
2293 .recalc = &followparent_recalc,
2294};
2295
2296static struct clk usb_otg_ick = {
2297 .name = "usb_otg_ick",
2298 .ops = &clkops_omap2_dflt,
2299 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2300 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2301 .clkdm_name = "l3_init_clkdm",
2302 .parent = &l3_div_ck,
2303 .recalc = &followparent_recalc,
2304};
2305
2306static struct clk usb_tll_ick = {
2307 .name = "usb_tll_ick",
2308 .ops = &clkops_omap2_dflt,
2309 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2310 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2311 .clkdm_name = "l3_init_clkdm",
2312 .parent = &l4_div_ck,
2313 .recalc = &followparent_recalc,
2314};
2315
2316static struct clk usbphyocp2scp_ick = {
2317 .name = "usbphyocp2scp_ick",
2318 .ops = &clkops_omap2_dflt,
2319 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2320 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2321 .clkdm_name = "l3_init_clkdm",
2322 .parent = &l4_div_ck,
2323 .recalc = &followparent_recalc,
2324};
2325
2326static struct clk usim_fck = {
2327 .name = "usim_fck",
2328 .ops = &clkops_omap2_dflt,
2329 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2330 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2331 .clkdm_name = "l4_wkup_clkdm",
2332 .parent = &sys_32k_ck,
2333 .recalc = &followparent_recalc,
2334};
2335
2336static struct clk wdt2_fck = {
2337 .name = "wdt2_fck",
2338 .ops = &clkops_omap2_dflt,
2339 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2340 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2341 .clkdm_name = "l4_wkup_clkdm",
2342 .parent = &sys_32k_ck,
2343 .recalc = &followparent_recalc,
2344};
2345
2346static struct clk wdt3_fck = {
2347 .name = "wdt3_fck",
2348 .ops = &clkops_omap2_dflt,
2349 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2350 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2351 .clkdm_name = "abe_clkdm",
2352 .parent = &sys_32k_ck,
2353 .recalc = &followparent_recalc,
2354};
2355
2356/* Remaining optional clocks */
2357static const struct clksel otg_60m_gfclk_sel[] = {
2358 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2359 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2360 { .parent = NULL },
2361};
2362
2363static struct clk otg_60m_gfclk_ck = {
2364 .name = "otg_60m_gfclk_ck",
2365 .parent = &utmi_phy_clkout_ck,
2366 .clksel = otg_60m_gfclk_sel,
2367 .init = &omap2_init_clksel_parent,
2368 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2369 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2370 .ops = &clkops_null,
2371 .recalc = &omap2_clksel_recalc,
2372};
2373
2374static const struct clksel stm_clk_div_div[] = {
2375 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2376 { .parent = NULL },
2377};
2378
2379static struct clk stm_clk_div_ck = {
2380 .name = "stm_clk_div_ck",
2381 .parent = &pmd_stm_clock_mux_ck,
2382 .clksel = stm_clk_div_div,
2383 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2384 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2385 .ops = &clkops_null,
2386 .recalc = &omap2_clksel_recalc,
2387 .round_rate = &omap2_clksel_round_rate,
2388 .set_rate = &omap2_clksel_set_rate,
2389};
2390
2391static const struct clksel trace_clk_div_div[] = {
2392 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2393 { .parent = NULL },
2394};
2395
2396static struct clk trace_clk_div_ck = {
2397 .name = "trace_clk_div_ck",
2398 .parent = &pmd_trace_clk_mux_ck,
2399 .clksel = trace_clk_div_div,
2400 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2401 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2402 .ops = &clkops_null,
2403 .recalc = &omap2_clksel_recalc,
2404 .round_rate = &omap2_clksel_round_rate,
2405 .set_rate = &omap2_clksel_set_rate,
2406};
2407
2408static const struct clksel_rate div2_14to18_rates[] = {
2409 { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2410 { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2411 { .div = 0 },
2412};
2413
2414static const struct clksel usim_fclk_div[] = {
2415 { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
2416 { .parent = NULL },
2417};
2418
2419static struct clk usim_fclk = {
2420 .name = "usim_fclk",
2421 .parent = &dpll_per_m4_ck,
2422 .clksel = usim_fclk_div,
2423 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2424 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
2425 .ops = &clkops_null,
2426 .recalc = &omap2_clksel_recalc,
2427 .round_rate = &omap2_clksel_round_rate,
2428 .set_rate = &omap2_clksel_set_rate,
2429};
2430
2431static const struct clksel utmi_p1_gfclk_sel[] = {
2432 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2433 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2434 { .parent = NULL },
2435};
2436
2437static struct clk utmi_p1_gfclk_ck = {
2438 .name = "utmi_p1_gfclk_ck",
2439 .parent = &init_60m_fclk,
2440 .clksel = utmi_p1_gfclk_sel,
2441 .init = &omap2_init_clksel_parent,
2442 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2443 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2444 .ops = &clkops_null,
2445 .recalc = &omap2_clksel_recalc,
2446};
2447
2448static const struct clksel utmi_p2_gfclk_sel[] = {
2449 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2450 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2451 { .parent = NULL },
2452};
2453
2454static struct clk utmi_p2_gfclk_ck = {
2455 .name = "utmi_p2_gfclk_ck",
2456 .parent = &init_60m_fclk,
2457 .clksel = utmi_p2_gfclk_sel,
2458 .init = &omap2_init_clksel_parent,
2459 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2460 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2461 .ops = &clkops_null,
2462 .recalc = &omap2_clksel_recalc,
2463};
2464
2465/*
2466 * clkdev
2467 */
2468
2469static struct omap_clk omap44xx_clks[] = {
2470 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
2471 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
2472 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
2473 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
2474 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
2475 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
2476 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
2477 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
2478 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
2479 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
2480 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
2481 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
2482 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
2483 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
2484 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
2485 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
2486 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
2487 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
2488 CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X),
2489 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
2490 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
2491 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
2492 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
2493 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
2494 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
2495 CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X),
2496 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
2497 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
2498 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X),
2499 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
2500 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
2501 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
2502 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X),
2503 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
2504 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
2505 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
2506 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X),
2507 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
2508 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
2509 CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X),
2510 CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X),
2511 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
2512 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
2513 CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X),
2514 CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X),
2515 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
2516 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
2517 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
2518 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
2519 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
2520 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
2521 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
2522 CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X),
2523 CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X),
2524 CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X),
2525 CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X),
2526 CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X),
2527 CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
2528 CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
2529 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
2530 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
2531 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
2532 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
2533 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
2534 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
2535 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
2536 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
2537 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
2538 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
2539 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
2540 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
2541 CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
2542 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
2543 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
2544 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
2545 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
2546 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
2547 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
2548 CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
2549 CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
2550 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
2551 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
2552 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
2553 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
2554 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
2555 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
2556 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
2557 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
2558 CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X),
2559 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
2560 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
2561 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
2562 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
2563 CLK(NULL, "ducati_ick", &ducati_ick, CK_443X),
2564 CLK(NULL, "emif1_ick", &emif1_ick, CK_443X),
2565 CLK(NULL, "emif2_ick", &emif2_ick, CK_443X),
2566 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
2567 CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X),
2568 CLK(NULL, "gfx_fck", &gfx_fck, CK_443X),
2569 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
2570 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
2571 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
2572 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
2573 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
2574 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
2575 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
2576 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X),
2577 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X),
2578 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X),
2579 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X),
2580 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X),
2581 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X),
2582 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X),
2583 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X),
2584 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X),
2585 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X),
2586 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X),
2587 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
2588 CLK(NULL, "hsi_ick", &hsi_ick, CK_443X),
2589 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X),
2590 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X),
2591 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X),
2592 CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X),
2593 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
2594 CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X),
2595 CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X),
2596 CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X),
2597 CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X),
2598 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
2599 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
2600 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
2601 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X),
2602 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
2603 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X),
2604 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
2605 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
2606 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
2607 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
2608 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
2609 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
2610 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
2611 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
2612 CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X),
2613 CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X),
2614 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X),
2615 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X),
2616 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X),
2617 CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X),
2618 CLK(NULL, "pdm_fck", &pdm_fck, CK_443X),
2619 CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X),
2620 CLK("omap_rng", "ick", &rng_ick, CK_443X),
2621 CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X),
2622 CLK(NULL, "sl2_ick", &sl2_ick, CK_443X),
2623 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
2624 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
2625 CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X),
2626 CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X),
2627 CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X),
2628 CLK(NULL, "tesla_ick", &tesla_ick, CK_443X),
2629 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
2630 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
2631 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
2632 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
2633 CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X),
2634 CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X),
2635 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
2636 CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X),
2637 CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X),
2638 CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X),
2639 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
2640 CLK("omap_wdt", "fck", &wdt2_fck, CK_443X),
2641 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X),
2642 CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X),
2643 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
2644 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
2645 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
2646 CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X),
2647 CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X),
2648 CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X),
2649 CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X),
2650 CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X),
2651 CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X),
2652 CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X),
2653 CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X),
2654 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
2655 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
2656 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
2657 CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X),
2658 CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X),
2659 CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X),
2660 CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X),
2661 CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X),
2662 CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X),
2663 CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
2664 CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
2665 CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
2666 CLK("i2c_omap.1", "ick", &dummy_ck, CK_443X),
2667 CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X),
2668 CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X),
2669 CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X),
2670 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
2671 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
2672 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
2673 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
2674 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
2675 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
2676 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
2677 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
2678 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
2679 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
2680 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
2681 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
2682 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
2683};
2684
2685int __init omap4xxx_clk_init(void)
2686{
2687 struct omap_clk *c;
2688 u32 cpu_clkflg;
2689
2690 if (cpu_is_omap44xx()) {
2691 cpu_mask = RATE_IN_4430;
2692 cpu_clkflg = CK_443X;
2693 }
2694
2695 clk_init(&omap2_clk_functions);
2696
2697 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
2698 c++)
2699 clk_preinit(c->lk.clk);
2700
2701 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
2702 c++)
2703 if (c->cpu & cpu_clkflg) {
2704 clkdev_add(&c->lk);
2705 clk_register(c->lk.clk);
2706 omap2_init_clk_clkdm(c->lk.clk);
2707 }
2708
2709 recalculate_root_clocks();
2710
2711 /*
2712 * Only enable those clocks we will need, let the drivers
2713 * enable other clocks as necessary
2714 */
2715 clk_enable_init_clocks();
2716
2717 return 0;
2718}
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-01 22:06:07 -0400