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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/arm/mach-omap2/clock3xxx_data.c
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'arch/arm/mach-omap2/clock3xxx_data.c')
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c470
1 files changed, 264 insertions, 206 deletions
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index dfdce2d82779..75b119bd9cda 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -2,7 +2,7 @@
2 * OMAP3 clock data 2 * OMAP3 clock data
3 * 3 *
4 * Copyright (C) 2007-2010 Texas Instruments, Inc. 4 * Copyright (C) 2007-2010 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation 5 * Copyright (C) 2007-2011 Nokia Corporation
6 * 6 *
7 * Written by Paul Walmsley 7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander 8 * With many device clock fixes by Kevin Hilman and Jouni Högander
@@ -20,7 +20,6 @@
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/list.h> 21#include <linux/list.h>
22 22
23#include <plat/control.h>
24#include <plat/clkdev_omap.h> 23#include <plat/clkdev_omap.h>
25 24
26#include "clock.h" 25#include "clock.h"
@@ -29,10 +28,11 @@
29#include "clock36xx.h" 28#include "clock36xx.h"
30#include "clock3517.h" 29#include "clock3517.h"
31 30
32#include "cm.h" 31#include "cm2xxx_3xxx.h"
33#include "cm-regbits-34xx.h" 32#include "cm-regbits-34xx.h"
34#include "prm.h" 33#include "prm2xxx_3xxx.h"
35#include "prm-regbits-34xx.h" 34#include "prm-regbits-34xx.h"
35#include "control.h"
36 36
37/* 37/*
38 * clocks 38 * clocks
@@ -120,7 +120,7 @@ static const struct clksel_rate osc_sys_13m_rates[] = {
120}; 120};
121 121
122static const struct clksel_rate osc_sys_16_8m_rates[] = { 122static const struct clksel_rate osc_sys_16_8m_rates[] = {
123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS }, 123 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
124 { .div = 0 } 124 { .div = 0 }
125}; 125};
126 126
@@ -291,12 +291,11 @@ static struct dpll_data dpll1_dd = {
291 .max_multiplier = OMAP3_MAX_DPLL_MULT, 291 .max_multiplier = OMAP3_MAX_DPLL_MULT,
292 .min_divider = 1, 292 .min_divider = 1,
293 .max_divider = OMAP3_MAX_DPLL_DIV, 293 .max_divider = OMAP3_MAX_DPLL_DIV,
294 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
295}; 294};
296 295
297static struct clk dpll1_ck = { 296static struct clk dpll1_ck = {
298 .name = "dpll1_ck", 297 .name = "dpll1_ck",
299 .ops = &clkops_null, 298 .ops = &clkops_omap3_noncore_dpll_ops,
300 .parent = &sys_ck, 299 .parent = &sys_ck,
301 .dpll_data = &dpll1_dd, 300 .dpll_data = &dpll1_dd,
302 .round_rate = &omap2_dpll_round_rate, 301 .round_rate = &omap2_dpll_round_rate,
@@ -364,7 +363,6 @@ static struct dpll_data dpll2_dd = {
364 .max_multiplier = OMAP3_MAX_DPLL_MULT, 363 .max_multiplier = OMAP3_MAX_DPLL_MULT,
365 .min_divider = 1, 364 .min_divider = 1,
366 .max_divider = OMAP3_MAX_DPLL_DIV, 365 .max_divider = OMAP3_MAX_DPLL_DIV,
367 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
368}; 366};
369 367
370static struct clk dpll2_ck = { 368static struct clk dpll2_ck = {
@@ -424,12 +422,11 @@ static struct dpll_data dpll3_dd = {
424 .max_multiplier = OMAP3_MAX_DPLL_MULT, 422 .max_multiplier = OMAP3_MAX_DPLL_MULT,
425 .min_divider = 1, 423 .min_divider = 1,
426 .max_divider = OMAP3_MAX_DPLL_DIV, 424 .max_divider = OMAP3_MAX_DPLL_DIV,
427 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
428}; 425};
429 426
430static struct clk dpll3_ck = { 427static struct clk dpll3_ck = {
431 .name = "dpll3_ck", 428 .name = "dpll3_ck",
432 .ops = &clkops_null, 429 .ops = &clkops_omap3_core_dpll_ops,
433 .parent = &sys_ck, 430 .parent = &sys_ck,
434 .dpll_data = &dpll3_dd, 431 .dpll_data = &dpll3_dd,
435 .round_rate = &omap2_dpll_round_rate, 432 .round_rate = &omap2_dpll_round_rate,
@@ -452,35 +449,35 @@ static struct clk dpll3_x2_ck = {
452static const struct clksel_rate div31_dpll3_rates[] = { 449static const struct clksel_rate div31_dpll3_rates[] = {
453 { .div = 1, .val = 1, .flags = RATE_IN_3XXX }, 450 { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
454 { .div = 2, .val = 2, .flags = RATE_IN_3XXX }, 451 { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
455 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS }, 452 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
456 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS }, 453 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
457 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS }, 454 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
458 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS }, 455 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
459 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS }, 456 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
460 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS }, 457 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
461 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS }, 458 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
462 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS }, 459 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
463 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS }, 460 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
464 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS }, 461 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
465 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS }, 462 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
466 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS }, 463 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
467 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS }, 464 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
468 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS }, 465 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
469 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS }, 466 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
470 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS }, 467 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
471 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS }, 468 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
472 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS }, 469 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
473 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS }, 470 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
474 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS }, 471 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
475 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS }, 472 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
476 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS }, 473 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
477 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS }, 474 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
478 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS }, 475 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
479 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS }, 476 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
480 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS }, 477 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
481 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS }, 478 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
482 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS }, 479 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
483 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS }, 480 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
484 { .div = 0 }, 481 { .div = 0 },
485}; 482};
486 483
@@ -583,7 +580,6 @@ static struct dpll_data dpll4_dd_34xx __initdata = {
583 .max_multiplier = OMAP3_MAX_DPLL_MULT, 580 .max_multiplier = OMAP3_MAX_DPLL_MULT,
584 .min_divider = 1, 581 .min_divider = 1,
585 .max_divider = OMAP3_MAX_DPLL_DIV, 582 .max_divider = OMAP3_MAX_DPLL_DIV,
586 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
587}; 583};
588 584
589static struct dpll_data dpll4_dd_3630 __initdata = { 585static struct dpll_data dpll4_dd_3630 __initdata = {
@@ -602,10 +598,11 @@ static struct dpll_data dpll4_dd_3630 __initdata = {
602 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, 598 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
603 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 599 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
604 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, 600 .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK,
601 .dco_mask = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
602 .sddiv_mask = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
605 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT, 603 .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
606 .min_divider = 1, 604 .min_divider = 1,
607 .max_divider = OMAP3_MAX_DPLL_DIV, 605 .max_divider = OMAP3_MAX_DPLL_DIV,
608 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
609 .flags = DPLL_J_TYPE 606 .flags = DPLL_J_TYPE
610}; 607};
611 608
@@ -937,7 +934,6 @@ static struct dpll_data dpll5_dd = {
937 .max_multiplier = OMAP3_MAX_DPLL_MULT, 934 .max_multiplier = OMAP3_MAX_DPLL_MULT,
938 .min_divider = 1, 935 .min_divider = 1,
939 .max_divider = OMAP3_MAX_DPLL_DIV, 936 .max_divider = OMAP3_MAX_DPLL_DIV,
940 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
941}; 937};
942 938
943static struct clk dpll5_ck = { 939static struct clk dpll5_ck = {
@@ -1203,7 +1199,10 @@ static const struct clksel gfx_l3_clksel[] = {
1203 { .parent = NULL } 1199 { .parent = NULL }
1204}; 1200};
1205 1201
1206/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ 1202/*
1203 * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1204 * This interface clock does not have a CM_AUTOIDLE bit
1205 */
1207static struct clk gfx_l3_ck = { 1206static struct clk gfx_l3_ck = {
1208 .name = "gfx_l3_ck", 1207 .name = "gfx_l3_ck",
1209 .ops = &clkops_omap2_dflt_wait, 1208 .ops = &clkops_omap2_dflt_wait,
@@ -1302,6 +1301,7 @@ static struct clk sgx_fck = {
1302 .round_rate = &omap2_clksel_round_rate 1301 .round_rate = &omap2_clksel_round_rate
1303}; 1302};
1304 1303
1304/* This interface clock does not have a CM_AUTOIDLE bit */
1305static struct clk sgx_ick = { 1305static struct clk sgx_ick = {
1306 .name = "sgx_ick", 1306 .name = "sgx_ick",
1307 .ops = &clkops_omap2_dflt_wait, 1307 .ops = &clkops_omap2_dflt_wait,
@@ -1326,7 +1326,7 @@ static struct clk d2d_26m_fck = {
1326 1326
1327static struct clk modem_fck = { 1327static struct clk modem_fck = {
1328 .name = "modem_fck", 1328 .name = "modem_fck",
1329 .ops = &clkops_omap2_dflt_wait, 1329 .ops = &clkops_omap2_mdmclk_dflt_wait,
1330 .parent = &sys_ck, 1330 .parent = &sys_ck,
1331 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1331 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1332 .enable_bit = OMAP3430_EN_MODEM_SHIFT, 1332 .enable_bit = OMAP3430_EN_MODEM_SHIFT,
@@ -1336,7 +1336,7 @@ static struct clk modem_fck = {
1336 1336
1337static struct clk sad2d_ick = { 1337static struct clk sad2d_ick = {
1338 .name = "sad2d_ick", 1338 .name = "sad2d_ick",
1339 .ops = &clkops_omap2_dflt_wait, 1339 .ops = &clkops_omap2_iclk_dflt_wait,
1340 .parent = &l3_ick, 1340 .parent = &l3_ick,
1341 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1341 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1342 .enable_bit = OMAP3430_EN_SAD2D_SHIFT, 1342 .enable_bit = OMAP3430_EN_SAD2D_SHIFT,
@@ -1346,7 +1346,7 @@ static struct clk sad2d_ick = {
1346 1346
1347static struct clk mad2d_ick = { 1347static struct clk mad2d_ick = {
1348 .name = "mad2d_ick", 1348 .name = "mad2d_ick",
1349 .ops = &clkops_omap2_dflt_wait, 1349 .ops = &clkops_omap2_iclk_dflt_wait,
1350 .parent = &l3_ick, 1350 .parent = &l3_ick,
1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1352 .enable_bit = OMAP3430_EN_MAD2D_SHIFT, 1352 .enable_bit = OMAP3430_EN_MAD2D_SHIFT,
@@ -1558,6 +1558,7 @@ static struct clk mcspi4_fck = {
1558 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1558 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1559 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1559 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1560 .recalc = &followparent_recalc, 1560 .recalc = &followparent_recalc,
1561 .clkdm_name = "core_l4_clkdm",
1561}; 1562};
1562 1563
1563static struct clk mcspi3_fck = { 1564static struct clk mcspi3_fck = {
@@ -1567,6 +1568,7 @@ static struct clk mcspi3_fck = {
1567 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1568 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1568 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1569 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1569 .recalc = &followparent_recalc, 1570 .recalc = &followparent_recalc,
1571 .clkdm_name = "core_l4_clkdm",
1570}; 1572};
1571 1573
1572static struct clk mcspi2_fck = { 1574static struct clk mcspi2_fck = {
@@ -1576,6 +1578,7 @@ static struct clk mcspi2_fck = {
1576 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1578 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1577 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1579 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1578 .recalc = &followparent_recalc, 1580 .recalc = &followparent_recalc,
1581 .clkdm_name = "core_l4_clkdm",
1579}; 1582};
1580 1583
1581static struct clk mcspi1_fck = { 1584static struct clk mcspi1_fck = {
@@ -1585,6 +1588,7 @@ static struct clk mcspi1_fck = {
1585 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1588 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1586 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1589 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1587 .recalc = &followparent_recalc, 1590 .recalc = &followparent_recalc,
1591 .clkdm_name = "core_l4_clkdm",
1588}; 1592};
1589 1593
1590static struct clk uart2_fck = { 1594static struct clk uart2_fck = {
@@ -1712,7 +1716,7 @@ static struct clk core_l3_ick = {
1712 1716
1713static struct clk hsotgusb_ick_3430es1 = { 1717static struct clk hsotgusb_ick_3430es1 = {
1714 .name = "hsotgusb_ick", 1718 .name = "hsotgusb_ick",
1715 .ops = &clkops_omap2_dflt, 1719 .ops = &clkops_omap2_iclk_dflt,
1716 .parent = &core_l3_ick, 1720 .parent = &core_l3_ick,
1717 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1721 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1718 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1722 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1722,7 +1726,7 @@ static struct clk hsotgusb_ick_3430es1 = {
1722 1726
1723static struct clk hsotgusb_ick_3430es2 = { 1727static struct clk hsotgusb_ick_3430es2 = {
1724 .name = "hsotgusb_ick", 1728 .name = "hsotgusb_ick",
1725 .ops = &clkops_omap3430es2_hsotgusb_wait, 1729 .ops = &clkops_omap3430es2_iclk_hsotgusb_wait,
1726 .parent = &core_l3_ick, 1730 .parent = &core_l3_ick,
1727 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1731 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1728 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, 1732 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1730,6 +1734,7 @@ static struct clk hsotgusb_ick_3430es2 = {
1730 .recalc = &followparent_recalc, 1734 .recalc = &followparent_recalc,
1731}; 1735};
1732 1736
1737/* This interface clock does not have a CM_AUTOIDLE bit */
1733static struct clk sdrc_ick = { 1738static struct clk sdrc_ick = {
1734 .name = "sdrc_ick", 1739 .name = "sdrc_ick",
1735 .ops = &clkops_omap2_dflt_wait, 1740 .ops = &clkops_omap2_dflt_wait,
@@ -1761,7 +1766,7 @@ static struct clk security_l3_ick = {
1761 1766
1762static struct clk pka_ick = { 1767static struct clk pka_ick = {
1763 .name = "pka_ick", 1768 .name = "pka_ick",
1764 .ops = &clkops_omap2_dflt_wait, 1769 .ops = &clkops_omap2_iclk_dflt_wait,
1765 .parent = &security_l3_ick, 1770 .parent = &security_l3_ick,
1766 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1767 .enable_bit = OMAP3430_EN_PKA_SHIFT, 1772 .enable_bit = OMAP3430_EN_PKA_SHIFT,
@@ -1780,7 +1785,7 @@ static struct clk core_l4_ick = {
1780 1785
1781static struct clk usbtll_ick = { 1786static struct clk usbtll_ick = {
1782 .name = "usbtll_ick", 1787 .name = "usbtll_ick",
1783 .ops = &clkops_omap2_dflt_wait, 1788 .ops = &clkops_omap2_iclk_dflt_wait,
1784 .parent = &core_l4_ick, 1789 .parent = &core_l4_ick,
1785 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), 1790 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1786 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, 1791 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
@@ -1790,7 +1795,7 @@ static struct clk usbtll_ick = {
1790 1795
1791static struct clk mmchs3_ick = { 1796static struct clk mmchs3_ick = {
1792 .name = "mmchs3_ick", 1797 .name = "mmchs3_ick",
1793 .ops = &clkops_omap2_dflt_wait, 1798 .ops = &clkops_omap2_iclk_dflt_wait,
1794 .parent = &core_l4_ick, 1799 .parent = &core_l4_ick,
1795 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1800 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1796 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, 1801 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
@@ -1801,7 +1806,7 @@ static struct clk mmchs3_ick = {
1801/* Intersystem Communication Registers - chassis mode only */ 1806/* Intersystem Communication Registers - chassis mode only */
1802static struct clk icr_ick = { 1807static struct clk icr_ick = {
1803 .name = "icr_ick", 1808 .name = "icr_ick",
1804 .ops = &clkops_omap2_dflt_wait, 1809 .ops = &clkops_omap2_iclk_dflt_wait,
1805 .parent = &core_l4_ick, 1810 .parent = &core_l4_ick,
1806 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1811 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1807 .enable_bit = OMAP3430_EN_ICR_SHIFT, 1812 .enable_bit = OMAP3430_EN_ICR_SHIFT,
@@ -1811,7 +1816,7 @@ static struct clk icr_ick = {
1811 1816
1812static struct clk aes2_ick = { 1817static struct clk aes2_ick = {
1813 .name = "aes2_ick", 1818 .name = "aes2_ick",
1814 .ops = &clkops_omap2_dflt_wait, 1819 .ops = &clkops_omap2_iclk_dflt_wait,
1815 .parent = &core_l4_ick, 1820 .parent = &core_l4_ick,
1816 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1817 .enable_bit = OMAP3430_EN_AES2_SHIFT, 1822 .enable_bit = OMAP3430_EN_AES2_SHIFT,
@@ -1821,7 +1826,7 @@ static struct clk aes2_ick = {
1821 1826
1822static struct clk sha12_ick = { 1827static struct clk sha12_ick = {
1823 .name = "sha12_ick", 1828 .name = "sha12_ick",
1824 .ops = &clkops_omap2_dflt_wait, 1829 .ops = &clkops_omap2_iclk_dflt_wait,
1825 .parent = &core_l4_ick, 1830 .parent = &core_l4_ick,
1826 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1827 .enable_bit = OMAP3430_EN_SHA12_SHIFT, 1832 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
@@ -1831,7 +1836,7 @@ static struct clk sha12_ick = {
1831 1836
1832static struct clk des2_ick = { 1837static struct clk des2_ick = {
1833 .name = "des2_ick", 1838 .name = "des2_ick",
1834 .ops = &clkops_omap2_dflt_wait, 1839 .ops = &clkops_omap2_iclk_dflt_wait,
1835 .parent = &core_l4_ick, 1840 .parent = &core_l4_ick,
1836 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1837 .enable_bit = OMAP3430_EN_DES2_SHIFT, 1842 .enable_bit = OMAP3430_EN_DES2_SHIFT,
@@ -1841,7 +1846,7 @@ static struct clk des2_ick = {
1841 1846
1842static struct clk mmchs2_ick = { 1847static struct clk mmchs2_ick = {
1843 .name = "mmchs2_ick", 1848 .name = "mmchs2_ick",
1844 .ops = &clkops_omap2_dflt_wait, 1849 .ops = &clkops_omap2_iclk_dflt_wait,
1845 .parent = &core_l4_ick, 1850 .parent = &core_l4_ick,
1846 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1847 .enable_bit = OMAP3430_EN_MMC2_SHIFT, 1852 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
@@ -1851,7 +1856,7 @@ static struct clk mmchs2_ick = {
1851 1856
1852static struct clk mmchs1_ick = { 1857static struct clk mmchs1_ick = {
1853 .name = "mmchs1_ick", 1858 .name = "mmchs1_ick",
1854 .ops = &clkops_omap2_dflt_wait, 1859 .ops = &clkops_omap2_iclk_dflt_wait,
1855 .parent = &core_l4_ick, 1860 .parent = &core_l4_ick,
1856 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1861 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1857 .enable_bit = OMAP3430_EN_MMC1_SHIFT, 1862 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
@@ -1861,7 +1866,7 @@ static struct clk mmchs1_ick = {
1861 1866
1862static struct clk mspro_ick = { 1867static struct clk mspro_ick = {
1863 .name = "mspro_ick", 1868 .name = "mspro_ick",
1864 .ops = &clkops_omap2_dflt_wait, 1869 .ops = &clkops_omap2_iclk_dflt_wait,
1865 .parent = &core_l4_ick, 1870 .parent = &core_l4_ick,
1866 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1871 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1867 .enable_bit = OMAP3430_EN_MSPRO_SHIFT, 1872 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
@@ -1871,7 +1876,7 @@ static struct clk mspro_ick = {
1871 1876
1872static struct clk hdq_ick = { 1877static struct clk hdq_ick = {
1873 .name = "hdq_ick", 1878 .name = "hdq_ick",
1874 .ops = &clkops_omap2_dflt_wait, 1879 .ops = &clkops_omap2_iclk_dflt_wait,
1875 .parent = &core_l4_ick, 1880 .parent = &core_l4_ick,
1876 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1877 .enable_bit = OMAP3430_EN_HDQ_SHIFT, 1882 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
@@ -1881,7 +1886,7 @@ static struct clk hdq_ick = {
1881 1886
1882static struct clk mcspi4_ick = { 1887static struct clk mcspi4_ick = {
1883 .name = "mcspi4_ick", 1888 .name = "mcspi4_ick",
1884 .ops = &clkops_omap2_dflt_wait, 1889 .ops = &clkops_omap2_iclk_dflt_wait,
1885 .parent = &core_l4_ick, 1890 .parent = &core_l4_ick,
1886 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1887 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, 1892 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
@@ -1891,7 +1896,7 @@ static struct clk mcspi4_ick = {
1891 1896
1892static struct clk mcspi3_ick = { 1897static struct clk mcspi3_ick = {
1893 .name = "mcspi3_ick", 1898 .name = "mcspi3_ick",
1894 .ops = &clkops_omap2_dflt_wait, 1899 .ops = &clkops_omap2_iclk_dflt_wait,
1895 .parent = &core_l4_ick, 1900 .parent = &core_l4_ick,
1896 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1901 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1897 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, 1902 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
@@ -1901,7 +1906,7 @@ static struct clk mcspi3_ick = {
1901 1906
1902static struct clk mcspi2_ick = { 1907static struct clk mcspi2_ick = {
1903 .name = "mcspi2_ick", 1908 .name = "mcspi2_ick",
1904 .ops = &clkops_omap2_dflt_wait, 1909 .ops = &clkops_omap2_iclk_dflt_wait,
1905 .parent = &core_l4_ick, 1910 .parent = &core_l4_ick,
1906 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1911 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1907 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, 1912 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
@@ -1911,7 +1916,7 @@ static struct clk mcspi2_ick = {
1911 1916
1912static struct clk mcspi1_ick = { 1917static struct clk mcspi1_ick = {
1913 .name = "mcspi1_ick", 1918 .name = "mcspi1_ick",
1914 .ops = &clkops_omap2_dflt_wait, 1919 .ops = &clkops_omap2_iclk_dflt_wait,
1915 .parent = &core_l4_ick, 1920 .parent = &core_l4_ick,
1916 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1921 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1917 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, 1922 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
@@ -1921,7 +1926,7 @@ static struct clk mcspi1_ick = {
1921 1926
1922static struct clk i2c3_ick = { 1927static struct clk i2c3_ick = {
1923 .name = "i2c3_ick", 1928 .name = "i2c3_ick",
1924 .ops = &clkops_omap2_dflt_wait, 1929 .ops = &clkops_omap2_iclk_dflt_wait,
1925 .parent = &core_l4_ick, 1930 .parent = &core_l4_ick,
1926 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1927 .enable_bit = OMAP3430_EN_I2C3_SHIFT, 1932 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
@@ -1931,7 +1936,7 @@ static struct clk i2c3_ick = {
1931 1936
1932static struct clk i2c2_ick = { 1937static struct clk i2c2_ick = {
1933 .name = "i2c2_ick", 1938 .name = "i2c2_ick",
1934 .ops = &clkops_omap2_dflt_wait, 1939 .ops = &clkops_omap2_iclk_dflt_wait,
1935 .parent = &core_l4_ick, 1940 .parent = &core_l4_ick,
1936 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1941 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1937 .enable_bit = OMAP3430_EN_I2C2_SHIFT, 1942 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
@@ -1941,7 +1946,7 @@ static struct clk i2c2_ick = {
1941 1946
1942static struct clk i2c1_ick = { 1947static struct clk i2c1_ick = {
1943 .name = "i2c1_ick", 1948 .name = "i2c1_ick",
1944 .ops = &clkops_omap2_dflt_wait, 1949 .ops = &clkops_omap2_iclk_dflt_wait,
1945 .parent = &core_l4_ick, 1950 .parent = &core_l4_ick,
1946 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1951 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1947 .enable_bit = OMAP3430_EN_I2C1_SHIFT, 1952 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
@@ -1951,7 +1956,7 @@ static struct clk i2c1_ick = {
1951 1956
1952static struct clk uart2_ick = { 1957static struct clk uart2_ick = {
1953 .name = "uart2_ick", 1958 .name = "uart2_ick",
1954 .ops = &clkops_omap2_dflt_wait, 1959 .ops = &clkops_omap2_iclk_dflt_wait,
1955 .parent = &core_l4_ick, 1960 .parent = &core_l4_ick,
1956 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1961 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1957 .enable_bit = OMAP3430_EN_UART2_SHIFT, 1962 .enable_bit = OMAP3430_EN_UART2_SHIFT,
@@ -1961,7 +1966,7 @@ static struct clk uart2_ick = {
1961 1966
1962static struct clk uart1_ick = { 1967static struct clk uart1_ick = {
1963 .name = "uart1_ick", 1968 .name = "uart1_ick",
1964 .ops = &clkops_omap2_dflt_wait, 1969 .ops = &clkops_omap2_iclk_dflt_wait,
1965 .parent = &core_l4_ick, 1970 .parent = &core_l4_ick,
1966 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1971 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1967 .enable_bit = OMAP3430_EN_UART1_SHIFT, 1972 .enable_bit = OMAP3430_EN_UART1_SHIFT,
@@ -1971,7 +1976,7 @@ static struct clk uart1_ick = {
1971 1976
1972static struct clk gpt11_ick = { 1977static struct clk gpt11_ick = {
1973 .name = "gpt11_ick", 1978 .name = "gpt11_ick",
1974 .ops = &clkops_omap2_dflt_wait, 1979 .ops = &clkops_omap2_iclk_dflt_wait,
1975 .parent = &core_l4_ick, 1980 .parent = &core_l4_ick,
1976 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1981 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1977 .enable_bit = OMAP3430_EN_GPT11_SHIFT, 1982 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
@@ -1981,7 +1986,7 @@ static struct clk gpt11_ick = {
1981 1986
1982static struct clk gpt10_ick = { 1987static struct clk gpt10_ick = {
1983 .name = "gpt10_ick", 1988 .name = "gpt10_ick",
1984 .ops = &clkops_omap2_dflt_wait, 1989 .ops = &clkops_omap2_iclk_dflt_wait,
1985 .parent = &core_l4_ick, 1990 .parent = &core_l4_ick,
1986 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1991 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1987 .enable_bit = OMAP3430_EN_GPT10_SHIFT, 1992 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
@@ -1991,7 +1996,7 @@ static struct clk gpt10_ick = {
1991 1996
1992static struct clk mcbsp5_ick = { 1997static struct clk mcbsp5_ick = {
1993 .name = "mcbsp5_ick", 1998 .name = "mcbsp5_ick",
1994 .ops = &clkops_omap2_dflt_wait, 1999 .ops = &clkops_omap2_iclk_dflt_wait,
1995 .parent = &core_l4_ick, 2000 .parent = &core_l4_ick,
1996 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1997 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 2002 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
@@ -2001,7 +2006,7 @@ static struct clk mcbsp5_ick = {
2001 2006
2002static struct clk mcbsp1_ick = { 2007static struct clk mcbsp1_ick = {
2003 .name = "mcbsp1_ick", 2008 .name = "mcbsp1_ick",
2004 .ops = &clkops_omap2_dflt_wait, 2009 .ops = &clkops_omap2_iclk_dflt_wait,
2005 .parent = &core_l4_ick, 2010 .parent = &core_l4_ick,
2006 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2011 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2007 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 2012 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
@@ -2011,7 +2016,7 @@ static struct clk mcbsp1_ick = {
2011 2016
2012static struct clk fac_ick = { 2017static struct clk fac_ick = {
2013 .name = "fac_ick", 2018 .name = "fac_ick",
2014 .ops = &clkops_omap2_dflt_wait, 2019 .ops = &clkops_omap2_iclk_dflt_wait,
2015 .parent = &core_l4_ick, 2020 .parent = &core_l4_ick,
2016 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2021 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2017 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, 2022 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
@@ -2021,7 +2026,7 @@ static struct clk fac_ick = {
2021 2026
2022static struct clk mailboxes_ick = { 2027static struct clk mailboxes_ick = {
2023 .name = "mailboxes_ick", 2028 .name = "mailboxes_ick",
2024 .ops = &clkops_omap2_dflt_wait, 2029 .ops = &clkops_omap2_iclk_dflt_wait,
2025 .parent = &core_l4_ick, 2030 .parent = &core_l4_ick,
2026 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2031 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2027 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, 2032 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
@@ -2031,7 +2036,7 @@ static struct clk mailboxes_ick = {
2031 2036
2032static struct clk omapctrl_ick = { 2037static struct clk omapctrl_ick = {
2033 .name = "omapctrl_ick", 2038 .name = "omapctrl_ick",
2034 .ops = &clkops_omap2_dflt_wait, 2039 .ops = &clkops_omap2_iclk_dflt_wait,
2035 .parent = &core_l4_ick, 2040 .parent = &core_l4_ick,
2036 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2041 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2037 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, 2042 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
@@ -2051,7 +2056,7 @@ static struct clk ssi_l4_ick = {
2051 2056
2052static struct clk ssi_ick_3430es1 = { 2057static struct clk ssi_ick_3430es1 = {
2053 .name = "ssi_ick", 2058 .name = "ssi_ick",
2054 .ops = &clkops_omap2_dflt, 2059 .ops = &clkops_omap2_iclk_dflt,
2055 .parent = &ssi_l4_ick, 2060 .parent = &ssi_l4_ick,
2056 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2061 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2057 .enable_bit = OMAP3430_EN_SSI_SHIFT, 2062 .enable_bit = OMAP3430_EN_SSI_SHIFT,
@@ -2061,7 +2066,7 @@ static struct clk ssi_ick_3430es1 = {
2061 2066
2062static struct clk ssi_ick_3430es2 = { 2067static struct clk ssi_ick_3430es2 = {
2063 .name = "ssi_ick", 2068 .name = "ssi_ick",
2064 .ops = &clkops_omap3430es2_ssi_wait, 2069 .ops = &clkops_omap3430es2_iclk_ssi_wait,
2065 .parent = &ssi_l4_ick, 2070 .parent = &ssi_l4_ick,
2066 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2071 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2067 .enable_bit = OMAP3430_EN_SSI_SHIFT, 2072 .enable_bit = OMAP3430_EN_SSI_SHIFT,
@@ -2079,7 +2084,7 @@ static const struct clksel usb_l4_clksel[] = {
2079 2084
2080static struct clk usb_l4_ick = { 2085static struct clk usb_l4_ick = {
2081 .name = "usb_l4_ick", 2086 .name = "usb_l4_ick",
2082 .ops = &clkops_omap2_dflt_wait, 2087 .ops = &clkops_omap2_iclk_dflt_wait,
2083 .parent = &l4_ick, 2088 .parent = &l4_ick,
2084 .init = &omap2_init_clksel_parent, 2089 .init = &omap2_init_clksel_parent,
2085 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 2090 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -2101,7 +2106,7 @@ static struct clk security_l4_ick2 = {
2101 2106
2102static struct clk aes1_ick = { 2107static struct clk aes1_ick = {
2103 .name = "aes1_ick", 2108 .name = "aes1_ick",
2104 .ops = &clkops_omap2_dflt_wait, 2109 .ops = &clkops_omap2_iclk_dflt_wait,
2105 .parent = &security_l4_ick2, 2110 .parent = &security_l4_ick2,
2106 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2111 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2107 .enable_bit = OMAP3430_EN_AES1_SHIFT, 2112 .enable_bit = OMAP3430_EN_AES1_SHIFT,
@@ -2110,7 +2115,7 @@ static struct clk aes1_ick = {
2110 2115
2111static struct clk rng_ick = { 2116static struct clk rng_ick = {
2112 .name = "rng_ick", 2117 .name = "rng_ick",
2113 .ops = &clkops_omap2_dflt_wait, 2118 .ops = &clkops_omap2_iclk_dflt_wait,
2114 .parent = &security_l4_ick2, 2119 .parent = &security_l4_ick2,
2115 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2120 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2116 .enable_bit = OMAP3430_EN_RNG_SHIFT, 2121 .enable_bit = OMAP3430_EN_RNG_SHIFT,
@@ -2119,7 +2124,7 @@ static struct clk rng_ick = {
2119 2124
2120static struct clk sha11_ick = { 2125static struct clk sha11_ick = {
2121 .name = "sha11_ick", 2126 .name = "sha11_ick",
2122 .ops = &clkops_omap2_dflt_wait, 2127 .ops = &clkops_omap2_iclk_dflt_wait,
2123 .parent = &security_l4_ick2, 2128 .parent = &security_l4_ick2,
2124 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2129 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2125 .enable_bit = OMAP3430_EN_SHA11_SHIFT, 2130 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
@@ -2128,7 +2133,7 @@ static struct clk sha11_ick = {
2128 2133
2129static struct clk des1_ick = { 2134static struct clk des1_ick = {
2130 .name = "des1_ick", 2135 .name = "des1_ick",
2131 .ops = &clkops_omap2_dflt_wait, 2136 .ops = &clkops_omap2_iclk_dflt_wait,
2132 .parent = &security_l4_ick2, 2137 .parent = &security_l4_ick2,
2133 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 2138 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2134 .enable_bit = OMAP3430_EN_DES1_SHIFT, 2139 .enable_bit = OMAP3430_EN_DES1_SHIFT,
@@ -2189,7 +2194,7 @@ static struct clk dss2_alwon_fck = {
2189static struct clk dss_ick_3430es1 = { 2194static struct clk dss_ick_3430es1 = {
2190 /* Handles both L3 and L4 clocks */ 2195 /* Handles both L3 and L4 clocks */
2191 .name = "dss_ick", 2196 .name = "dss_ick",
2192 .ops = &clkops_omap2_dflt, 2197 .ops = &clkops_omap2_iclk_dflt,
2193 .parent = &l4_ick, 2198 .parent = &l4_ick,
2194 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2199 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2195 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, 2200 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@@ -2200,7 +2205,7 @@ static struct clk dss_ick_3430es1 = {
2200static struct clk dss_ick_3430es2 = { 2205static struct clk dss_ick_3430es2 = {
2201 /* Handles both L3 and L4 clocks */ 2206 /* Handles both L3 and L4 clocks */
2202 .name = "dss_ick", 2207 .name = "dss_ick",
2203 .ops = &clkops_omap3430es2_dss_usbhost_wait, 2208 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2204 .parent = &l4_ick, 2209 .parent = &l4_ick,
2205 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), 2210 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2206 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, 2211 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@@ -2223,7 +2228,7 @@ static struct clk cam_mclk = {
2223static struct clk cam_ick = { 2228static struct clk cam_ick = {
2224 /* Handles both L3 and L4 clocks */ 2229 /* Handles both L3 and L4 clocks */
2225 .name = "cam_ick", 2230 .name = "cam_ick",
2226 .ops = &clkops_omap2_dflt, 2231 .ops = &clkops_omap2_iclk_dflt,
2227 .parent = &l4_ick, 2232 .parent = &l4_ick,
2228 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), 2233 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2229 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2234 .enable_bit = OMAP3430_EN_CAM_SHIFT,
@@ -2266,7 +2271,7 @@ static struct clk usbhost_48m_fck = {
2266static struct clk usbhost_ick = { 2271static struct clk usbhost_ick = {
2267 /* Handles both L3 and L4 clocks */ 2272 /* Handles both L3 and L4 clocks */
2268 .name = "usbhost_ick", 2273 .name = "usbhost_ick",
2269 .ops = &clkops_omap3430es2_dss_usbhost_wait, 2274 .ops = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2270 .parent = &l4_ick, 2275 .parent = &l4_ick,
2271 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), 2276 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2272 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, 2277 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
@@ -2366,7 +2371,7 @@ static struct clk wkup_l4_ick = {
2366/* Never specifically named in the TRM, so we have to infer a likely name */ 2371/* Never specifically named in the TRM, so we have to infer a likely name */
2367static struct clk usim_ick = { 2372static struct clk usim_ick = {
2368 .name = "usim_ick", 2373 .name = "usim_ick",
2369 .ops = &clkops_omap2_dflt_wait, 2374 .ops = &clkops_omap2_iclk_dflt_wait,
2370 .parent = &wkup_l4_ick, 2375 .parent = &wkup_l4_ick,
2371 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2376 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2372 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, 2377 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
@@ -2376,7 +2381,7 @@ static struct clk usim_ick = {
2376 2381
2377static struct clk wdt2_ick = { 2382static struct clk wdt2_ick = {
2378 .name = "wdt2_ick", 2383 .name = "wdt2_ick",
2379 .ops = &clkops_omap2_dflt_wait, 2384 .ops = &clkops_omap2_iclk_dflt_wait,
2380 .parent = &wkup_l4_ick, 2385 .parent = &wkup_l4_ick,
2381 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2386 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2382 .enable_bit = OMAP3430_EN_WDT2_SHIFT, 2387 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
@@ -2386,7 +2391,7 @@ static struct clk wdt2_ick = {
2386 2391
2387static struct clk wdt1_ick = { 2392static struct clk wdt1_ick = {
2388 .name = "wdt1_ick", 2393 .name = "wdt1_ick",
2389 .ops = &clkops_omap2_dflt_wait, 2394 .ops = &clkops_omap2_iclk_dflt_wait,
2390 .parent = &wkup_l4_ick, 2395 .parent = &wkup_l4_ick,
2391 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2396 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2392 .enable_bit = OMAP3430_EN_WDT1_SHIFT, 2397 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
@@ -2396,7 +2401,7 @@ static struct clk wdt1_ick = {
2396 2401
2397static struct clk gpio1_ick = { 2402static struct clk gpio1_ick = {
2398 .name = "gpio1_ick", 2403 .name = "gpio1_ick",
2399 .ops = &clkops_omap2_dflt_wait, 2404 .ops = &clkops_omap2_iclk_dflt_wait,
2400 .parent = &wkup_l4_ick, 2405 .parent = &wkup_l4_ick,
2401 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2406 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2402 .enable_bit = OMAP3430_EN_GPIO1_SHIFT, 2407 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
@@ -2406,7 +2411,7 @@ static struct clk gpio1_ick = {
2406 2411
2407static struct clk omap_32ksync_ick = { 2412static struct clk omap_32ksync_ick = {
2408 .name = "omap_32ksync_ick", 2413 .name = "omap_32ksync_ick",
2409 .ops = &clkops_omap2_dflt_wait, 2414 .ops = &clkops_omap2_iclk_dflt_wait,
2410 .parent = &wkup_l4_ick, 2415 .parent = &wkup_l4_ick,
2411 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2416 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2412 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, 2417 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
@@ -2417,7 +2422,7 @@ static struct clk omap_32ksync_ick = {
2417/* XXX This clock no longer exists in 3430 TRM rev F */ 2422/* XXX This clock no longer exists in 3430 TRM rev F */
2418static struct clk gpt12_ick = { 2423static struct clk gpt12_ick = {
2419 .name = "gpt12_ick", 2424 .name = "gpt12_ick",
2420 .ops = &clkops_omap2_dflt_wait, 2425 .ops = &clkops_omap2_iclk_dflt_wait,
2421 .parent = &wkup_l4_ick, 2426 .parent = &wkup_l4_ick,
2422 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2427 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2423 .enable_bit = OMAP3430_EN_GPT12_SHIFT, 2428 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
@@ -2427,7 +2432,7 @@ static struct clk gpt12_ick = {
2427 2432
2428static struct clk gpt1_ick = { 2433static struct clk gpt1_ick = {
2429 .name = "gpt1_ick", 2434 .name = "gpt1_ick",
2430 .ops = &clkops_omap2_dflt_wait, 2435 .ops = &clkops_omap2_iclk_dflt_wait,
2431 .parent = &wkup_l4_ick, 2436 .parent = &wkup_l4_ick,
2432 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), 2437 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2433 .enable_bit = OMAP3430_EN_GPT1_SHIFT, 2438 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
@@ -2465,6 +2470,16 @@ static struct clk uart3_fck = {
2465 .recalc = &followparent_recalc, 2470 .recalc = &followparent_recalc,
2466}; 2471};
2467 2472
2473static struct clk uart4_fck = {
2474 .name = "uart4_fck",
2475 .ops = &clkops_omap2_dflt_wait,
2476 .parent = &per_48m_fck,
2477 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2478 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2479 .clkdm_name = "per_clkdm",
2480 .recalc = &followparent_recalc,
2481};
2482
2468static struct clk gpt2_fck = { 2483static struct clk gpt2_fck = {
2469 .name = "gpt2_fck", 2484 .name = "gpt2_fck",
2470 .ops = &clkops_omap2_dflt_wait, 2485 .ops = &clkops_omap2_dflt_wait,
@@ -2647,7 +2662,7 @@ static struct clk per_l4_ick = {
2647 2662
2648static struct clk gpio6_ick = { 2663static struct clk gpio6_ick = {
2649 .name = "gpio6_ick", 2664 .name = "gpio6_ick",
2650 .ops = &clkops_omap2_dflt_wait, 2665 .ops = &clkops_omap2_iclk_dflt_wait,
2651 .parent = &per_l4_ick, 2666 .parent = &per_l4_ick,
2652 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2667 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2653 .enable_bit = OMAP3430_EN_GPIO6_SHIFT, 2668 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
@@ -2657,7 +2672,7 @@ static struct clk gpio6_ick = {
2657 2672
2658static struct clk gpio5_ick = { 2673static struct clk gpio5_ick = {
2659 .name = "gpio5_ick", 2674 .name = "gpio5_ick",
2660 .ops = &clkops_omap2_dflt_wait, 2675 .ops = &clkops_omap2_iclk_dflt_wait,
2661 .parent = &per_l4_ick, 2676 .parent = &per_l4_ick,
2662 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2677 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2663 .enable_bit = OMAP3430_EN_GPIO5_SHIFT, 2678 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
@@ -2667,7 +2682,7 @@ static struct clk gpio5_ick = {
2667 2682
2668static struct clk gpio4_ick = { 2683static struct clk gpio4_ick = {
2669 .name = "gpio4_ick", 2684 .name = "gpio4_ick",
2670 .ops = &clkops_omap2_dflt_wait, 2685 .ops = &clkops_omap2_iclk_dflt_wait,
2671 .parent = &per_l4_ick, 2686 .parent = &per_l4_ick,
2672 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2687 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2673 .enable_bit = OMAP3430_EN_GPIO4_SHIFT, 2688 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
@@ -2677,7 +2692,7 @@ static struct clk gpio4_ick = {
2677 2692
2678static struct clk gpio3_ick = { 2693static struct clk gpio3_ick = {
2679 .name = "gpio3_ick", 2694 .name = "gpio3_ick",
2680 .ops = &clkops_omap2_dflt_wait, 2695 .ops = &clkops_omap2_iclk_dflt_wait,
2681 .parent = &per_l4_ick, 2696 .parent = &per_l4_ick,
2682 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2697 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2683 .enable_bit = OMAP3430_EN_GPIO3_SHIFT, 2698 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
@@ -2687,7 +2702,7 @@ static struct clk gpio3_ick = {
2687 2702
2688static struct clk gpio2_ick = { 2703static struct clk gpio2_ick = {
2689 .name = "gpio2_ick", 2704 .name = "gpio2_ick",
2690 .ops = &clkops_omap2_dflt_wait, 2705 .ops = &clkops_omap2_iclk_dflt_wait,
2691 .parent = &per_l4_ick, 2706 .parent = &per_l4_ick,
2692 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2707 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2693 .enable_bit = OMAP3430_EN_GPIO2_SHIFT, 2708 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
@@ -2697,7 +2712,7 @@ static struct clk gpio2_ick = {
2697 2712
2698static struct clk wdt3_ick = { 2713static struct clk wdt3_ick = {
2699 .name = "wdt3_ick", 2714 .name = "wdt3_ick",
2700 .ops = &clkops_omap2_dflt_wait, 2715 .ops = &clkops_omap2_iclk_dflt_wait,
2701 .parent = &per_l4_ick, 2716 .parent = &per_l4_ick,
2702 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2717 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2703 .enable_bit = OMAP3430_EN_WDT3_SHIFT, 2718 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
@@ -2707,7 +2722,7 @@ static struct clk wdt3_ick = {
2707 2722
2708static struct clk uart3_ick = { 2723static struct clk uart3_ick = {
2709 .name = "uart3_ick", 2724 .name = "uart3_ick",
2710 .ops = &clkops_omap2_dflt_wait, 2725 .ops = &clkops_omap2_iclk_dflt_wait,
2711 .parent = &per_l4_ick, 2726 .parent = &per_l4_ick,
2712 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2727 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2713 .enable_bit = OMAP3430_EN_UART3_SHIFT, 2728 .enable_bit = OMAP3430_EN_UART3_SHIFT,
@@ -2715,9 +2730,19 @@ static struct clk uart3_ick = {
2715 .recalc = &followparent_recalc, 2730 .recalc = &followparent_recalc,
2716}; 2731};
2717 2732
2733static struct clk uart4_ick = {
2734 .name = "uart4_ick",
2735 .ops = &clkops_omap2_iclk_dflt_wait,
2736 .parent = &per_l4_ick,
2737 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2738 .enable_bit = OMAP3630_EN_UART4_SHIFT,
2739 .clkdm_name = "per_clkdm",
2740 .recalc = &followparent_recalc,
2741};
2742
2718static struct clk gpt9_ick = { 2743static struct clk gpt9_ick = {
2719 .name = "gpt9_ick", 2744 .name = "gpt9_ick",
2720 .ops = &clkops_omap2_dflt_wait, 2745 .ops = &clkops_omap2_iclk_dflt_wait,
2721 .parent = &per_l4_ick, 2746 .parent = &per_l4_ick,
2722 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2747 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2723 .enable_bit = OMAP3430_EN_GPT9_SHIFT, 2748 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
@@ -2727,7 +2752,7 @@ static struct clk gpt9_ick = {
2727 2752
2728static struct clk gpt8_ick = { 2753static struct clk gpt8_ick = {
2729 .name = "gpt8_ick", 2754 .name = "gpt8_ick",
2730 .ops = &clkops_omap2_dflt_wait, 2755 .ops = &clkops_omap2_iclk_dflt_wait,
2731 .parent = &per_l4_ick, 2756 .parent = &per_l4_ick,
2732 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2757 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2733 .enable_bit = OMAP3430_EN_GPT8_SHIFT, 2758 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
@@ -2737,7 +2762,7 @@ static struct clk gpt8_ick = {
2737 2762
2738static struct clk gpt7_ick = { 2763static struct clk gpt7_ick = {
2739 .name = "gpt7_ick", 2764 .name = "gpt7_ick",
2740 .ops = &clkops_omap2_dflt_wait, 2765 .ops = &clkops_omap2_iclk_dflt_wait,
2741 .parent = &per_l4_ick, 2766 .parent = &per_l4_ick,
2742 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2767 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2743 .enable_bit = OMAP3430_EN_GPT7_SHIFT, 2768 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
@@ -2747,7 +2772,7 @@ static struct clk gpt7_ick = {
2747 2772
2748static struct clk gpt6_ick = { 2773static struct clk gpt6_ick = {
2749 .name = "gpt6_ick", 2774 .name = "gpt6_ick",
2750 .ops = &clkops_omap2_dflt_wait, 2775 .ops = &clkops_omap2_iclk_dflt_wait,
2751 .parent = &per_l4_ick, 2776 .parent = &per_l4_ick,
2752 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2777 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2753 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2778 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
@@ -2757,7 +2782,7 @@ static struct clk gpt6_ick = {
2757 2782
2758static struct clk gpt5_ick = { 2783static struct clk gpt5_ick = {
2759 .name = "gpt5_ick", 2784 .name = "gpt5_ick",
2760 .ops = &clkops_omap2_dflt_wait, 2785 .ops = &clkops_omap2_iclk_dflt_wait,
2761 .parent = &per_l4_ick, 2786 .parent = &per_l4_ick,
2762 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2787 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2763 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2788 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
@@ -2767,7 +2792,7 @@ static struct clk gpt5_ick = {
2767 2792
2768static struct clk gpt4_ick = { 2793static struct clk gpt4_ick = {
2769 .name = "gpt4_ick", 2794 .name = "gpt4_ick",
2770 .ops = &clkops_omap2_dflt_wait, 2795 .ops = &clkops_omap2_iclk_dflt_wait,
2771 .parent = &per_l4_ick, 2796 .parent = &per_l4_ick,
2772 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2797 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2773 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2798 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
@@ -2777,7 +2802,7 @@ static struct clk gpt4_ick = {
2777 2802
2778static struct clk gpt3_ick = { 2803static struct clk gpt3_ick = {
2779 .name = "gpt3_ick", 2804 .name = "gpt3_ick",
2780 .ops = &clkops_omap2_dflt_wait, 2805 .ops = &clkops_omap2_iclk_dflt_wait,
2781 .parent = &per_l4_ick, 2806 .parent = &per_l4_ick,
2782 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2807 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2783 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2808 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
@@ -2787,7 +2812,7 @@ static struct clk gpt3_ick = {
2787 2812
2788static struct clk gpt2_ick = { 2813static struct clk gpt2_ick = {
2789 .name = "gpt2_ick", 2814 .name = "gpt2_ick",
2790 .ops = &clkops_omap2_dflt_wait, 2815 .ops = &clkops_omap2_iclk_dflt_wait,
2791 .parent = &per_l4_ick, 2816 .parent = &per_l4_ick,
2792 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2817 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2793 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2818 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
@@ -2797,7 +2822,7 @@ static struct clk gpt2_ick = {
2797 2822
2798static struct clk mcbsp2_ick = { 2823static struct clk mcbsp2_ick = {
2799 .name = "mcbsp2_ick", 2824 .name = "mcbsp2_ick",
2800 .ops = &clkops_omap2_dflt_wait, 2825 .ops = &clkops_omap2_iclk_dflt_wait,
2801 .parent = &per_l4_ick, 2826 .parent = &per_l4_ick,
2802 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2827 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2803 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2828 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2807,7 +2832,7 @@ static struct clk mcbsp2_ick = {
2807 2832
2808static struct clk mcbsp3_ick = { 2833static struct clk mcbsp3_ick = {
2809 .name = "mcbsp3_ick", 2834 .name = "mcbsp3_ick",
2810 .ops = &clkops_omap2_dflt_wait, 2835 .ops = &clkops_omap2_iclk_dflt_wait,
2811 .parent = &per_l4_ick, 2836 .parent = &per_l4_ick,
2812 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2837 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2813 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2838 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2817,7 +2842,7 @@ static struct clk mcbsp3_ick = {
2817 2842
2818static struct clk mcbsp4_ick = { 2843static struct clk mcbsp4_ick = {
2819 .name = "mcbsp4_ick", 2844 .name = "mcbsp4_ick",
2820 .ops = &clkops_omap2_dflt_wait, 2845 .ops = &clkops_omap2_iclk_dflt_wait,
2821 .parent = &per_l4_ick, 2846 .parent = &per_l4_ick,
2822 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2847 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2823 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2848 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
@@ -3024,6 +3049,7 @@ static struct clk sr1_fck = {
3024 .parent = &sys_ck, 3049 .parent = &sys_ck,
3025 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 3050 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3026 .enable_bit = OMAP3430_EN_SR1_SHIFT, 3051 .enable_bit = OMAP3430_EN_SR1_SHIFT,
3052 .clkdm_name = "wkup_clkdm",
3027 .recalc = &followparent_recalc, 3053 .recalc = &followparent_recalc,
3028}; 3054};
3029 3055
@@ -3034,6 +3060,7 @@ static struct clk sr2_fck = {
3034 .parent = &sys_ck, 3060 .parent = &sys_ck,
3035 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), 3061 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3036 .enable_bit = OMAP3430_EN_SR2_SHIFT, 3062 .enable_bit = OMAP3430_EN_SR2_SHIFT,
3063 .clkdm_name = "wkup_clkdm",
3037 .recalc = &followparent_recalc, 3064 .recalc = &followparent_recalc,
3038}; 3065};
3039 3066
@@ -3158,7 +3185,7 @@ static struct clk vpfe_fck = {
3158 */ 3185 */
3159static struct clk uart4_ick_am35xx = { 3186static struct clk uart4_ick_am35xx = {
3160 .name = "uart4_ick", 3187 .name = "uart4_ick",
3161 .ops = &clkops_omap2_dflt_wait, 3188 .ops = &clkops_omap2_iclk_dflt_wait,
3162 .parent = &core_l4_ick, 3189 .parent = &core_l4_ick,
3163 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 3190 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3164 .enable_bit = AM35XX_EN_UART4_SHIFT, 3191 .enable_bit = AM35XX_EN_UART4_SHIFT,
@@ -3181,20 +3208,25 @@ static struct omap_clk omap3xxx_clks[] = {
3181 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX), 3208 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_3XXX),
3182 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX), 3209 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_3XXX),
3183 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX), 3210 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_3XXX),
3184 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX), 3211 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3185 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX), 3212 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3186 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX), 3213 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_3XXX),
3187 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX), 3214 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3188 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), 3215 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX),
3189 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), 3216 CLK(NULL, "sys_ck", &sys_ck, CK_3XXX),
3190 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), 3217 CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX),
3218 CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX),
3219 CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX),
3220 CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX),
3221 CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX),
3222 CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX),
3191 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), 3223 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX),
3192 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), 3224 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX),
3193 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), 3225 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX),
3194 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX), 3226 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_3XXX),
3195 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX), 3227 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3196 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), 3228 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_34XX | CK_36XX),
3197 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), 3229 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_34XX | CK_36XX),
3198 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX), 3230 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_3XXX),
3199 CLK(NULL, "core_ck", &core_ck, CK_3XXX), 3231 CLK(NULL, "core_ck", &core_ck, CK_3XXX),
3200 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX), 3232 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_3XXX),
@@ -3223,8 +3255,8 @@ static struct omap_clk omap3xxx_clks[] = {
3223 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX), 3255 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_3XXX),
3224 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX), 3256 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3225 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX), 3257 CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3226 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2 | CK_AM35XX), 3258 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3227 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2 | CK_AM35XX), 3259 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3228 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), 3260 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3229 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), 3261 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX),
3230 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), 3262 CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX),
@@ -3232,8 +3264,8 @@ static struct omap_clk omap3xxx_clks[] = {
3232 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), 3264 CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX),
3233 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), 3265 CLK(NULL, "arm_fck", &arm_fck, CK_3XXX),
3234 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), 3266 CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3235 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), 3267 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX),
3236 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), 3268 CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX),
3237 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), 3269 CLK(NULL, "l3_ick", &l3_ick, CK_3XXX),
3238 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), 3270 CLK(NULL, "l4_ick", &l4_ick, CK_3XXX),
3239 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX), 3271 CLK(NULL, "rm_ick", &rm_ick, CK_3XXX),
@@ -3242,25 +3274,28 @@ static struct omap_clk omap3xxx_clks[] = {
3242 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), 3274 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
3243 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), 3275 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
3244 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), 3276 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
3245 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2 | CK_3517), 3277 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2PLUS | CK_3517 | CK_36XX),
3246 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2 | CK_3517), 3278 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2PLUS | CK_3517 | CK_36XX),
3247 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), 3279 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
3248 CLK(NULL, "modem_fck", &modem_fck, CK_343X), 3280 CLK(NULL, "modem_fck", &modem_fck, CK_34XX | CK_36XX),
3249 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X), 3281 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_34XX | CK_36XX),
3250 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X), 3282 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_34XX | CK_36XX),
3251 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX), 3283 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_3XXX),
3252 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX), 3284 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_3XXX),
3253 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2 | CK_AM35XX), 3285 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3254 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2 | CK_AM35XX), 3286 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3255 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2 | CK_AM35XX), 3287 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3288 CLK("usbhs-omap.0", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3289 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3290 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3256 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3291 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3257 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2 | CK_AM35XX), 3292 CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3258 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), 3293 CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX),
3259 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), 3294 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3260 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), 3295 CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX),
3261 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_3XXX), 3296 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX),
3262 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_3XXX), 3297 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX),
3263 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_3XXX), 3298 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX),
3264 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX), 3299 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX),
3265 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX), 3300 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX),
3266 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX), 3301 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
@@ -3274,34 +3309,35 @@ static struct omap_clk omap3xxx_clks[] = {
3274 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX), 3309 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
3275 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX), 3310 CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
3276 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1), 3311 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
3277 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2), 3312 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3278 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1), 3313 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
3279 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2), 3314 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
3280 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX), 3315 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_3XXX),
3281 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1), 3316 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
3282 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2), 3317 CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3283 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX), 3318 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_3XXX),
3284 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX), 3319 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_3XXX),
3285 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), 3320 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3286 CLK(NULL, "pka_ick", &pka_ick, CK_343X), 3321 CLK(NULL, "pka_ick", &pka_ick, CK_34XX | CK_36XX),
3287 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), 3322 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3288 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2 | CK_AM35XX), 3323 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3289 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2 | CK_AM35XX), 3324 CLK("usbhs-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3290 CLK(NULL, "icr_ick", &icr_ick, CK_343X), 3325 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3291 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), 3326 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3292 CLK("omap-sham", "ick", &sha12_ick, CK_343X), 3327 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3293 CLK(NULL, "des2_ick", &des2_ick, CK_343X), 3328 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3294 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), 3329 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3295 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), 3330 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
3296 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), 3331 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
3332 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3297 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), 3333 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3298 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), 3334 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
3299 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX), 3335 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_3XXX),
3300 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX), 3336 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_3XXX),
3301 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX), 3337 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_3XXX),
3302 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_3XXX), 3338 CLK("omap_i2c.3", "ick", &i2c3_ick, CK_3XXX),
3303 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_3XXX), 3339 CLK("omap_i2c.2", "ick", &i2c2_ick, CK_3XXX),
3304 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_3XXX), 3340 CLK("omap_i2c.1", "ick", &i2c1_ick, CK_3XXX),
3305 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX), 3341 CLK(NULL, "uart2_ick", &uart2_ick, CK_3XXX),
3306 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX), 3342 CLK(NULL, "uart1_ick", &uart1_ick, CK_3XXX),
3307 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX), 3343 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_3XXX),
@@ -3309,46 +3345,62 @@ static struct omap_clk omap3xxx_clks[] = {
3309 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX), 3345 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_3XXX),
3310 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX), 3346 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_3XXX),
3311 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), 3347 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
3312 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), 3348 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3313 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX), 3349 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_3XXX),
3314 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), 3350 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_34XX | CK_36XX),
3315 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1), 3351 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
3316 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2), 3352 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2PLUS | CK_36XX),
3317 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), 3353 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
3318 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), 3354 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3319 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), 3355 CLK(NULL, "aes1_ick", &aes1_ick, CK_34XX | CK_36XX),
3320 CLK("omap_rng", "ick", &rng_ick, CK_343X), 3356 CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
3321 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), 3357 CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
3322 CLK(NULL, "des1_ick", &des1_ick, CK_343X), 3358 CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
3323 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1), 3359 CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
3324 CLK("omapdss", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX), 3360 CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3325 CLK("omapdss", "tv_fck", &dss_tv_fck, CK_3XXX), 3361 CLK("omapdss_dss", "tv_clk", &dss_tv_fck, CK_3XXX),
3326 CLK("omapdss", "video_fck", &dss_96m_fck, CK_3XXX), 3362 CLK("omapdss_dss", "video_clk", &dss_96m_fck, CK_3XXX),
3327 CLK("omapdss", "dss2_fck", &dss2_alwon_fck, CK_3XXX), 3363 CLK("omapdss_dss", "sys_clk", &dss2_alwon_fck, CK_3XXX),
3328 CLK("omapdss", "ick", &dss_ick_3430es1, CK_3430ES1), 3364 CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
3329 CLK("omapdss", "ick", &dss_ick_3430es2, CK_3430ES2 | CK_AM35XX), 3365 CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3330 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), 3366 CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
3331 CLK(NULL, "cam_ick", &cam_ick, CK_343X), 3367 CLK(NULL, "cam_ick", &cam_ick, CK_34XX | CK_36XX),
3332 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), 3368 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_34XX | CK_36XX),
3333 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX), 3369 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3334 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX), 3370 CLK("usbhs-omap.0", "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3335 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2 | CK_AM35XX), 3371 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3336 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), 3372 CLK("usbhs-omap.0", "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3373 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3374 CLK("usbhs-omap.0", "usbhost_ick", &usbhost_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3375 CLK("usbhs-omap.0", "utmi_p1_gfclk", &dummy_ck, CK_3XXX),
3376 CLK("usbhs-omap.0", "utmi_p2_gfclk", &dummy_ck, CK_3XXX),
3377 CLK("usbhs-omap.0", "xclk60mhsp1_ck", &dummy_ck, CK_3XXX),
3378 CLK("usbhs-omap.0", "xclk60mhsp2_ck", &dummy_ck, CK_3XXX),
3379 CLK("usbhs-omap.0", "usb_host_hs_utmi_p1_clk", &dummy_ck, CK_3XXX),
3380 CLK("usbhs-omap.0", "usb_host_hs_utmi_p2_clk", &dummy_ck, CK_3XXX),
3381 CLK("usbhs-omap.0", "usb_tll_hs_usb_ch0_clk", &dummy_ck, CK_3XXX),
3382 CLK("usbhs-omap.0", "usb_tll_hs_usb_ch1_clk", &dummy_ck, CK_3XXX),
3383 CLK("usbhs-omap.0", "init_60m_fclk", &dummy_ck, CK_3XXX),
3384 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2PLUS | CK_36XX),
3337 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX), 3385 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
3338 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX), 3386 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
3339 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX), 3387 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
3340 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX), 3388 CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
3341 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), 3389 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
3342 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), 3390 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
3343 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX), 3391 CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
3344 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX), 3392 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_3XXX),
3345 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX), 3393 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_3XXX),
3346 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), 3394 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3347 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), 3395 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX),
3348 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), 3396 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX),
3397 CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX),
3398 CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX),
3399 CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX),
3349 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), 3400 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX),
3350 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), 3401 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX),
3351 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), 3402 CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX),
3403 CLK(NULL, "uart4_fck", &uart4_fck, CK_36XX),
3352 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX), 3404 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_3XXX),
3353 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX), 3405 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_3XXX),
3354 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX), 3406 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_3XXX),
@@ -3372,6 +3424,7 @@ static struct omap_clk omap3xxx_clks[] = {
3372 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX), 3424 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_3XXX),
3373 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX), 3425 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_3XXX),
3374 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX), 3426 CLK(NULL, "uart3_ick", &uart3_ick, CK_3XXX),
3427 CLK(NULL, "uart4_ick", &uart4_ick, CK_36XX),
3375 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX), 3428 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_3XXX),
3376 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX), 3429 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_3XXX),
3377 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX), 3430 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_3XXX),
@@ -3392,9 +3445,9 @@ static struct omap_clk omap3xxx_clks[] = {
3392 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX), 3445 CLK(NULL, "atclk_fck", &atclk_fck, CK_3XXX),
3393 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX), 3446 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3394 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX), 3447 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_3XXX),
3395 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), 3448 CLK(NULL, "sr1_fck", &sr1_fck, CK_34XX | CK_36XX),
3396 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), 3449 CLK(NULL, "sr2_fck", &sr2_fck, CK_34XX | CK_36XX),
3397 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), 3450 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_34XX | CK_36XX),
3398 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), 3451 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3399 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), 3452 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX),
3400 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), 3453 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX),
@@ -3405,8 +3458,8 @@ static struct omap_clk omap3xxx_clks[] = {
3405 CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX), 3458 CLK("davinci_emac", "phy_clk", &emac_fck, CK_AM35XX),
3406 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), 3459 CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX),
3407 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), 3460 CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX),
3408 CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), 3461 CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX),
3409 CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), 3462 CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX),
3410 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), 3463 CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
3411 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), 3464 CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX),
3412}; 3465};
@@ -3415,38 +3468,40 @@ static struct omap_clk omap3xxx_clks[] = {
3415int __init omap3xxx_clk_init(void) 3468int __init omap3xxx_clk_init(void)
3416{ 3469{
3417 struct omap_clk *c; 3470 struct omap_clk *c;
3418 u32 cpu_clkflg = CK_3XXX; 3471 u32 cpu_clkflg = 0;
3419 3472
3420 if (cpu_is_omap3517()) { 3473 if (cpu_is_omap3517()) {
3421 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; 3474 cpu_mask = RATE_IN_34XX;
3422 cpu_clkflg |= CK_3517; 3475 cpu_clkflg = CK_3517;
3423 } else if (cpu_is_omap3505()) { 3476 } else if (cpu_is_omap3505()) {
3424 cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS; 3477 cpu_mask = RATE_IN_34XX;
3425 cpu_clkflg |= CK_3505; 3478 cpu_clkflg = CK_3505;
3479 } else if (cpu_is_omap3630()) {
3480 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3481 cpu_clkflg = CK_36XX;
3482 } else if (cpu_is_ti816x()) {
3483 cpu_mask = RATE_IN_TI816X;
3484 cpu_clkflg = CK_TI816X;
3426 } else if (cpu_is_omap34xx()) { 3485 } else if (cpu_is_omap34xx()) {
3427 cpu_mask = RATE_IN_3XXX;
3428 cpu_clkflg |= CK_343X;
3429
3430 /*
3431 * Update this if there are further clock changes between ES2
3432 * and production parts
3433 */
3434 if (omap_rev() == OMAP3430_REV_ES1_0) { 3486 if (omap_rev() == OMAP3430_REV_ES1_0) {
3435 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ 3487 cpu_mask = RATE_IN_3430ES1;
3436 cpu_clkflg |= CK_3430ES1; 3488 cpu_clkflg = CK_3430ES1;
3437 } else { 3489 } else {
3438 cpu_mask |= RATE_IN_3430ES2PLUS; 3490 /*
3439 cpu_clkflg |= CK_3430ES2; 3491 * Assume that anything that we haven't matched yet
3492 * has 3430ES2-type clocks.
3493 */
3494 cpu_mask = RATE_IN_3430ES2PLUS;
3495 cpu_clkflg = CK_3430ES2PLUS;
3440 } 3496 }
3497 } else {
3498 WARN(1, "clock: could not identify OMAP3 variant\n");
3441 } 3499 }
3442 3500
3443 if (omap3_has_192mhz_clk()) 3501 if (omap3_has_192mhz_clk())
3444 omap_96m_alwon_fck = omap_96m_alwon_fck_3630; 3502 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3445 3503
3446 if (cpu_is_omap3630()) { 3504 if (cpu_is_omap3630()) {
3447 cpu_mask |= RATE_IN_36XX;
3448 cpu_clkflg |= CK_36XX;
3449
3450 /* 3505 /*
3451 * XXX This type of dynamic rewriting of the clock tree is 3506 * XXX This type of dynamic rewriting of the clock tree is
3452 * deprecated and should be revised soon. 3507 * deprecated and should be revised soon.
@@ -3491,12 +3546,14 @@ int __init omap3xxx_clk_init(void)
3491 omap2_init_clk_clkdm(c->lk.clk); 3546 omap2_init_clk_clkdm(c->lk.clk);
3492 } 3547 }
3493 3548
3549 /* Disable autoidle on all clocks; let the PM code enable it later */
3550 omap_clk_disable_autoidle_all();
3551
3494 recalculate_root_clocks(); 3552 recalculate_root_clocks();
3495 3553
3496 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): " 3554 pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3497 "%ld.%01ld/%ld/%ld MHz\n", 3555 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3498 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, 3556 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3499 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3500 3557
3501 /* 3558 /*
3502 * Only enable those clocks we will need, let the drivers 3559 * Only enable those clocks we will need, let the drivers
@@ -3505,9 +3562,10 @@ int __init omap3xxx_clk_init(void)
3505 clk_enable_init_clocks(); 3562 clk_enable_init_clocks();
3506 3563
3507 /* 3564 /*
3508 * Lock DPLL5 and put it in autoidle. 3565 * Lock DPLL5 -- here only until other device init code can
3566 * handle this
3509 */ 3567 */
3510 if (omap_rev() >= OMAP3430_REV_ES2_0) 3568 if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
3511 omap3_clk_lock_dpll5(); 3569 omap3_clk_lock_dpll5();
3512 3570
3513 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */ 3571 /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-13 07:23:08 -0400