OMAP2/3/4 clock: rename and clean the omap2_clk_init() functions

Rename the omap2_clk_init() in the OMAP2, 3, and 4 clock code to be
omap2xxx_clk_init(), omap3xxx_clk_init(), etc.  Remove all traces of
the (commented) old virt_prcm_set code from omap3xxx_clk_init() and
omap4xxx_clk_init(), since this will be handled with the OPP code that
is cooking in the PM branch.

After this patch, there should be very little else in the clock code
that blocks a multi-OMAP 2+3 kernel.  (OMAP2420+OMAP2430 still has some
outstanding issues that need to be resolved; this is pending on some
additions to the hwmod data.)

Signed-off-by: Paul Walmsley <paul@pwsan.com>

1 files changed, 1 insertions, 18 deletions

diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c
index 9e7f68a8fca2..0d04f92f63e1 100644
--- a/arch/arm/mach-omap2/clock34xx_data.c
+++ b/arch/arm/mach-omap2/clock34xx_data.c
@@ -3212,11 +3212,9 @@ static struct omap_clk omap3xxx_clks[] = {
 };
 
 
-int __init omap2_clk_init(void)
+int __init omap3xxx_clk_init(void)
 {
-        /* struct prcm_config *prcm; */
         struct omap_clk *c;
-        /* u32 clkrate; */
         u32 cpu_clkflg = CK_3XXX;
 
         if (cpu_is_omap3517()) {
@@ -3254,21 +3252,6 @@ int __init omap2_clk_init(void)
                         omap2_init_clk_clkdm(c->lk.clk);
                 }
 
-        /* REVISIT: Not yet ready for OMAP3 */
-#if 0
-        /* Check the MPU rate set by bootloader */
-        clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
-        for (prcm = rate_table; prcm->mpu_speed; prcm++) {
-                if (!(prcm->flags & cpu_mask))
-                        continue;
-                if (prcm->xtal_speed != sys_ck.rate)
-                        continue;
-                if (prcm->dpll_speed <= clkrate)
-                        break;
-        }
-        curr_prcm_set = prcm;
-#endif
-
         recalculate_root_clocks();
 
         printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "