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authorPaul Walmsley <paul@pwsan.com>2010-02-23 00:09:22 -0500
committerPaul Walmsley <paul@pwsan.com>2010-02-24 14:29:42 -0500
commit81b34fbecbfbf24ed95c2d80d5cb14149652408f (patch)
treeb29a0d117a7dda644e6d37931a7999095aeeaf69 /arch/arm/mach-omap2/clock2430_data.c
parent657ebfadc19c5a14f709dee1645082828330d5d4 (diff)
OMAP2 clock: split OMAP2420, OMAP2430 clock data into their own files
In preparation for multi-OMAP2 kernels, split mach-omap2/clock2xxx_data.c into mach-omap2/clock2420_data.c and mach-omap2/clock2430_data.c. 2430 uses a different device space physical memory layout than past or future OMAPs, and we use a different virtual memory layout as well, which causes trouble for architecture-level code/data that tries to support both. We tried using offsets from the virtual base last year, but those patches never made it upstream; so after some discussion with Tony about the best all-around approach, we'll just grit our teeth and duplicate the structures. The maintenance advantages of a single kernel config that can compile and boot on OMAP2, 3, and 4 platforms are simply too compelling. This approach does have some nice benefits beyond multi-OMAP 2 kernel support. The runtime size of OMAP2420-specific and OMAP2430-specific kernels is smaller, since unused clocks for the other OMAP2 chip will no longer be compiled in. (At some point we will mark the clock data __initdata and allocate it during registration, which will eliminate the runtime memory advantage.) It also makes the clock trees slightly easier to read, since 2420-specific and 2430-specific clocks are no longer mixed together. This patch also splits 2430-specific clock code into its own file, mach-omap2/clock2430.c, which is only compiled in for 2430 builds - mostly for organizational clarity. While here, fix a bug in the OMAP2430 clock tree: "emul_ck" was incorrectly marked as being 2420-only, when actually it is present on both OMAP2420 and OMAP2430. Thanks to Tony for some good discussions about how to approach this problem. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Richard Woodruff <r-woodruff2@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock2430_data.c')
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c2031
1 files changed, 2031 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
new file mode 100644
index 000000000000..9b9470e51e04
--- /dev/null
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -0,0 +1,2031 @@
1/*
2 * linux/arch/arm/mach-omap2/clock2430_data.c
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/list.h>
19
20#include <plat/clkdev_omap.h>
21
22#include "clock.h"
23#include "clock2xxx.h"
24#include "opp2xxx.h"
25#include "prm.h"
26#include "cm.h"
27#include "prm-regbits-24xx.h"
28#include "cm-regbits-24xx.h"
29#include "sdrc.h"
30
31#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
32
33/*
34 * 2430 clock tree.
35 *
36 * NOTE:In many cases here we are assigning a 'default' parent. In many
37 * cases the parent is selectable. The get/set parent calls will also
38 * switch sources.
39 *
40 * Many some clocks say always_enabled, but they can be auto idled for
41 * power savings. They will always be available upon clock request.
42 *
43 * Several sources are given initial rates which may be wrong, this will
44 * be fixed up in the init func.
45 *
46 * Things are broadly separated below by clock domains. It is
47 * noteworthy that most periferals have dependencies on multiple clock
48 * domains. Many get their interface clocks from the L4 domain, but get
49 * functional clocks from fixed sources or other core domain derived
50 * clocks.
51 */
52
53/* Base external input clocks */
54static struct clk func_32k_ck = {
55 .name = "func_32k_ck",
56 .ops = &clkops_null,
57 .rate = 32000,
58 .flags = RATE_FIXED,
59 .clkdm_name = "wkup_clkdm",
60};
61
62static struct clk secure_32k_ck = {
63 .name = "secure_32k_ck",
64 .ops = &clkops_null,
65 .rate = 32768,
66 .flags = RATE_FIXED,
67 .clkdm_name = "wkup_clkdm",
68};
69
70/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
71static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
72 .name = "osc_ck",
73 .ops = &clkops_oscck,
74 .clkdm_name = "wkup_clkdm",
75 .recalc = &omap2_osc_clk_recalc,
76};
77
78/* Without modem likely 12MHz, with modem likely 13MHz */
79static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */
80 .name = "sys_ck", /* ~ ref_clk also */
81 .ops = &clkops_null,
82 .parent = &osc_ck,
83 .clkdm_name = "wkup_clkdm",
84 .recalc = &omap2xxx_sys_clk_recalc,
85};
86
87static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
88 .name = "alt_ck",
89 .ops = &clkops_null,
90 .rate = 54000000,
91 .flags = RATE_FIXED,
92 .clkdm_name = "wkup_clkdm",
93};
94
95/*
96 * Analog domain root source clocks
97 */
98
99/* dpll_ck, is broken out in to special cases through clksel */
100/* REVISIT: Rate changes on dpll_ck trigger a full set change. ...
101 * deal with this
102 */
103
104static struct dpll_data dpll_dd = {
105 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
106 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
107 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
108 .clk_bypass = &sys_ck,
109 .clk_ref = &sys_ck,
110 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
111 .enable_mask = OMAP24XX_EN_DPLL_MASK,
112 .max_multiplier = 1023,
113 .min_divider = 1,
114 .max_divider = 16,
115 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
116};
117
118/*
119 * XXX Cannot add round_rate here yet, as this is still a composite clock,
120 * not just a DPLL
121 */
122static struct clk dpll_ck = {
123 .name = "dpll_ck",
124 .ops = &clkops_null,
125 .parent = &sys_ck, /* Can be func_32k also */
126 .dpll_data = &dpll_dd,
127 .clkdm_name = "wkup_clkdm",
128 .recalc = &omap2_dpllcore_recalc,
129 .set_rate = &omap2_reprogram_dpllcore,
130};
131
132static struct clk apll96_ck = {
133 .name = "apll96_ck",
134 .ops = &clkops_apll96,
135 .parent = &sys_ck,
136 .rate = 96000000,
137 .flags = RATE_FIXED | ENABLE_ON_INIT,
138 .clkdm_name = "wkup_clkdm",
139 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
140 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
141};
142
143static struct clk apll54_ck = {
144 .name = "apll54_ck",
145 .ops = &clkops_apll54,
146 .parent = &sys_ck,
147 .rate = 54000000,
148 .flags = RATE_FIXED | ENABLE_ON_INIT,
149 .clkdm_name = "wkup_clkdm",
150 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
151 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
152};
153
154/*
155 * PRCM digital base sources
156 */
157
158/* func_54m_ck */
159
160static const struct clksel_rate func_54m_apll54_rates[] = {
161 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
162 { .div = 0 },
163};
164
165static const struct clksel_rate func_54m_alt_rates[] = {
166 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
167 { .div = 0 },
168};
169
170static const struct clksel func_54m_clksel[] = {
171 { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
172 { .parent = &alt_ck, .rates = func_54m_alt_rates, },
173 { .parent = NULL },
174};
175
176static struct clk func_54m_ck = {
177 .name = "func_54m_ck",
178 .ops = &clkops_null,
179 .parent = &apll54_ck, /* can also be alt_clk */
180 .clkdm_name = "wkup_clkdm",
181 .init = &omap2_init_clksel_parent,
182 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
183 .clksel_mask = OMAP24XX_54M_SOURCE,
184 .clksel = func_54m_clksel,
185 .recalc = &omap2_clksel_recalc,
186};
187
188static struct clk core_ck = {
189 .name = "core_ck",
190 .ops = &clkops_null,
191 .parent = &dpll_ck, /* can also be 32k */
192 .clkdm_name = "wkup_clkdm",
193 .recalc = &followparent_recalc,
194};
195
196/* func_96m_ck */
197static const struct clksel_rate func_96m_apll96_rates[] = {
198 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
199 { .div = 0 },
200};
201
202static const struct clksel_rate func_96m_alt_rates[] = {
203 { .div = 1, .val = 1, .flags = RATE_IN_243X | DEFAULT_RATE },
204 { .div = 0 },
205};
206
207static const struct clksel func_96m_clksel[] = {
208 { .parent = &apll96_ck, .rates = func_96m_apll96_rates },
209 { .parent = &alt_ck, .rates = func_96m_alt_rates },
210 { .parent = NULL }
211};
212
213/* The parent of this clock is not selectable on 2420. */
214static struct clk func_96m_ck = {
215 .name = "func_96m_ck",
216 .ops = &clkops_null,
217 .parent = &apll96_ck,
218 .clkdm_name = "wkup_clkdm",
219 .init = &omap2_init_clksel_parent,
220 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
221 .clksel_mask = OMAP2430_96M_SOURCE,
222 .clksel = func_96m_clksel,
223 .recalc = &omap2_clksel_recalc,
224 .round_rate = &omap2_clksel_round_rate,
225 .set_rate = &omap2_clksel_set_rate
226};
227
228/* func_48m_ck */
229
230static const struct clksel_rate func_48m_apll96_rates[] = {
231 { .div = 2, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
232 { .div = 0 },
233};
234
235static const struct clksel_rate func_48m_alt_rates[] = {
236 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
237 { .div = 0 },
238};
239
240static const struct clksel func_48m_clksel[] = {
241 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
242 { .parent = &alt_ck, .rates = func_48m_alt_rates },
243 { .parent = NULL }
244};
245
246static struct clk func_48m_ck = {
247 .name = "func_48m_ck",
248 .ops = &clkops_null,
249 .parent = &apll96_ck, /* 96M or Alt */
250 .clkdm_name = "wkup_clkdm",
251 .init = &omap2_init_clksel_parent,
252 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
253 .clksel_mask = OMAP24XX_48M_SOURCE,
254 .clksel = func_48m_clksel,
255 .recalc = &omap2_clksel_recalc,
256 .round_rate = &omap2_clksel_round_rate,
257 .set_rate = &omap2_clksel_set_rate
258};
259
260static struct clk func_12m_ck = {
261 .name = "func_12m_ck",
262 .ops = &clkops_null,
263 .parent = &func_48m_ck,
264 .fixed_div = 4,
265 .clkdm_name = "wkup_clkdm",
266 .recalc = &omap_fixed_divisor_recalc,
267};
268
269/* Secure timer, only available in secure mode */
270static struct clk wdt1_osc_ck = {
271 .name = "ck_wdt1_osc",
272 .ops = &clkops_null, /* RMK: missing? */
273 .parent = &osc_ck,
274 .recalc = &followparent_recalc,
275};
276
277/*
278 * The common_clkout* clksel_rate structs are common to
279 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
280 * sys_clkout2_* are 2420-only, so the
281 * clksel_rate flags fields are inaccurate for those clocks. This is
282 * harmless since access to those clocks are gated by the struct clk
283 * flags fields, which mark them as 2420-only.
284 */
285static const struct clksel_rate common_clkout_src_core_rates[] = {
286 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
287 { .div = 0 }
288};
289
290static const struct clksel_rate common_clkout_src_sys_rates[] = {
291 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
292 { .div = 0 }
293};
294
295static const struct clksel_rate common_clkout_src_96m_rates[] = {
296 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
297 { .div = 0 }
298};
299
300static const struct clksel_rate common_clkout_src_54m_rates[] = {
301 { .div = 1, .val = 3, .flags = RATE_IN_24XX | DEFAULT_RATE },
302 { .div = 0 }
303};
304
305static const struct clksel common_clkout_src_clksel[] = {
306 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
307 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
308 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
309 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
310 { .parent = NULL }
311};
312
313static struct clk sys_clkout_src = {
314 .name = "sys_clkout_src",
315 .ops = &clkops_omap2_dflt,
316 .parent = &func_54m_ck,
317 .clkdm_name = "wkup_clkdm",
318 .enable_reg = OMAP2430_PRCM_CLKOUT_CTRL,
319 .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT,
320 .init = &omap2_init_clksel_parent,
321 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
322 .clksel_mask = OMAP24XX_CLKOUT_SOURCE_MASK,
323 .clksel = common_clkout_src_clksel,
324 .recalc = &omap2_clksel_recalc,
325 .round_rate = &omap2_clksel_round_rate,
326 .set_rate = &omap2_clksel_set_rate
327};
328
329static const struct clksel_rate common_clkout_rates[] = {
330 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
331 { .div = 2, .val = 1, .flags = RATE_IN_24XX },
332 { .div = 4, .val = 2, .flags = RATE_IN_24XX },
333 { .div = 8, .val = 3, .flags = RATE_IN_24XX },
334 { .div = 16, .val = 4, .flags = RATE_IN_24XX },
335 { .div = 0 },
336};
337
338static const struct clksel sys_clkout_clksel[] = {
339 { .parent = &sys_clkout_src, .rates = common_clkout_rates },
340 { .parent = NULL }
341};
342
343static struct clk sys_clkout = {
344 .name = "sys_clkout",
345 .ops = &clkops_null,
346 .parent = &sys_clkout_src,
347 .clkdm_name = "wkup_clkdm",
348 .clksel_reg = OMAP2430_PRCM_CLKOUT_CTRL,
349 .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK,
350 .clksel = sys_clkout_clksel,
351 .recalc = &omap2_clksel_recalc,
352 .round_rate = &omap2_clksel_round_rate,
353 .set_rate = &omap2_clksel_set_rate
354};
355
356static struct clk emul_ck = {
357 .name = "emul_ck",
358 .ops = &clkops_omap2_dflt,
359 .parent = &func_54m_ck,
360 .clkdm_name = "wkup_clkdm",
361 .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
362 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
363 .recalc = &followparent_recalc,
364
365};
366
367/*
368 * MPU clock domain
369 * Clocks:
370 * MPU_FCLK, MPU_ICLK
371 * INT_M_FCLK, INT_M_I_CLK
372 *
373 * - Individual clocks are hardware managed.
374 * - Base divider comes from: CM_CLKSEL_MPU
375 *
376 */
377static const struct clksel_rate mpu_core_rates[] = {
378 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
379 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
380 { .div = 0 },
381};
382
383static const struct clksel mpu_clksel[] = {
384 { .parent = &core_ck, .rates = mpu_core_rates },
385 { .parent = NULL }
386};
387
388static struct clk mpu_ck = { /* Control cpu */
389 .name = "mpu_ck",
390 .ops = &clkops_null,
391 .parent = &core_ck,
392 .flags = DELAYED_APP,
393 .clkdm_name = "mpu_clkdm",
394 .init = &omap2_init_clksel_parent,
395 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
396 .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK,
397 .clksel = mpu_clksel,
398 .recalc = &omap2_clksel_recalc,
399};
400
401/*
402 * DSP (2430-IVA2.1) clock domain
403 * Clocks:
404 * 2430: IVA2.1_FCLK (really just DSP_FCLK), IVA2.1_ICLK
405 *
406 * Won't be too specific here. The core clock comes into this block
407 * it is divided then tee'ed. One branch goes directly to xyz enable
408 * controls. The other branch gets further divided by 2 then possibly
409 * routed into a synchronizer and out of clocks abc.
410 */
411static const struct clksel_rate dsp_fck_core_rates[] = {
412 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
413 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
414 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
415 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
416 { .div = 0 },
417};
418
419static const struct clksel dsp_fck_clksel[] = {
420 { .parent = &core_ck, .rates = dsp_fck_core_rates },
421 { .parent = NULL }
422};
423
424static struct clk dsp_fck = {
425 .name = "dsp_fck",
426 .ops = &clkops_omap2_dflt_wait,
427 .parent = &core_ck,
428 .flags = DELAYED_APP,
429 .clkdm_name = "dsp_clkdm",
430 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
431 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
432 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
433 .clksel_mask = OMAP24XX_CLKSEL_DSP_MASK,
434 .clksel = dsp_fck_clksel,
435 .recalc = &omap2_clksel_recalc,
436};
437
438/* DSP interface clock */
439static const struct clksel_rate dsp_irate_ick_rates[] = {
440 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
441 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
442 { .div = 3, .val = 3, .flags = RATE_IN_243X },
443 { .div = 0 },
444};
445
446static const struct clksel dsp_irate_ick_clksel[] = {
447 { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
448 { .parent = NULL }
449};
450
451/* This clock does not exist as such in the TRM. */
452static struct clk dsp_irate_ick = {
453 .name = "dsp_irate_ick",
454 .ops = &clkops_null,
455 .parent = &dsp_fck,
456 .flags = DELAYED_APP,
457 .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
458 .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK,
459 .clksel = dsp_irate_ick_clksel,
460 .recalc = &omap2_clksel_recalc,
461};
462
463/* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
464static struct clk iva2_1_ick = {
465 .name = "iva2_1_ick",
466 .ops = &clkops_omap2_dflt_wait,
467 .parent = &dsp_irate_ick,
468 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
469 .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
470};
471
472/*
473 * L3 clock domain
474 * L3 clocks are used for both interface and functional clocks to
475 * multiple entities. Some of these clocks are completely managed
476 * by hardware, and some others allow software control. Hardware
477 * managed ones general are based on directly CLK_REQ signals and
478 * various auto idle settings. The functional spec sets many of these
479 * as 'tie-high' for their enables.
480 *
481 * I-CLOCKS:
482 * L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
483 * CAM, HS-USB.
484 * F-CLOCK
485 * SSI.
486 *
487 * GPMC memories and SDRC have timing and clock sensitive registers which
488 * may very well need notification when the clock changes. Currently for low
489 * operating points, these are taken care of in sleep.S.
490 */
491static const struct clksel_rate core_l3_core_rates[] = {
492 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
493 { .div = 4, .val = 4, .flags = RATE_IN_24XX | DEFAULT_RATE },
494 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
495 { .div = 0 }
496};
497
498static const struct clksel core_l3_clksel[] = {
499 { .parent = &core_ck, .rates = core_l3_core_rates },
500 { .parent = NULL }
501};
502
503static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */
504 .name = "core_l3_ck",
505 .ops = &clkops_null,
506 .parent = &core_ck,
507 .flags = DELAYED_APP,
508 .clkdm_name = "core_l3_clkdm",
509 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
510 .clksel_mask = OMAP24XX_CLKSEL_L3_MASK,
511 .clksel = core_l3_clksel,
512 .recalc = &omap2_clksel_recalc,
513};
514
515/* usb_l4_ick */
516static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
517 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
518 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
519 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
520 { .div = 0 }
521};
522
523static const struct clksel usb_l4_ick_clksel[] = {
524 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
525 { .parent = NULL },
526};
527
528/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
529static struct clk usb_l4_ick = { /* FS-USB interface clock */
530 .name = "usb_l4_ick",
531 .ops = &clkops_omap2_dflt_wait,
532 .parent = &core_l3_ck,
533 .flags = DELAYED_APP,
534 .clkdm_name = "core_l4_clkdm",
535 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
536 .enable_bit = OMAP24XX_EN_USB_SHIFT,
537 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
538 .clksel_mask = OMAP24XX_CLKSEL_USB_MASK,
539 .clksel = usb_l4_ick_clksel,
540 .recalc = &omap2_clksel_recalc,
541};
542
543/*
544 * L4 clock management domain
545 *
546 * This domain contains lots of interface clocks from the L4 interface, some
547 * functional clocks. Fixed APLL functional source clocks are managed in
548 * this domain.
549 */
550static const struct clksel_rate l4_core_l3_rates[] = {
551 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
552 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
553 { .div = 0 }
554};
555
556static const struct clksel l4_clksel[] = {
557 { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
558 { .parent = NULL }
559};
560
561static struct clk l4_ck = { /* used both as an ick and fck */
562 .name = "l4_ck",
563 .ops = &clkops_null,
564 .parent = &core_l3_ck,
565 .flags = DELAYED_APP,
566 .clkdm_name = "core_l4_clkdm",
567 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
568 .clksel_mask = OMAP24XX_CLKSEL_L4_MASK,
569 .clksel = l4_clksel,
570 .recalc = &omap2_clksel_recalc,
571 .round_rate = &omap2_clksel_round_rate,
572 .set_rate = &omap2_clksel_set_rate
573};
574
575/*
576 * SSI is in L3 management domain, its direct parent is core not l3,
577 * many core power domain entities are grouped into the L3 clock
578 * domain.
579 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
580 *
581 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
582 */
583static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
584 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
585 { .div = 2, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
586 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
587 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
588 { .div = 5, .val = 5, .flags = RATE_IN_243X },
589 { .div = 0 }
590};
591
592static const struct clksel ssi_ssr_sst_fck_clksel[] = {
593 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
594 { .parent = NULL }
595};
596
597static struct clk ssi_ssr_sst_fck = {
598 .name = "ssi_fck",
599 .ops = &clkops_omap2_dflt_wait,
600 .parent = &core_ck,
601 .flags = DELAYED_APP,
602 .clkdm_name = "core_l3_clkdm",
603 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
604 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
605 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
606 .clksel_mask = OMAP24XX_CLKSEL_SSI_MASK,
607 .clksel = ssi_ssr_sst_fck_clksel,
608 .recalc = &omap2_clksel_recalc,
609 .round_rate = &omap2_clksel_round_rate,
610 .set_rate = &omap2_clksel_set_rate
611};
612
613/*
614 * Presumably this is the same as SSI_ICLK.
615 * TRM contradicts itself on what clockdomain SSI_ICLK is in
616 */
617static struct clk ssi_l4_ick = {
618 .name = "ssi_l4_ick",
619 .ops = &clkops_omap2_dflt_wait,
620 .parent = &l4_ck,
621 .clkdm_name = "core_l4_clkdm",
622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
623 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
624 .recalc = &followparent_recalc,
625};
626
627
628/*
629 * GFX clock domain
630 * Clocks:
631 * GFX_FCLK, GFX_ICLK
632 * GFX_CG1(2d), GFX_CG2(3d)
633 *
634 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
635 * The 2d and 3d clocks run at a hardware determined
636 * divided value of fclk.
637 *
638 */
639
640/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
641static const struct clksel gfx_fck_clksel[] = {
642 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
643 { .parent = NULL },
644};
645
646static struct clk gfx_3d_fck = {
647 .name = "gfx_3d_fck",
648 .ops = &clkops_omap2_dflt_wait,
649 .parent = &core_l3_ck,
650 .clkdm_name = "gfx_clkdm",
651 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
652 .enable_bit = OMAP24XX_EN_3D_SHIFT,
653 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
654 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
655 .clksel = gfx_fck_clksel,
656 .recalc = &omap2_clksel_recalc,
657 .round_rate = &omap2_clksel_round_rate,
658 .set_rate = &omap2_clksel_set_rate
659};
660
661static struct clk gfx_2d_fck = {
662 .name = "gfx_2d_fck",
663 .ops = &clkops_omap2_dflt_wait,
664 .parent = &core_l3_ck,
665 .flags = DELAYED_APP,
666 .clkdm_name = "gfx_clkdm",
667 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
668 .enable_bit = OMAP24XX_EN_2D_SHIFT,
669 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
670 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
671 .clksel = gfx_fck_clksel,
672 .recalc = &omap2_clksel_recalc,
673};
674
675static struct clk gfx_ick = {
676 .name = "gfx_ick", /* From l3 */
677 .ops = &clkops_omap2_dflt_wait,
678 .parent = &core_l3_ck,
679 .clkdm_name = "gfx_clkdm",
680 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
681 .enable_bit = OMAP_EN_GFX_SHIFT,
682 .recalc = &followparent_recalc,
683};
684
685/*
686 * Modem clock domain (2430)
687 * CLOCKS:
688 * MDM_OSC_CLK
689 * MDM_ICLK
690 * These clocks are usable in chassis mode only.
691 */
692static const struct clksel_rate mdm_ick_core_rates[] = {
693 { .div = 1, .val = 1, .flags = RATE_IN_243X },
694 { .div = 4, .val = 4, .flags = RATE_IN_243X | DEFAULT_RATE },
695 { .div = 6, .val = 6, .flags = RATE_IN_243X },
696 { .div = 9, .val = 9, .flags = RATE_IN_243X },
697 { .div = 0 }
698};
699
700static const struct clksel mdm_ick_clksel[] = {
701 { .parent = &core_ck, .rates = mdm_ick_core_rates },
702 { .parent = NULL }
703};
704
705static struct clk mdm_ick = { /* used both as a ick and fck */
706 .name = "mdm_ick",
707 .ops = &clkops_omap2_dflt_wait,
708 .parent = &core_ck,
709 .flags = DELAYED_APP,
710 .clkdm_name = "mdm_clkdm",
711 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
712 .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
713 .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
714 .clksel_mask = OMAP2430_CLKSEL_MDM_MASK,
715 .clksel = mdm_ick_clksel,
716 .recalc = &omap2_clksel_recalc,
717};
718
719static struct clk mdm_osc_ck = {
720 .name = "mdm_osc_ck",
721 .ops = &clkops_omap2_dflt_wait,
722 .parent = &osc_ck,
723 .clkdm_name = "mdm_clkdm",
724 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
725 .enable_bit = OMAP2430_EN_OSC_SHIFT,
726 .recalc = &followparent_recalc,
727};
728
729/*
730 * DSS clock domain
731 * CLOCKs:
732 * DSS_L4_ICLK, DSS_L3_ICLK,
733 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
734 *
735 * DSS is both initiator and target.
736 */
737/* XXX Add RATE_NOT_VALIDATED */
738
739static const struct clksel_rate dss1_fck_sys_rates[] = {
740 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
741 { .div = 0 }
742};
743
744static const struct clksel_rate dss1_fck_core_rates[] = {
745 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
746 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
747 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
748 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
749 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
750 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
751 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
752 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
753 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
754 { .div = 16, .val = 16, .flags = RATE_IN_24XX | DEFAULT_RATE },
755 { .div = 0 }
756};
757
758static const struct clksel dss1_fck_clksel[] = {
759 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
760 { .parent = &core_ck, .rates = dss1_fck_core_rates },
761 { .parent = NULL },
762};
763
764static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */
765 .name = "dss_ick",
766 .ops = &clkops_omap2_dflt,
767 .parent = &l4_ck, /* really both l3 and l4 */
768 .clkdm_name = "dss_clkdm",
769 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
770 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
771 .recalc = &followparent_recalc,
772};
773
774static struct clk dss1_fck = {
775 .name = "dss1_fck",
776 .ops = &clkops_omap2_dflt,
777 .parent = &core_ck, /* Core or sys */
778 .flags = DELAYED_APP,
779 .clkdm_name = "dss_clkdm",
780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
781 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
782 .init = &omap2_init_clksel_parent,
783 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
784 .clksel_mask = OMAP24XX_CLKSEL_DSS1_MASK,
785 .clksel = dss1_fck_clksel,
786 .recalc = &omap2_clksel_recalc,
787 .round_rate = &omap2_clksel_round_rate,
788 .set_rate = &omap2_clksel_set_rate
789};
790
791static const struct clksel_rate dss2_fck_sys_rates[] = {
792 { .div = 1, .val = 0, .flags = RATE_IN_24XX | DEFAULT_RATE },
793 { .div = 0 }
794};
795
796static const struct clksel_rate dss2_fck_48m_rates[] = {
797 { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE },
798 { .div = 0 }
799};
800
801static const struct clksel dss2_fck_clksel[] = {
802 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
803 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
804 { .parent = NULL }
805};
806
807static struct clk dss2_fck = { /* Alt clk used in power management */
808 .name = "dss2_fck",
809 .ops = &clkops_omap2_dflt,
810 .parent = &sys_ck, /* fixed at sys_ck or 48MHz */
811 .flags = DELAYED_APP,
812 .clkdm_name = "dss_clkdm",
813 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
814 .enable_bit = OMAP24XX_EN_DSS2_SHIFT,
815 .init = &omap2_init_clksel_parent,
816 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
817 .clksel_mask = OMAP24XX_CLKSEL_DSS2_MASK,
818 .clksel = dss2_fck_clksel,
819 .recalc = &followparent_recalc,
820};
821
822static struct clk dss_54m_fck = { /* Alt clk used in power management */
823 .name = "dss_54m_fck", /* 54m tv clk */
824 .ops = &clkops_omap2_dflt_wait,
825 .parent = &func_54m_ck,
826 .clkdm_name = "dss_clkdm",
827 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
828 .enable_bit = OMAP24XX_EN_TV_SHIFT,
829 .recalc = &followparent_recalc,
830};
831
832/*
833 * CORE power domain ICLK & FCLK defines.
834 * Many of the these can have more than one possible parent. Entries
835 * here will likely have an L4 interface parent, and may have multiple
836 * functional clock parents.
837 */
838static const struct clksel_rate gpt_alt_rates[] = {
839 { .div = 1, .val = 2, .flags = RATE_IN_24XX | DEFAULT_RATE },
840 { .div = 0 }
841};
842
843static const struct clksel omap24xx_gpt_clksel[] = {
844 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
845 { .parent = &sys_ck, .rates = gpt_sys_rates },
846 { .parent = &alt_ck, .rates = gpt_alt_rates },
847 { .parent = NULL },
848};
849
850static struct clk gpt1_ick = {
851 .name = "gpt1_ick",
852 .ops = &clkops_omap2_dflt_wait,
853 .parent = &l4_ck,
854 .clkdm_name = "core_l4_clkdm",
855 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
856 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
857 .recalc = &followparent_recalc,
858};
859
860static struct clk gpt1_fck = {
861 .name = "gpt1_fck",
862 .ops = &clkops_omap2_dflt_wait,
863 .parent = &func_32k_ck,
864 .clkdm_name = "core_l4_clkdm",
865 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
866 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
867 .init = &omap2_init_clksel_parent,
868 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
869 .clksel_mask = OMAP24XX_CLKSEL_GPT1_MASK,
870 .clksel = omap24xx_gpt_clksel,
871 .recalc = &omap2_clksel_recalc,
872 .round_rate = &omap2_clksel_round_rate,
873 .set_rate = &omap2_clksel_set_rate
874};
875
876static struct clk gpt2_ick = {
877 .name = "gpt2_ick",
878 .ops = &clkops_omap2_dflt_wait,
879 .parent = &l4_ck,
880 .clkdm_name = "core_l4_clkdm",
881 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
882 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
883 .recalc = &followparent_recalc,
884};
885
886static struct clk gpt2_fck = {
887 .name = "gpt2_fck",
888 .ops = &clkops_omap2_dflt_wait,
889 .parent = &func_32k_ck,
890 .clkdm_name = "core_l4_clkdm",
891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
892 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
893 .init = &omap2_init_clksel_parent,
894 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
895 .clksel_mask = OMAP24XX_CLKSEL_GPT2_MASK,
896 .clksel = omap24xx_gpt_clksel,
897 .recalc = &omap2_clksel_recalc,
898};
899
900static struct clk gpt3_ick = {
901 .name = "gpt3_ick",
902 .ops = &clkops_omap2_dflt_wait,
903 .parent = &l4_ck,
904 .clkdm_name = "core_l4_clkdm",
905 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
906 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
907 .recalc = &followparent_recalc,
908};
909
910static struct clk gpt3_fck = {
911 .name = "gpt3_fck",
912 .ops = &clkops_omap2_dflt_wait,
913 .parent = &func_32k_ck,
914 .clkdm_name = "core_l4_clkdm",
915 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
916 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
917 .init = &omap2_init_clksel_parent,
918 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
919 .clksel_mask = OMAP24XX_CLKSEL_GPT3_MASK,
920 .clksel = omap24xx_gpt_clksel,
921 .recalc = &omap2_clksel_recalc,
922};
923
924static struct clk gpt4_ick = {
925 .name = "gpt4_ick",
926 .ops = &clkops_omap2_dflt_wait,
927 .parent = &l4_ck,
928 .clkdm_name = "core_l4_clkdm",
929 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
930 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
931 .recalc = &followparent_recalc,
932};
933
934static struct clk gpt4_fck = {
935 .name = "gpt4_fck",
936 .ops = &clkops_omap2_dflt_wait,
937 .parent = &func_32k_ck,
938 .clkdm_name = "core_l4_clkdm",
939 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
940 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
941 .init = &omap2_init_clksel_parent,
942 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
943 .clksel_mask = OMAP24XX_CLKSEL_GPT4_MASK,
944 .clksel = omap24xx_gpt_clksel,
945 .recalc = &omap2_clksel_recalc,
946};
947
948static struct clk gpt5_ick = {
949 .name = "gpt5_ick",
950 .ops = &clkops_omap2_dflt_wait,
951 .parent = &l4_ck,
952 .clkdm_name = "core_l4_clkdm",
953 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
954 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
955 .recalc = &followparent_recalc,
956};
957
958static struct clk gpt5_fck = {
959 .name = "gpt5_fck",
960 .ops = &clkops_omap2_dflt_wait,
961 .parent = &func_32k_ck,
962 .clkdm_name = "core_l4_clkdm",
963 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
964 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
965 .init = &omap2_init_clksel_parent,
966 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
967 .clksel_mask = OMAP24XX_CLKSEL_GPT5_MASK,
968 .clksel = omap24xx_gpt_clksel,
969 .recalc = &omap2_clksel_recalc,
970};
971
972static struct clk gpt6_ick = {
973 .name = "gpt6_ick",
974 .ops = &clkops_omap2_dflt_wait,
975 .parent = &l4_ck,
976 .clkdm_name = "core_l4_clkdm",
977 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
978 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
979 .recalc = &followparent_recalc,
980};
981
982static struct clk gpt6_fck = {
983 .name = "gpt6_fck",
984 .ops = &clkops_omap2_dflt_wait,
985 .parent = &func_32k_ck,
986 .clkdm_name = "core_l4_clkdm",
987 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
988 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
989 .init = &omap2_init_clksel_parent,
990 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
991 .clksel_mask = OMAP24XX_CLKSEL_GPT6_MASK,
992 .clksel = omap24xx_gpt_clksel,
993 .recalc = &omap2_clksel_recalc,
994};
995
996static struct clk gpt7_ick = {
997 .name = "gpt7_ick",
998 .ops = &clkops_omap2_dflt_wait,
999 .parent = &l4_ck,
1000 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1001 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1002 .recalc = &followparent_recalc,
1003};
1004
1005static struct clk gpt7_fck = {
1006 .name = "gpt7_fck",
1007 .ops = &clkops_omap2_dflt_wait,
1008 .parent = &func_32k_ck,
1009 .clkdm_name = "core_l4_clkdm",
1010 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1011 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
1012 .init = &omap2_init_clksel_parent,
1013 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1014 .clksel_mask = OMAP24XX_CLKSEL_GPT7_MASK,
1015 .clksel = omap24xx_gpt_clksel,
1016 .recalc = &omap2_clksel_recalc,
1017};
1018
1019static struct clk gpt8_ick = {
1020 .name = "gpt8_ick",
1021 .ops = &clkops_omap2_dflt_wait,
1022 .parent = &l4_ck,
1023 .clkdm_name = "core_l4_clkdm",
1024 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1025 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1026 .recalc = &followparent_recalc,
1027};
1028
1029static struct clk gpt8_fck = {
1030 .name = "gpt8_fck",
1031 .ops = &clkops_omap2_dflt_wait,
1032 .parent = &func_32k_ck,
1033 .clkdm_name = "core_l4_clkdm",
1034 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1035 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
1036 .init = &omap2_init_clksel_parent,
1037 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1038 .clksel_mask = OMAP24XX_CLKSEL_GPT8_MASK,
1039 .clksel = omap24xx_gpt_clksel,
1040 .recalc = &omap2_clksel_recalc,
1041};
1042
1043static struct clk gpt9_ick = {
1044 .name = "gpt9_ick",
1045 .ops = &clkops_omap2_dflt_wait,
1046 .parent = &l4_ck,
1047 .clkdm_name = "core_l4_clkdm",
1048 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1049 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1050 .recalc = &followparent_recalc,
1051};
1052
1053static struct clk gpt9_fck = {
1054 .name = "gpt9_fck",
1055 .ops = &clkops_omap2_dflt_wait,
1056 .parent = &func_32k_ck,
1057 .clkdm_name = "core_l4_clkdm",
1058 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1059 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
1060 .init = &omap2_init_clksel_parent,
1061 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1062 .clksel_mask = OMAP24XX_CLKSEL_GPT9_MASK,
1063 .clksel = omap24xx_gpt_clksel,
1064 .recalc = &omap2_clksel_recalc,
1065};
1066
1067static struct clk gpt10_ick = {
1068 .name = "gpt10_ick",
1069 .ops = &clkops_omap2_dflt_wait,
1070 .parent = &l4_ck,
1071 .clkdm_name = "core_l4_clkdm",
1072 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1073 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1074 .recalc = &followparent_recalc,
1075};
1076
1077static struct clk gpt10_fck = {
1078 .name = "gpt10_fck",
1079 .ops = &clkops_omap2_dflt_wait,
1080 .parent = &func_32k_ck,
1081 .clkdm_name = "core_l4_clkdm",
1082 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1083 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
1084 .init = &omap2_init_clksel_parent,
1085 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1086 .clksel_mask = OMAP24XX_CLKSEL_GPT10_MASK,
1087 .clksel = omap24xx_gpt_clksel,
1088 .recalc = &omap2_clksel_recalc,
1089};
1090
1091static struct clk gpt11_ick = {
1092 .name = "gpt11_ick",
1093 .ops = &clkops_omap2_dflt_wait,
1094 .parent = &l4_ck,
1095 .clkdm_name = "core_l4_clkdm",
1096 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1097 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1098 .recalc = &followparent_recalc,
1099};
1100
1101static struct clk gpt11_fck = {
1102 .name = "gpt11_fck",
1103 .ops = &clkops_omap2_dflt_wait,
1104 .parent = &func_32k_ck,
1105 .clkdm_name = "core_l4_clkdm",
1106 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1107 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
1108 .init = &omap2_init_clksel_parent,
1109 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1110 .clksel_mask = OMAP24XX_CLKSEL_GPT11_MASK,
1111 .clksel = omap24xx_gpt_clksel,
1112 .recalc = &omap2_clksel_recalc,
1113};
1114
1115static struct clk gpt12_ick = {
1116 .name = "gpt12_ick",
1117 .ops = &clkops_omap2_dflt_wait,
1118 .parent = &l4_ck,
1119 .clkdm_name = "core_l4_clkdm",
1120 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1121 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1122 .recalc = &followparent_recalc,
1123};
1124
1125static struct clk gpt12_fck = {
1126 .name = "gpt12_fck",
1127 .ops = &clkops_omap2_dflt_wait,
1128 .parent = &secure_32k_ck,
1129 .clkdm_name = "core_l4_clkdm",
1130 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1131 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
1132 .init = &omap2_init_clksel_parent,
1133 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1134 .clksel_mask = OMAP24XX_CLKSEL_GPT12_MASK,
1135 .clksel = omap24xx_gpt_clksel,
1136 .recalc = &omap2_clksel_recalc,
1137};
1138
1139static struct clk mcbsp1_ick = {
1140 .name = "mcbsp1_ick",
1141 .ops = &clkops_omap2_dflt_wait,
1142 .parent = &l4_ck,
1143 .clkdm_name = "core_l4_clkdm",
1144 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1145 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1146 .recalc = &followparent_recalc,
1147};
1148
1149static struct clk mcbsp1_fck = {
1150 .name = "mcbsp1_fck",
1151 .ops = &clkops_omap2_dflt_wait,
1152 .parent = &func_96m_ck,
1153 .clkdm_name = "core_l4_clkdm",
1154 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1155 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1156 .recalc = &followparent_recalc,
1157};
1158
1159static struct clk mcbsp2_ick = {
1160 .name = "mcbsp2_ick",
1161 .ops = &clkops_omap2_dflt_wait,
1162 .parent = &l4_ck,
1163 .clkdm_name = "core_l4_clkdm",
1164 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1165 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1166 .recalc = &followparent_recalc,
1167};
1168
1169static struct clk mcbsp2_fck = {
1170 .name = "mcbsp2_fck",
1171 .ops = &clkops_omap2_dflt_wait,
1172 .parent = &func_96m_ck,
1173 .clkdm_name = "core_l4_clkdm",
1174 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1175 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1176 .recalc = &followparent_recalc,
1177};
1178
1179static struct clk mcbsp3_ick = {
1180 .name = "mcbsp3_ick",
1181 .ops = &clkops_omap2_dflt_wait,
1182 .parent = &l4_ck,
1183 .clkdm_name = "core_l4_clkdm",
1184 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1185 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1186 .recalc = &followparent_recalc,
1187};
1188
1189static struct clk mcbsp3_fck = {
1190 .name = "mcbsp3_fck",
1191 .ops = &clkops_omap2_dflt_wait,
1192 .parent = &func_96m_ck,
1193 .clkdm_name = "core_l4_clkdm",
1194 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1195 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1196 .recalc = &followparent_recalc,
1197};
1198
1199static struct clk mcbsp4_ick = {
1200 .name = "mcbsp4_ick",
1201 .ops = &clkops_omap2_dflt_wait,
1202 .parent = &l4_ck,
1203 .clkdm_name = "core_l4_clkdm",
1204 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1205 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1206 .recalc = &followparent_recalc,
1207};
1208
1209static struct clk mcbsp4_fck = {
1210 .name = "mcbsp4_fck",
1211 .ops = &clkops_omap2_dflt_wait,
1212 .parent = &func_96m_ck,
1213 .clkdm_name = "core_l4_clkdm",
1214 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1215 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1216 .recalc = &followparent_recalc,
1217};
1218
1219static struct clk mcbsp5_ick = {
1220 .name = "mcbsp5_ick",
1221 .ops = &clkops_omap2_dflt_wait,
1222 .parent = &l4_ck,
1223 .clkdm_name = "core_l4_clkdm",
1224 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1225 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1226 .recalc = &followparent_recalc,
1227};
1228
1229static struct clk mcbsp5_fck = {
1230 .name = "mcbsp5_fck",
1231 .ops = &clkops_omap2_dflt_wait,
1232 .parent = &func_96m_ck,
1233 .clkdm_name = "core_l4_clkdm",
1234 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1235 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1236 .recalc = &followparent_recalc,
1237};
1238
1239static struct clk mcspi1_ick = {
1240 .name = "mcspi1_ick",
1241 .ops = &clkops_omap2_dflt_wait,
1242 .parent = &l4_ck,
1243 .clkdm_name = "core_l4_clkdm",
1244 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1245 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1246 .recalc = &followparent_recalc,
1247};
1248
1249static struct clk mcspi1_fck = {
1250 .name = "mcspi1_fck",
1251 .ops = &clkops_omap2_dflt_wait,
1252 .parent = &func_48m_ck,
1253 .clkdm_name = "core_l4_clkdm",
1254 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1255 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1256 .recalc = &followparent_recalc,
1257};
1258
1259static struct clk mcspi2_ick = {
1260 .name = "mcspi2_ick",
1261 .ops = &clkops_omap2_dflt_wait,
1262 .parent = &l4_ck,
1263 .clkdm_name = "core_l4_clkdm",
1264 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1265 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1266 .recalc = &followparent_recalc,
1267};
1268
1269static struct clk mcspi2_fck = {
1270 .name = "mcspi2_fck",
1271 .ops = &clkops_omap2_dflt_wait,
1272 .parent = &func_48m_ck,
1273 .clkdm_name = "core_l4_clkdm",
1274 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1275 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1276 .recalc = &followparent_recalc,
1277};
1278
1279static struct clk mcspi3_ick = {
1280 .name = "mcspi3_ick",
1281 .ops = &clkops_omap2_dflt_wait,
1282 .parent = &l4_ck,
1283 .clkdm_name = "core_l4_clkdm",
1284 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1285 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1286 .recalc = &followparent_recalc,
1287};
1288
1289static struct clk mcspi3_fck = {
1290 .name = "mcspi3_fck",
1291 .ops = &clkops_omap2_dflt_wait,
1292 .parent = &func_48m_ck,
1293 .clkdm_name = "core_l4_clkdm",
1294 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1295 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1296 .recalc = &followparent_recalc,
1297};
1298
1299static struct clk uart1_ick = {
1300 .name = "uart1_ick",
1301 .ops = &clkops_omap2_dflt_wait,
1302 .parent = &l4_ck,
1303 .clkdm_name = "core_l4_clkdm",
1304 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1305 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1306 .recalc = &followparent_recalc,
1307};
1308
1309static struct clk uart1_fck = {
1310 .name = "uart1_fck",
1311 .ops = &clkops_omap2_dflt_wait,
1312 .parent = &func_48m_ck,
1313 .clkdm_name = "core_l4_clkdm",
1314 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1315 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1316 .recalc = &followparent_recalc,
1317};
1318
1319static struct clk uart2_ick = {
1320 .name = "uart2_ick",
1321 .ops = &clkops_omap2_dflt_wait,
1322 .parent = &l4_ck,
1323 .clkdm_name = "core_l4_clkdm",
1324 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1325 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1326 .recalc = &followparent_recalc,
1327};
1328
1329static struct clk uart2_fck = {
1330 .name = "uart2_fck",
1331 .ops = &clkops_omap2_dflt_wait,
1332 .parent = &func_48m_ck,
1333 .clkdm_name = "core_l4_clkdm",
1334 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1335 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1336 .recalc = &followparent_recalc,
1337};
1338
1339static struct clk uart3_ick = {
1340 .name = "uart3_ick",
1341 .ops = &clkops_omap2_dflt_wait,
1342 .parent = &l4_ck,
1343 .clkdm_name = "core_l4_clkdm",
1344 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1345 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1346 .recalc = &followparent_recalc,
1347};
1348
1349static struct clk uart3_fck = {
1350 .name = "uart3_fck",
1351 .ops = &clkops_omap2_dflt_wait,
1352 .parent = &func_48m_ck,
1353 .clkdm_name = "core_l4_clkdm",
1354 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1355 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1356 .recalc = &followparent_recalc,
1357};
1358
1359static struct clk gpios_ick = {
1360 .name = "gpios_ick",
1361 .ops = &clkops_omap2_dflt_wait,
1362 .parent = &l4_ck,
1363 .clkdm_name = "core_l4_clkdm",
1364 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1365 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1366 .recalc = &followparent_recalc,
1367};
1368
1369static struct clk gpios_fck = {
1370 .name = "gpios_fck",
1371 .ops = &clkops_omap2_dflt_wait,
1372 .parent = &func_32k_ck,
1373 .clkdm_name = "wkup_clkdm",
1374 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1375 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
1376 .recalc = &followparent_recalc,
1377};
1378
1379static struct clk mpu_wdt_ick = {
1380 .name = "mpu_wdt_ick",
1381 .ops = &clkops_omap2_dflt_wait,
1382 .parent = &l4_ck,
1383 .clkdm_name = "core_l4_clkdm",
1384 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1385 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1386 .recalc = &followparent_recalc,
1387};
1388
1389static struct clk mpu_wdt_fck = {
1390 .name = "mpu_wdt_fck",
1391 .ops = &clkops_omap2_dflt_wait,
1392 .parent = &func_32k_ck,
1393 .clkdm_name = "wkup_clkdm",
1394 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1395 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1396 .recalc = &followparent_recalc,
1397};
1398
1399static struct clk sync_32k_ick = {
1400 .name = "sync_32k_ick",
1401 .ops = &clkops_omap2_dflt_wait,
1402 .parent = &l4_ck,
1403 .flags = ENABLE_ON_INIT,
1404 .clkdm_name = "core_l4_clkdm",
1405 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1406 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1407 .recalc = &followparent_recalc,
1408};
1409
1410static struct clk wdt1_ick = {
1411 .name = "wdt1_ick",
1412 .ops = &clkops_omap2_dflt_wait,
1413 .parent = &l4_ck,
1414 .clkdm_name = "core_l4_clkdm",
1415 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1416 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1417 .recalc = &followparent_recalc,
1418};
1419
1420static struct clk omapctrl_ick = {
1421 .name = "omapctrl_ick",
1422 .ops = &clkops_omap2_dflt_wait,
1423 .parent = &l4_ck,
1424 .flags = ENABLE_ON_INIT,
1425 .clkdm_name = "core_l4_clkdm",
1426 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1427 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1428 .recalc = &followparent_recalc,
1429};
1430
1431static struct clk icr_ick = {
1432 .name = "icr_ick",
1433 .ops = &clkops_omap2_dflt_wait,
1434 .parent = &l4_ck,
1435 .clkdm_name = "core_l4_clkdm",
1436 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1437 .enable_bit = OMAP2430_EN_ICR_SHIFT,
1438 .recalc = &followparent_recalc,
1439};
1440
1441static struct clk cam_ick = {
1442 .name = "cam_ick",
1443 .ops = &clkops_omap2_dflt,
1444 .parent = &l4_ck,
1445 .clkdm_name = "core_l4_clkdm",
1446 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1447 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1448 .recalc = &followparent_recalc,
1449};
1450
1451/*
1452 * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be
1453 * split into two separate clocks, since the parent clocks are different
1454 * and the clockdomains are also different.
1455 */
1456static struct clk cam_fck = {
1457 .name = "cam_fck",
1458 .ops = &clkops_omap2_dflt,
1459 .parent = &func_96m_ck,
1460 .clkdm_name = "core_l3_clkdm",
1461 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1462 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
1463 .recalc = &followparent_recalc,
1464};
1465
1466static struct clk mailboxes_ick = {
1467 .name = "mailboxes_ick",
1468 .ops = &clkops_omap2_dflt_wait,
1469 .parent = &l4_ck,
1470 .clkdm_name = "core_l4_clkdm",
1471 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1472 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1473 .recalc = &followparent_recalc,
1474};
1475
1476static struct clk wdt4_ick = {
1477 .name = "wdt4_ick",
1478 .ops = &clkops_omap2_dflt_wait,
1479 .parent = &l4_ck,
1480 .clkdm_name = "core_l4_clkdm",
1481 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1482 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1483 .recalc = &followparent_recalc,
1484};
1485
1486static struct clk wdt4_fck = {
1487 .name = "wdt4_fck",
1488 .ops = &clkops_omap2_dflt_wait,
1489 .parent = &func_32k_ck,
1490 .clkdm_name = "core_l4_clkdm",
1491 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1492 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1493 .recalc = &followparent_recalc,
1494};
1495
1496static struct clk mspro_ick = {
1497 .name = "mspro_ick",
1498 .ops = &clkops_omap2_dflt_wait,
1499 .parent = &l4_ck,
1500 .clkdm_name = "core_l4_clkdm",
1501 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1502 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1503 .recalc = &followparent_recalc,
1504};
1505
1506static struct clk mspro_fck = {
1507 .name = "mspro_fck",
1508 .ops = &clkops_omap2_dflt_wait,
1509 .parent = &func_96m_ck,
1510 .clkdm_name = "core_l4_clkdm",
1511 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1512 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1513 .recalc = &followparent_recalc,
1514};
1515
1516static struct clk fac_ick = {
1517 .name = "fac_ick",
1518 .ops = &clkops_omap2_dflt_wait,
1519 .parent = &l4_ck,
1520 .clkdm_name = "core_l4_clkdm",
1521 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1522 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1523 .recalc = &followparent_recalc,
1524};
1525
1526static struct clk fac_fck = {
1527 .name = "fac_fck",
1528 .ops = &clkops_omap2_dflt_wait,
1529 .parent = &func_12m_ck,
1530 .clkdm_name = "core_l4_clkdm",
1531 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1532 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
1533 .recalc = &followparent_recalc,
1534};
1535
1536static struct clk hdq_ick = {
1537 .name = "hdq_ick",
1538 .ops = &clkops_omap2_dflt_wait,
1539 .parent = &l4_ck,
1540 .clkdm_name = "core_l4_clkdm",
1541 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1542 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1543 .recalc = &followparent_recalc,
1544};
1545
1546static struct clk hdq_fck = {
1547 .name = "hdq_fck",
1548 .ops = &clkops_omap2_dflt_wait,
1549 .parent = &func_12m_ck,
1550 .clkdm_name = "core_l4_clkdm",
1551 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1552 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
1553 .recalc = &followparent_recalc,
1554};
1555
1556/*
1557 * XXX This is marked as a 2420-only define, but it claims to be present
1558 * on 2430 also. Double-check.
1559 */
1560static struct clk i2c2_ick = {
1561 .name = "i2c2_ick",
1562 .ops = &clkops_omap2_dflt_wait,
1563 .parent = &l4_ck,
1564 .clkdm_name = "core_l4_clkdm",
1565 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1566 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1567 .recalc = &followparent_recalc,
1568};
1569
1570static struct clk i2chs2_fck = {
1571 .name = "i2chs2_fck",
1572 .ops = &clkops_omap2430_i2chs_wait,
1573 .parent = &func_96m_ck,
1574 .clkdm_name = "core_l4_clkdm",
1575 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1576 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
1577 .recalc = &followparent_recalc,
1578};
1579
1580/*
1581 * XXX This is marked as a 2420-only define, but it claims to be present
1582 * on 2430 also. Double-check.
1583 */
1584static struct clk i2c1_ick = {
1585 .name = "i2c1_ick",
1586 .ops = &clkops_omap2_dflt_wait,
1587 .parent = &l4_ck,
1588 .clkdm_name = "core_l4_clkdm",
1589 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1590 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
1591 .recalc = &followparent_recalc,
1592};
1593
1594static struct clk i2chs1_fck = {
1595 .name = "i2chs1_fck",
1596 .ops = &clkops_omap2430_i2chs_wait,
1597 .parent = &func_96m_ck,
1598 .clkdm_name = "core_l4_clkdm",
1599 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1600 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
1601 .recalc = &followparent_recalc,
1602};
1603
1604static struct clk gpmc_fck = {
1605 .name = "gpmc_fck",
1606 .ops = &clkops_null, /* RMK: missing? */
1607 .parent = &core_l3_ck,
1608 .flags = ENABLE_ON_INIT,
1609 .clkdm_name = "core_l3_clkdm",
1610 .recalc = &followparent_recalc,
1611};
1612
1613static struct clk sdma_fck = {
1614 .name = "sdma_fck",
1615 .ops = &clkops_null, /* RMK: missing? */
1616 .parent = &core_l3_ck,
1617 .clkdm_name = "core_l3_clkdm",
1618 .recalc = &followparent_recalc,
1619};
1620
1621static struct clk sdma_ick = {
1622 .name = "sdma_ick",
1623 .ops = &clkops_null, /* RMK: missing? */
1624 .parent = &l4_ck,
1625 .clkdm_name = "core_l3_clkdm",
1626 .recalc = &followparent_recalc,
1627};
1628
1629static struct clk sdrc_ick = {
1630 .name = "sdrc_ick",
1631 .ops = &clkops_omap2_dflt_wait,
1632 .parent = &l4_ck,
1633 .flags = ENABLE_ON_INIT,
1634 .clkdm_name = "core_l4_clkdm",
1635 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1636 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1637 .recalc = &followparent_recalc,
1638};
1639
1640static struct clk des_ick = {
1641 .name = "des_ick",
1642 .ops = &clkops_omap2_dflt_wait,
1643 .parent = &l4_ck,
1644 .clkdm_name = "core_l4_clkdm",
1645 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1646 .enable_bit = OMAP24XX_EN_DES_SHIFT,
1647 .recalc = &followparent_recalc,
1648};
1649
1650static struct clk sha_ick = {
1651 .name = "sha_ick",
1652 .ops = &clkops_omap2_dflt_wait,
1653 .parent = &l4_ck,
1654 .clkdm_name = "core_l4_clkdm",
1655 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1656 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1657 .recalc = &followparent_recalc,
1658};
1659
1660static struct clk rng_ick = {
1661 .name = "rng_ick",
1662 .ops = &clkops_omap2_dflt_wait,
1663 .parent = &l4_ck,
1664 .clkdm_name = "core_l4_clkdm",
1665 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1666 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1667 .recalc = &followparent_recalc,
1668};
1669
1670static struct clk aes_ick = {
1671 .name = "aes_ick",
1672 .ops = &clkops_omap2_dflt_wait,
1673 .parent = &l4_ck,
1674 .clkdm_name = "core_l4_clkdm",
1675 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1676 .enable_bit = OMAP24XX_EN_AES_SHIFT,
1677 .recalc = &followparent_recalc,
1678};
1679
1680static struct clk pka_ick = {
1681 .name = "pka_ick",
1682 .ops = &clkops_omap2_dflt_wait,
1683 .parent = &l4_ck,
1684 .clkdm_name = "core_l4_clkdm",
1685 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1686 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1687 .recalc = &followparent_recalc,
1688};
1689
1690static struct clk usb_fck = {
1691 .name = "usb_fck",
1692 .ops = &clkops_omap2_dflt_wait,
1693 .parent = &func_48m_ck,
1694 .clkdm_name = "core_l3_clkdm",
1695 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1696 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1697 .recalc = &followparent_recalc,
1698};
1699
1700static struct clk usbhs_ick = {
1701 .name = "usbhs_ick",
1702 .ops = &clkops_omap2_dflt_wait,
1703 .parent = &core_l3_ck,
1704 .clkdm_name = "core_l3_clkdm",
1705 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1706 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
1707 .recalc = &followparent_recalc,
1708};
1709
1710static struct clk mmchs1_ick = {
1711 .name = "mmchs1_ick",
1712 .ops = &clkops_omap2_dflt_wait,
1713 .parent = &l4_ck,
1714 .clkdm_name = "core_l4_clkdm",
1715 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1716 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1717 .recalc = &followparent_recalc,
1718};
1719
1720static struct clk mmchs1_fck = {
1721 .name = "mmchs1_fck",
1722 .ops = &clkops_omap2_dflt_wait,
1723 .parent = &func_96m_ck,
1724 .clkdm_name = "core_l3_clkdm",
1725 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1726 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1727 .recalc = &followparent_recalc,
1728};
1729
1730static struct clk mmchs2_ick = {
1731 .name = "mmchs2_ick",
1732 .ops = &clkops_omap2_dflt_wait,
1733 .parent = &l4_ck,
1734 .clkdm_name = "core_l4_clkdm",
1735 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1736 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1737 .recalc = &followparent_recalc,
1738};
1739
1740static struct clk mmchs2_fck = {
1741 .name = "mmchs2_fck",
1742 .ops = &clkops_omap2_dflt_wait,
1743 .parent = &func_96m_ck,
1744 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1745 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1746 .recalc = &followparent_recalc,
1747};
1748
1749static struct clk gpio5_ick = {
1750 .name = "gpio5_ick",
1751 .ops = &clkops_omap2_dflt_wait,
1752 .parent = &l4_ck,
1753 .clkdm_name = "core_l4_clkdm",
1754 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1755 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1756 .recalc = &followparent_recalc,
1757};
1758
1759static struct clk gpio5_fck = {
1760 .name = "gpio5_fck",
1761 .ops = &clkops_omap2_dflt_wait,
1762 .parent = &func_32k_ck,
1763 .clkdm_name = "core_l4_clkdm",
1764 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1765 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
1766 .recalc = &followparent_recalc,
1767};
1768
1769static struct clk mdm_intc_ick = {
1770 .name = "mdm_intc_ick",
1771 .ops = &clkops_omap2_dflt_wait,
1772 .parent = &l4_ck,
1773 .clkdm_name = "core_l4_clkdm",
1774 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1775 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
1776 .recalc = &followparent_recalc,
1777};
1778
1779static struct clk mmchsdb1_fck = {
1780 .name = "mmchsdb1_fck",
1781 .ops = &clkops_omap2_dflt_wait,
1782 .parent = &func_32k_ck,
1783 .clkdm_name = "core_l4_clkdm",
1784 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1785 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
1786 .recalc = &followparent_recalc,
1787};
1788
1789static struct clk mmchsdb2_fck = {
1790 .name = "mmchsdb2_fck",
1791 .ops = &clkops_omap2_dflt_wait,
1792 .parent = &func_32k_ck,
1793 .clkdm_name = "core_l4_clkdm",
1794 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1795 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
1796 .recalc = &followparent_recalc,
1797};
1798
1799/*
1800 * This clock is a composite clock which does entire set changes then
1801 * forces a rebalance. It keys on the MPU speed, but it really could
1802 * be any key speed part of a set in the rate table.
1803 *
1804 * to really change a set, you need memory table sets which get changed
1805 * in sram, pre-notifiers & post notifiers, changing the top set, without
1806 * having low level display recalc's won't work... this is why dpm notifiers
1807 * work, isr's off, walk a list of clocks already _off_ and not messing with
1808 * the bus.
1809 *
1810 * This clock should have no parent. It embodies the entire upper level
1811 * active set. A parent will mess up some of the init also.
1812 */
1813static struct clk virt_prcm_set = {
1814 .name = "virt_prcm_set",
1815 .ops = &clkops_null,
1816 .parent = &mpu_ck, /* Indexed by mpu speed, no parent */
1817 .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */
1818 .set_rate = &omap2_select_table_rate,
1819 .round_rate = &omap2_round_to_table_rate,
1820};
1821
1822
1823/*
1824 * clkdev integration
1825 */
1826
1827static struct omap_clk omap2430_clks[] = {
1828 /* external root sources */
1829 CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X),
1830 CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X),
1831 CLK(NULL, "osc_ck", &osc_ck, CK_243X),
1832 CLK(NULL, "sys_ck", &sys_ck, CK_243X),
1833 CLK(NULL, "alt_ck", &alt_ck, CK_243X),
1834 /* internal analog sources */
1835 CLK(NULL, "dpll_ck", &dpll_ck, CK_243X),
1836 CLK(NULL, "apll96_ck", &apll96_ck, CK_243X),
1837 CLK(NULL, "apll54_ck", &apll54_ck, CK_243X),
1838 /* internal prcm root sources */
1839 CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X),
1840 CLK(NULL, "core_ck", &core_ck, CK_243X),
1841 CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X),
1842 CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X),
1843 CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X),
1844 CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X),
1845 CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X),
1846 CLK(NULL, "sys_clkout", &sys_clkout, CK_243X),
1847 CLK(NULL, "emul_ck", &emul_ck, CK_243X),
1848 /* mpu domain clocks */
1849 CLK(NULL, "mpu_ck", &mpu_ck, CK_243X),
1850 /* dsp domain clocks */
1851 CLK(NULL, "dsp_fck", &dsp_fck, CK_243X),
1852 CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X),
1853 CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X),
1854 /* GFX domain clocks */
1855 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X),
1856 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X),
1857 CLK(NULL, "gfx_ick", &gfx_ick, CK_243X),
1858 /* Modem domain clocks */
1859 CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
1860 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
1861 /* DSS domain clocks */
1862 CLK("omapdss", "ick", &dss_ick, CK_243X),
1863 CLK("omapdss", "dss1_fck", &dss1_fck, CK_243X),
1864 CLK("omapdss", "dss2_fck", &dss2_fck, CK_243X),
1865 CLK("omapdss", "tv_fck", &dss_54m_fck, CK_243X),
1866 /* L3 domain clocks */
1867 CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
1868 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
1869 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X),
1870 /* L4 domain clocks */
1871 CLK(NULL, "l4_ck", &l4_ck, CK_243X),
1872 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X),
1873 /* virtual meta-group clock */
1874 CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X),
1875 /* general l4 interface ck, multi-parent functional clk */
1876 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X),
1877 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X),
1878 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X),
1879 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X),
1880 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X),
1881 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X),
1882 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X),
1883 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X),
1884 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X),
1885 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X),
1886 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X),
1887 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X),
1888 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X),
1889 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X),
1890 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X),
1891 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X),
1892 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X),
1893 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X),
1894 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X),
1895 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X),
1896 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X),
1897 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X),
1898 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
1899 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
1900 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
1901 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X),
1902 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
1903 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X),
1904 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
1905 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
1906 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
1907 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
1908 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
1909 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
1910 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
1911 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X),
1912 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
1913 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X),
1914 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
1915 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
1916 CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
1917 CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
1918 CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
1919 CLK(NULL, "uart2_fck", &uart2_fck, CK_243X),
1920 CLK(NULL, "uart3_ick", &uart3_ick, CK_243X),
1921 CLK(NULL, "uart3_fck", &uart3_fck, CK_243X),
1922 CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
1923 CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
1924 CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
1925 CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X),
1926 CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
1927 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
1928 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
1929 CLK(NULL, "icr_ick", &icr_ick, CK_243X),
1930 CLK("omap24xxcam", "fck", &cam_fck, CK_243X),
1931 CLK("omap24xxcam", "ick", &cam_ick, CK_243X),
1932 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X),
1933 CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X),
1934 CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X),
1935 CLK(NULL, "mspro_ick", &mspro_ick, CK_243X),
1936 CLK(NULL, "mspro_fck", &mspro_fck, CK_243X),
1937 CLK(NULL, "fac_ick", &fac_ick, CK_243X),
1938 CLK(NULL, "fac_fck", &fac_fck, CK_243X),
1939 CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
1940 CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
1941 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X),
1942 CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X),
1943 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X),
1944 CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X),
1945 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
1946 CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
1947 CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
1948 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X),
1949 CLK(NULL, "des_ick", &des_ick, CK_243X),
1950 CLK(NULL, "sha_ick", &sha_ick, CK_243X),
1951 CLK("omap_rng", "ick", &rng_ick, CK_243X),
1952 CLK(NULL, "aes_ick", &aes_ick, CK_243X),
1953 CLK(NULL, "pka_ick", &pka_ick, CK_243X),
1954 CLK(NULL, "usb_fck", &usb_fck, CK_243X),
1955 CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
1956 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
1957 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
1958 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
1959 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X),
1960 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
1961 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
1962 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
1963 CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
1964 CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
1965};
1966
1967/*
1968 * init code
1969 */
1970
1971int __init omap2430_clk_init(void)
1972{
1973 const struct prcm_config *prcm;
1974 struct omap_clk *c;
1975 u32 clkrate;
1976
1977 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
1978 cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
1979 cpu_mask = RATE_IN_243X;
1980 rate_table = omap2430_rate_table;
1981
1982 clk_init(&omap2_clk_functions);
1983
1984 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
1985 c++)
1986 clk_preinit(c->lk.clk);
1987
1988 osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
1989 propagate_rate(&osc_ck);
1990 sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
1991 propagate_rate(&sys_ck);
1992
1993 for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
1994 c++) {
1995 clkdev_add(&c->lk);
1996 clk_register(c->lk.clk);
1997 omap2_init_clk_clkdm(c->lk.clk);
1998 }
1999
2000 /* Check the MPU rate set by bootloader */
2001 clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
2002 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
2003 if (!(prcm->flags & cpu_mask))
2004 continue;
2005 if (prcm->xtal_speed != sys_ck.rate)
2006 continue;
2007 if (prcm->dpll_speed <= clkrate)
2008 break;
2009 }
2010 curr_prcm_set = prcm;
2011
2012 recalculate_root_clocks();
2013
2014 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
2015 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
2016 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
2017
2018 /*
2019 * Only enable those clocks we will need, let the drivers
2020 * enable other clocks as necessary
2021 */
2022 clk_enable_init_clocks();
2023
2024 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
2025 vclk = clk_get(NULL, "virt_prcm_set");
2026 sclk = clk_get(NULL, "sys_ck");
2027 dclk = clk_get(NULL, "dpll_ck");
2028
2029 return 0;
2030}
2031
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 05:25:57 -0400