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authorRajendra Nayak <rnayak@ti.com>2009-12-08 20:47:16 -0500
committerpaul <paul@twilight.(none)>2009-12-11 19:00:46 -0500
commita1391d276866845018920329bc2a3a82ab322af8 (patch)
treea16a46b6d0af3cb5e3dcd4f7de207f138d087011 /arch/arm/mach-omap2/clock.h
parentd79b126724554122d9598834ef39fb0bb4fc132d (diff)
ARM: OMAP4: PM: Move DPLL control apis to dpll.c
This patch moves all the dpll control api's to a common file dpll.c. This is in preperation of omap4 support wherein most of these api's can be reused. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoit Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch/arm/mach-omap2/clock.h')
-rw-r--r--arch/arm/mach-omap2/clock.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 87c08056b303..4df7aa43ef44 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -36,6 +36,11 @@
36#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 36#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
37#define OMAP3XXX_EN_DPLL_LOCKED 0x7 37#define OMAP3XXX_EN_DPLL_LOCKED 0x7
38 38
39/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
40#define DPLL_LOW_POWER_STOP 0x1
41#define DPLL_LOW_POWER_BYPASS 0x5
42#define DPLL_LOCKED 0x7
43
39int omap2_clk_init(void); 44int omap2_clk_init(void);
40int omap2_clk_enable(struct clk *clk); 45int omap2_clk_enable(struct clk *clk);
41void omap2_clk_disable(struct clk *clk); 46void omap2_clk_disable(struct clk *clk);
@@ -44,6 +49,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
44int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); 49int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
45int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); 50int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
46long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); 51long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
52unsigned long omap3_dpll_recalc(struct clk *clk);
53unsigned long omap3_clkoutx2_recalc(struct clk *clk);
54void omap3_dpll_allow_idle(struct clk *clk);
55void omap3_dpll_deny_idle(struct clk *clk);
56u32 omap3_dpll_autoidle_read(struct clk *clk);
57int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
58int omap3_noncore_dpll_enable(struct clk *clk);
59void omap3_noncore_dpll_disable(struct clk *clk);
47 60
48#ifdef CONFIG_OMAP_RESET_CLOCKS 61#ifdef CONFIG_OMAP_RESET_CLOCKS
49void omap2_clk_disable_unused(struct clk *clk); 62void omap2_clk_disable_unused(struct clk *clk);