diff options
author | Mike Turquette <mturquette@linaro.org> | 2012-11-10 18:58:41 -0500 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2012-11-12 15:55:50 -0500 |
commit | 32cc002116b866151ca24c6e9110ba8a93754753 (patch) | |
tree | 4a7d3f08bf774ed72d37bd0de541d9dac5e3083e /arch/arm/mach-omap2/clkt_dpll.c | |
parent | f5dd3bb53ca45f3b47c6889e5920c562f5a37359 (diff) |
ARM: OMAP4: clock: Convert to common clk
Convert all OMAP4 specific platform files to use COMMON clk
and keep all the changes under the CONFIG_COMMON_CLK macro check
so it does not break any existing code. At a later point switch
to COMMON clk and get rid of all old/legacy code.
This converts all apis which will be called directly from COMMON
clk to take a struct clk_hw parameter, and all the internal platform
apis to take a struct clk_hw_omap parameter.
Changes are based off the original patch from Mike Turquette.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: created new omap2_clksel_find_parent_index() rather than
modifying omap2_init_clksel_parent(); moved clkhwops_iclk_wait to
clkt_iclk.c to fix OMAP4-only builds; added clk-provider.h include to clock.h
to try to fix some 3430-builds]
[mturquette@ti.com: squash patch for omap2_clkops_{en,dis}able_clkdm;
omap2_dflt_clk_is_enabled should not enable clocks]
Signed-off-by: Mike Turquette <mturquette@ti.com>
[paul@pwsan.com: fix compiler warning; update to apply; added kerneldoc on
non-trivial new functions; added the dpll3xxx clockdomain modifications]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'arch/arm/mach-omap2/clkt_dpll.c')
-rw-r--r-- | arch/arm/mach-omap2/clkt_dpll.c | 54 |
1 files changed, 53 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 8463cc356245..f343389fc6e8 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c | |||
@@ -16,7 +16,11 @@ | |||
16 | 16 | ||
17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
18 | #include <linux/errno.h> | 18 | #include <linux/errno.h> |
19 | #ifdef CONFIG_COMMON_CLK | ||
20 | #include <linux/clk-provider.h> | ||
21 | #else | ||
19 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
23 | #endif | ||
20 | #include <linux/io.h> | 24 | #include <linux/io.h> |
21 | 25 | ||
22 | #include <asm/div64.h> | 26 | #include <asm/div64.h> |
@@ -76,7 +80,11 @@ | |||
76 | * (assuming that it is counting N upwards), or -2 if the enclosing loop | 80 | * (assuming that it is counting N upwards), or -2 if the enclosing loop |
77 | * should skip to the next iteration (again assuming N is increasing). | 81 | * should skip to the next iteration (again assuming N is increasing). |
78 | */ | 82 | */ |
83 | #ifdef CONFIG_COMMON_CLK | ||
84 | static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n) | ||
85 | #else | ||
79 | static int _dpll_test_fint(struct clk *clk, u8 n) | 86 | static int _dpll_test_fint(struct clk *clk, u8 n) |
87 | #endif | ||
80 | { | 88 | { |
81 | struct dpll_data *dd; | 89 | struct dpll_data *dd; |
82 | long fint, fint_min, fint_max; | 90 | long fint, fint_min, fint_max; |
@@ -85,7 +93,11 @@ static int _dpll_test_fint(struct clk *clk, u8 n) | |||
85 | dd = clk->dpll_data; | 93 | dd = clk->dpll_data; |
86 | 94 | ||
87 | /* DPLL divider must result in a valid jitter correction val */ | 95 | /* DPLL divider must result in a valid jitter correction val */ |
96 | #ifdef CONFIG_COMMON_CLK | ||
97 | fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; | ||
98 | #else | ||
88 | fint = __clk_get_rate(__clk_get_parent(clk)) / n; | 99 | fint = __clk_get_rate(__clk_get_parent(clk)) / n; |
100 | #endif | ||
89 | 101 | ||
90 | if (cpu_is_omap24xx()) { | 102 | if (cpu_is_omap24xx()) { |
91 | /* Should not be called for OMAP2, so warn if it is called */ | 103 | /* Should not be called for OMAP2, so warn if it is called */ |
@@ -186,15 +198,24 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, | |||
186 | } | 198 | } |
187 | 199 | ||
188 | /* Public functions */ | 200 | /* Public functions */ |
189 | 201 | #ifdef CONFIG_COMMON_CLK | |
202 | u8 omap2_init_dpll_parent(struct clk_hw *hw) | ||
203 | { | ||
204 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | ||
205 | #else | ||
190 | void omap2_init_dpll_parent(struct clk *clk) | 206 | void omap2_init_dpll_parent(struct clk *clk) |
191 | { | 207 | { |
208 | #endif | ||
192 | u32 v; | 209 | u32 v; |
193 | struct dpll_data *dd; | 210 | struct dpll_data *dd; |
194 | 211 | ||
195 | dd = clk->dpll_data; | 212 | dd = clk->dpll_data; |
196 | if (!dd) | 213 | if (!dd) |
214 | #ifdef CONFIG_COMMON_CLK | ||
215 | return -EINVAL; | ||
216 | #else | ||
197 | return; | 217 | return; |
218 | #endif | ||
198 | 219 | ||
199 | v = __raw_readl(dd->control_reg); | 220 | v = __raw_readl(dd->control_reg); |
200 | v &= dd->enable_mask; | 221 | v &= dd->enable_mask; |
@@ -204,18 +225,34 @@ void omap2_init_dpll_parent(struct clk *clk) | |||
204 | if (cpu_is_omap24xx()) { | 225 | if (cpu_is_omap24xx()) { |
205 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || | 226 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || |
206 | v == OMAP2XXX_EN_DPLL_FRBYPASS) | 227 | v == OMAP2XXX_EN_DPLL_FRBYPASS) |
228 | #ifdef CONFIG_COMMON_CLK | ||
229 | return 1; | ||
230 | #else | ||
207 | clk_reparent(clk, dd->clk_bypass); | 231 | clk_reparent(clk, dd->clk_bypass); |
232 | #endif | ||
208 | } else if (cpu_is_omap34xx()) { | 233 | } else if (cpu_is_omap34xx()) { |
209 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | 234 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || |
210 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | 235 | v == OMAP3XXX_EN_DPLL_FRBYPASS) |
236 | #ifdef CONFIG_COMMON_CLK | ||
237 | return 1; | ||
238 | #else | ||
211 | clk_reparent(clk, dd->clk_bypass); | 239 | clk_reparent(clk, dd->clk_bypass); |
240 | #endif | ||
212 | } else if (soc_is_am33xx() || cpu_is_omap44xx()) { | 241 | } else if (soc_is_am33xx() || cpu_is_omap44xx()) { |
213 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | 242 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || |
214 | v == OMAP4XXX_EN_DPLL_FRBYPASS || | 243 | v == OMAP4XXX_EN_DPLL_FRBYPASS || |
215 | v == OMAP4XXX_EN_DPLL_MNBYPASS) | 244 | v == OMAP4XXX_EN_DPLL_MNBYPASS) |
245 | #ifdef CONFIG_COMMON_CLK | ||
246 | return 1; | ||
247 | #else | ||
216 | clk_reparent(clk, dd->clk_bypass); | 248 | clk_reparent(clk, dd->clk_bypass); |
249 | #endif | ||
217 | } | 250 | } |
251 | #ifdef CONFIG_COMMON_CLK | ||
252 | return 0; | ||
253 | #else | ||
218 | return; | 254 | return; |
255 | #endif | ||
219 | } | 256 | } |
220 | 257 | ||
221 | /** | 258 | /** |
@@ -232,7 +269,11 @@ void omap2_init_dpll_parent(struct clk *clk) | |||
232 | * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 | 269 | * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 |
233 | * if the clock @clk is not a DPLL. | 270 | * if the clock @clk is not a DPLL. |
234 | */ | 271 | */ |
272 | #ifdef CONFIG_COMMON_CLK | ||
273 | unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) | ||
274 | #else | ||
235 | u32 omap2_get_dpll_rate(struct clk *clk) | 275 | u32 omap2_get_dpll_rate(struct clk *clk) |
276 | #endif | ||
236 | { | 277 | { |
237 | long long dpll_clk; | 278 | long long dpll_clk; |
238 | u32 dpll_mult, dpll_div, v; | 279 | u32 dpll_mult, dpll_div, v; |
@@ -288,8 +329,15 @@ u32 omap2_get_dpll_rate(struct clk *clk) | |||
288 | * (expensive) function again. Returns ~0 if the target rate cannot | 329 | * (expensive) function again. Returns ~0 if the target rate cannot |
289 | * be rounded, or the rounded rate upon success. | 330 | * be rounded, or the rounded rate upon success. |
290 | */ | 331 | */ |
332 | #ifdef CONFIG_COMMON_CLK | ||
333 | long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, | ||
334 | unsigned long *parent_rate) | ||
335 | { | ||
336 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | ||
337 | #else | ||
291 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) | 338 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) |
292 | { | 339 | { |
340 | #endif | ||
293 | int m, n, r, scaled_max_m; | 341 | int m, n, r, scaled_max_m; |
294 | unsigned long scaled_rt_rp; | 342 | unsigned long scaled_rt_rp; |
295 | unsigned long new_rate = 0; | 343 | unsigned long new_rate = 0; |
@@ -303,7 +351,11 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) | |||
303 | dd = clk->dpll_data; | 351 | dd = clk->dpll_data; |
304 | 352 | ||
305 | ref_rate = __clk_get_rate(dd->clk_ref); | 353 | ref_rate = __clk_get_rate(dd->clk_ref); |
354 | #ifdef CONFIG_COMMON_CLK | ||
355 | clk_name = __clk_get_name(hw->clk); | ||
356 | #else | ||
306 | clk_name = __clk_get_name(clk); | 357 | clk_name = __clk_get_name(clk); |
358 | #endif | ||
307 | pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", | 359 | pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n", |
308 | clk_name, target_rate); | 360 | clk_name, target_rate); |
309 | 361 | ||