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authorLinus Torvalds <torvalds@linux-foundation.org>2013-02-21 18:27:22 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-02-21 18:27:22 -0500
commitbab588fcfb6335c767d811a8955979f5440328e0 (patch)
tree2a862ddf47a82be885a8e7945a17cc3ff7a658b9 /arch/arm/mach-omap2/cclock44xx_data.c
parent3298a3511f1e73255a8dc023efd909e569eea037 (diff)
parent9cb0d1babfcb1b4ac248c09425f7d5de1e771133 (diff)
Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC-specific updates from Arnd Bergmann: "This is a larger set of new functionality for the existing SoC families, including: - vt8500 gains support for new CPU cores, notably the Cortex-A9 based wm8850 - prima2 gains support for the "marco" SoC family, its SMP based cousin - tegra gains support for the new Tegra4 (Tegra114) family - socfpga now supports a newer version of the hardware including SMP - i.mx31 and bcm2835 are now using DT probing for their clocks - lots of updates for sh-mobile - OMAP updates for clocks, power management and USB - i.mx6q and tegra now support cpuidle - kirkwood now supports PCIe hot plugging - tegra clock support is updated - tegra USB PHY probing gets implemented diffently" * tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits) ARM: prima2: remove duplicate v7_invalidate_l1 ARM: shmobile: r8a7779: Correct TMU clock support again ARM: prima2: fix __init section for cpu hotplug ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3) ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3) arm: socfpga: Add SMP support for actual socfpga harware arm: Add v7_invalidate_l1 to cache-v7.S arm: socfpga: Add entries to enable make dtbs socfpga arm: socfpga: Add new device tree source for actual socfpga HW ARM: tegra: sort Kconfig selects for Tegra114 ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114 ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC ARM: tegra: Fix build error for gic update ARM: tegra: remove empty tegra_smp_init_cpus() ARM: shmobile: Register ARM architected timer ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move ARM: shmobile: r8a7779: Correct TMU clock support ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles ARM: mxs: use apbx bus clock to drive the timers on timrotv2 ...
Diffstat (limited to 'arch/arm/mach-omap2/cclock44xx_data.c')
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c578
1 files changed, 119 insertions, 459 deletions
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index a2cc046b47f4..cebe2b31943e 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -16,6 +16,10 @@
16 * XXX Some of the ES1 clocks have been removed/changed; once support 16 * XXX Some of the ES1 clocks have been removed/changed; once support
17 * is added for discriminating clocks by ES level, these should be added back 17 * is added for discriminating clocks by ES level, these should be added back
18 * in. 18 * in.
19 *
20 * XXX All of the remaining MODULEMODE clock nodes should be removed
21 * once the drivers are updated to use pm_runtime or to use the appropriate
22 * upstream clock node for rate/parent selection.
19 */ 23 */
20 24
21#include <linux/kernel.h> 25#include <linux/kernel.h>
@@ -315,7 +319,7 @@ DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
315 OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT, 319 OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
316 OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); 320 OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
317 321
318static const struct clk_ops dmic_fck_ops = { 322static const struct clk_ops dpll_hsd_ops = {
319 .enable = &omap2_dflt_clk_enable, 323 .enable = &omap2_dflt_clk_enable,
320 .disable = &omap2_dflt_clk_disable, 324 .disable = &omap2_dflt_clk_disable,
321 .is_enabled = &omap2_dflt_clk_is_enabled, 325 .is_enabled = &omap2_dflt_clk_is_enabled,
@@ -325,6 +329,12 @@ static const struct clk_ops dmic_fck_ops = {
325 .init = &omap2_init_clk_clkdm, 329 .init = &omap2_init_clk_clkdm,
326}; 330};
327 331
332static const struct clk_ops func_dmic_abe_gfclk_ops = {
333 .recalc_rate = &omap2_clksel_recalc,
334 .get_parent = &omap2_clksel_find_parent_index,
335 .set_parent = &omap2_clksel_set_parent,
336};
337
328static const char *dpll_core_m3x2_ck_parents[] = { 338static const char *dpll_core_m3x2_ck_parents[] = {
329 "dpll_core_x2_ck", 339 "dpll_core_x2_ck",
330}; 340};
@@ -340,7 +350,7 @@ DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
340 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 350 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
341 OMAP4430_CM_DIV_M3_DPLL_CORE, 351 OMAP4430_CM_DIV_M3_DPLL_CORE,
342 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, 352 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
343 dpll_core_m3x2_ck_parents, dmic_fck_ops); 353 dpll_core_m3x2_ck_parents, dpll_hsd_ops);
344 354
345DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck", 355DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
346 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE, 356 &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
@@ -547,7 +557,7 @@ DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
547 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 557 OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
548 OMAP4430_CM_DIV_M3_DPLL_PER, 558 OMAP4430_CM_DIV_M3_DPLL_PER,
549 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL, 559 OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
550 dpll_per_m3x2_ck_parents, dmic_fck_ops); 560 dpll_per_m3x2_ck_parents, dpll_hsd_ops);
551 561
552DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck, 562DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
553 0x0, OMAP4430_CM_DIV_M4_DPLL_PER, 563 0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
@@ -749,10 +759,6 @@ DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
749 OMAP4430_CM_L4SEC_AES2_CLKCTRL, 759 OMAP4430_CM_L4SEC_AES2_CLKCTRL,
750 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 760 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
751 761
752DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0,
753 OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
754 0x0, NULL);
755
756DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0, 762DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
757 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, 763 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
758 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL); 764 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
@@ -774,11 +780,6 @@ DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
774 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT, 780 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
775 0x0, NULL); 781 0x0, NULL);
776 782
777DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0,
778 OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
779 OMAP4430_MODULEMODE_SWCTRL_SHIFT,
780 0x0, NULL);
781
782static const char *dmic_sync_mux_ck_parents[] = { 783static const char *dmic_sync_mux_ck_parents[] = {
783 "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk", 784 "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
784}; 785};
@@ -795,23 +796,13 @@ static const struct clksel func_dmic_abe_gfclk_sel[] = {
795 { .parent = NULL }, 796 { .parent = NULL },
796}; 797};
797 798
798static const char *dmic_fck_parents[] = { 799static const char *func_dmic_abe_gfclk_parents[] = {
799 "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk", 800 "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
800}; 801};
801 802
802/* Merged func_dmic_abe_gfclk into dmic */ 803DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
803static struct clk dmic_fck; 804 OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
804 805 func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
805DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel,
806 OMAP4430_CM1_ABE_DMIC_CLKCTRL,
807 OMAP4430_CLKSEL_SOURCE_MASK,
808 OMAP4430_CM1_ABE_DMIC_CLKCTRL,
809 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
810 dmic_fck_parents, dmic_fck_ops);
811
812DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0,
813 OMAP4430_CM_TESLA_TESLA_CLKCTRL,
814 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
815 806
816DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0, 807DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
817 OMAP4430_CM_DSS_DSS_CLKCTRL, 808 OMAP4430_CM_DSS_DSS_CLKCTRL,
@@ -833,177 +824,57 @@ DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
833 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT, 824 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
834 0x0, NULL); 825 0x0, NULL);
835 826
836DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
837 OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
838 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
839
840DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
841 OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
842 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
843
844DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
845 OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
846 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
847
848DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0, 827DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
849 OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT, 828 OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
850 OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL); 829 OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
851 830
852DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0,
853 OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
854 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
855
856DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 831DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
857 OMAP4430_CM_WKUP_GPIO1_CLKCTRL, 832 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
858 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); 833 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
859 834
860DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0,
861 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
862 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
863
864DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 835DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
865 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 836 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
866 0x0, NULL); 837 0x0, NULL);
867 838
868DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0,
869 OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
870 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
871
872DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 839DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
873 OMAP4430_CM_L4PER_GPIO3_CLKCTRL, 840 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
874 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL); 841 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
875 842
876DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0,
877 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
878 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
879
880DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 843DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
881 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 844 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
882 0x0, NULL); 845 0x0, NULL);
883 846
884DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0,
885 OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
886 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
887
888DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 847DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
889 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 848 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
890 0x0, NULL); 849 0x0, NULL);
891 850
892DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0,
893 OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
894 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
895
896DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0, 851DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
897 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 852 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
898 0x0, NULL); 853 0x0, NULL);
899 854
900DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0,
901 OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
902 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
903
904DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0,
905 OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
906 0x0, NULL);
907
908static const struct clksel sgx_clk_mux_sel[] = { 855static const struct clksel sgx_clk_mux_sel[] = {
909 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, 856 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
910 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, 857 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
911 { .parent = NULL }, 858 { .parent = NULL },
912}; 859};
913 860
914static const char *gpu_fck_parents[] = { 861static const char *sgx_clk_mux_parents[] = {
915 "dpll_core_m7x2_ck", "dpll_per_m7x2_ck", 862 "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
916}; 863};
917 864
918/* Merged sgx_clk_mux into gpu */ 865DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
919DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel, 866 OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
920 OMAP4430_CM_GFX_GFX_CLKCTRL, 867 sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
921 OMAP4430_CLKSEL_SGX_FCLK_MASK,
922 OMAP4430_CM_GFX_GFX_CLKCTRL,
923 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
924 gpu_fck_parents, dmic_fck_ops);
925
926DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0,
927 OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
928 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
929 868
930DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0, 869DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
931 OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT, 870 OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
932 OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO, 871 OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
933 NULL); 872 NULL);
934 873
935DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
936 OMAP4430_CM_L4PER_I2C1_CLKCTRL,
937 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
938
939DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
940 OMAP4430_CM_L4PER_I2C2_CLKCTRL,
941 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
942
943DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
944 OMAP4430_CM_L4PER_I2C3_CLKCTRL,
945 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
946
947DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
948 OMAP4430_CM_L4PER_I2C4_CLKCTRL,
949 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
950
951DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
952 OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
953 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
954
955DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0, 874DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
956 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, 875 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
957 0x0, NULL); 876 0x0, NULL);
958 877
959DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
960 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
961 0x0, NULL);
962
963DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
964 OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
965 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
966
967DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
968 OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
969 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
970
971static struct clk l3_instr_ick;
972
973static const char *l3_instr_ick_parent_names[] = {
974 "l3_div_ck",
975};
976
977static const struct clk_ops l3_instr_ick_ops = {
978 .enable = &omap2_dflt_clk_enable,
979 .disable = &omap2_dflt_clk_disable,
980 .is_enabled = &omap2_dflt_clk_is_enabled,
981 .init = &omap2_init_clk_clkdm,
982};
983
984static struct clk_hw_omap l3_instr_ick_hw = {
985 .hw = {
986 .clk = &l3_instr_ick,
987 },
988 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
989 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
990 .clkdm_name = "l3_instr_clkdm",
991};
992
993DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
994
995static struct clk l3_main_3_ick;
996static struct clk_hw_omap l3_main_3_ick_hw = {
997 .hw = {
998 .clk = &l3_main_3_ick,
999 },
1000 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1001 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1002 .clkdm_name = "l3_instr_clkdm",
1003};
1004
1005DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
1006
1007DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, 878DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1008 OMAP4430_CM1_ABE_MCASP_CLKCTRL, 879 OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1009 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT, 880 OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
@@ -1016,17 +887,13 @@ static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1016 { .parent = NULL }, 887 { .parent = NULL },
1017}; 888};
1018 889
1019static const char *mcasp_fck_parents[] = { 890static const char *func_mcasp_abe_gfclk_parents[] = {
1020 "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk", 891 "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1021}; 892};
1022 893
1023/* Merged func_mcasp_abe_gfclk into mcasp */ 894DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
1024DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel, 895 OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
1025 OMAP4430_CM1_ABE_MCASP_CLKCTRL, 896 func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
1026 OMAP4430_CLKSEL_SOURCE_MASK,
1027 OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1028 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1029 mcasp_fck_parents, dmic_fck_ops);
1030 897
1031DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, 898DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1032 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, 899 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
@@ -1040,17 +907,14 @@ static const struct clksel func_mcbsp1_gfclk_sel[] = {
1040 { .parent = NULL }, 907 { .parent = NULL },
1041}; 908};
1042 909
1043static const char *mcbsp1_fck_parents[] = { 910static const char *func_mcbsp1_gfclk_parents[] = {
1044 "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk", 911 "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1045}; 912};
1046 913
1047/* Merged func_mcbsp1_gfclk into mcbsp1 */ 914DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
1048DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel, 915 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1049 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, 916 OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
1050 OMAP4430_CLKSEL_SOURCE_MASK, 917 func_dmic_abe_gfclk_ops);
1051 OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1052 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1053 mcbsp1_fck_parents, dmic_fck_ops);
1054 918
1055DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, 919DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1056 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, 920 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
@@ -1064,17 +928,14 @@ static const struct clksel func_mcbsp2_gfclk_sel[] = {
1064 { .parent = NULL }, 928 { .parent = NULL },
1065}; 929};
1066 930
1067static const char *mcbsp2_fck_parents[] = { 931static const char *func_mcbsp2_gfclk_parents[] = {
1068 "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk", 932 "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1069}; 933};
1070 934
1071/* Merged func_mcbsp2_gfclk into mcbsp2 */ 935DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
1072DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel, 936 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1073 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, 937 OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
1074 OMAP4430_CLKSEL_SOURCE_MASK, 938 func_dmic_abe_gfclk_ops);
1075 OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1076 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1077 mcbsp2_fck_parents, dmic_fck_ops);
1078 939
1079DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0, 940DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1080 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, 941 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
@@ -1088,17 +949,14 @@ static const struct clksel func_mcbsp3_gfclk_sel[] = {
1088 { .parent = NULL }, 949 { .parent = NULL },
1089}; 950};
1090 951
1091static const char *mcbsp3_fck_parents[] = { 952static const char *func_mcbsp3_gfclk_parents[] = {
1092 "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk", 953 "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1093}; 954};
1094 955
1095/* Merged func_mcbsp3_gfclk into mcbsp3 */ 956DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
1096DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel, 957 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1097 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, 958 OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
1098 OMAP4430_CLKSEL_SOURCE_MASK, 959 func_dmic_abe_gfclk_ops);
1099 OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1100 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1101 mcbsp3_fck_parents, dmic_fck_ops);
1102 960
1103static const char *mcbsp4_sync_mux_ck_parents[] = { 961static const char *mcbsp4_sync_mux_ck_parents[] = {
1104 "func_96m_fclk", "per_abe_nc_fclk", 962 "func_96m_fclk", "per_abe_nc_fclk",
@@ -1115,37 +973,14 @@ static const struct clksel per_mcbsp4_gfclk_sel[] = {
1115 { .parent = NULL }, 973 { .parent = NULL },
1116}; 974};
1117 975
1118static const char *mcbsp4_fck_parents[] = { 976static const char *per_mcbsp4_gfclk_parents[] = {
1119 "mcbsp4_sync_mux_ck", "pad_clks_ck", 977 "mcbsp4_sync_mux_ck", "pad_clks_ck",
1120}; 978};
1121 979
1122/* Merged per_mcbsp4_gfclk into mcbsp4 */ 980DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
1123DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel, 981 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1124 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, 982 OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
1125 OMAP4430_CLKSEL_SOURCE_24_24_MASK, 983 func_dmic_abe_gfclk_ops);
1126 OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1127 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1128 mcbsp4_fck_parents, dmic_fck_ops);
1129
1130DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0,
1131 OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1132 0x0, NULL);
1133
1134DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1135 OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1136 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1137
1138DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1139 OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1140 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1141
1142DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1143 OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1144 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1145
1146DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1147 OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
1148 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1149 984
1150static const struct clksel hsmmc1_fclk_sel[] = { 985static const struct clksel hsmmc1_fclk_sel[] = {
1151 { .parent = &func_64m_fclk, .rates = div_1_0_rates }, 986 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
@@ -1153,69 +988,22 @@ static const struct clksel hsmmc1_fclk_sel[] = {
1153 { .parent = NULL }, 988 { .parent = NULL },
1154}; 989};
1155 990
1156static const char *mmc1_fck_parents[] = { 991static const char *hsmmc1_fclk_parents[] = {
1157 "func_64m_fclk", "func_96m_fclk", 992 "func_64m_fclk", "func_96m_fclk",
1158}; 993};
1159 994
1160/* Merged hsmmc1_fclk into mmc1 */ 995DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
1161DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel, 996 OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1162 OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK, 997 hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
1163 OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
1164 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1165 mmc1_fck_parents, dmic_fck_ops);
1166
1167/* Merged hsmmc2_fclk into mmc2 */
1168DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
1169 OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1170 OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
1171 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1172 mmc1_fck_parents, dmic_fck_ops);
1173
1174DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1175 OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
1176 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1177
1178DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1179 OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
1180 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1181
1182DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1183 OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
1184 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1185
1186DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
1187 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1188 OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
1189
1190DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0,
1191 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1192 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1193
1194static struct clk ocp_wp_noc_ick;
1195
1196static struct clk_hw_omap ocp_wp_noc_ick_hw = {
1197 .hw = {
1198 .clk = &ocp_wp_noc_ick,
1199 },
1200 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
1201 .enable_bit = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1202 .clkdm_name = "l3_instr_clkdm",
1203};
1204
1205DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
1206 998
1207DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0, 999DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
1208 OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT, 1000 OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1209 0x0, NULL); 1001 hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
1210 1002
1211DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0, 1003DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
1212 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, 1004 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
1213 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1005 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1214 1006
1215DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
1216 OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1217 0x0, NULL);
1218
1219DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0, 1007DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
1220 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, 1008 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1221 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL); 1009 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
@@ -1232,10 +1020,6 @@ DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
1232 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, 1020 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1233 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL); 1021 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
1234 1022
1235DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0,
1236 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1237 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1238
1239DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0, 1023DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
1240 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, 1024 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1241 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL); 1025 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
@@ -1249,10 +1033,6 @@ DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
1249 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, 1033 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1250 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL); 1034 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
1251 1035
1252DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0,
1253 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1254 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1255
1256DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 1036DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1257 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, 1037 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1258 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1038 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
@@ -1271,52 +1051,35 @@ static const struct clksel dmt1_clk_mux_sel[] = {
1271 { .parent = NULL }, 1051 { .parent = NULL },
1272}; 1052};
1273 1053
1274/* Merged dmt1_clk_mux into timer1 */ 1054DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
1275DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel, 1055 OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1276 OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK, 1056 abe_dpll_bypass_clk_mux_ck_parents,
1277 OMAP4430_CM_WKUP_TIMER1_CLKCTRL, 1057 func_dmic_abe_gfclk_ops);
1278 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, 1058
1279 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); 1059DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1280 1060 OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
1281/* Merged cm2_dm10_mux into timer10 */ 1061 abe_dpll_bypass_clk_mux_ck_parents,
1282DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel, 1062 func_dmic_abe_gfclk_ops);
1283 OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, 1063
1284 OMAP4430_CLKSEL_MASK, 1064DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1285 OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, 1065 OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
1286 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, 1066 abe_dpll_bypass_clk_mux_ck_parents,
1287 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); 1067 func_dmic_abe_gfclk_ops);
1288 1068
1289/* Merged cm2_dm11_mux into timer11 */ 1069DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1290DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel, 1070 OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1291 OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, 1071 abe_dpll_bypass_clk_mux_ck_parents,
1292 OMAP4430_CLKSEL_MASK, 1072 func_dmic_abe_gfclk_ops);
1293 OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, 1073
1294 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, 1074DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1295 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops); 1075 OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
1296 1076 abe_dpll_bypass_clk_mux_ck_parents,
1297/* Merged cm2_dm2_mux into timer2 */ 1077 func_dmic_abe_gfclk_ops);
1298DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel, 1078
1299 OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, 1079DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1300 OMAP4430_CLKSEL_MASK, 1080 OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
1301 OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, 1081 abe_dpll_bypass_clk_mux_ck_parents,
1302 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL, 1082 func_dmic_abe_gfclk_ops);
1303 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1304
1305/* Merged cm2_dm3_mux into timer3 */
1306DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1307 OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1308 OMAP4430_CLKSEL_MASK,
1309 OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1310 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1311 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1312
1313/* Merged cm2_dm4_mux into timer4 */
1314DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1315 OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1316 OMAP4430_CLKSEL_MASK,
1317 OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1318 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1319 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1320 1083
1321static const struct clksel timer5_sync_mux_sel[] = { 1084static const struct clksel timer5_sync_mux_sel[] = {
1322 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, 1085 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
@@ -1324,61 +1087,30 @@ static const struct clksel timer5_sync_mux_sel[] = {
1324 { .parent = NULL }, 1087 { .parent = NULL },
1325}; 1088};
1326 1089
1327static const char *timer5_fck_parents[] = { 1090static const char *timer5_sync_mux_parents[] = {
1328 "syc_clk_div_ck", "sys_32k_ck", 1091 "syc_clk_div_ck", "sys_32k_ck",
1329}; 1092};
1330 1093
1331/* Merged timer5_sync_mux into timer5 */ 1094DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1332DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel, 1095 OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
1333 OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK, 1096 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1334 OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1335 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1336 timer5_fck_parents, dmic_fck_ops);
1337
1338/* Merged timer6_sync_mux into timer6 */
1339DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel,
1340 OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
1341 OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1342 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1343 timer5_fck_parents, dmic_fck_ops);
1344
1345/* Merged timer7_sync_mux into timer7 */
1346DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel,
1347 OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
1348 OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1349 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1350 timer5_fck_parents, dmic_fck_ops);
1351
1352/* Merged timer8_sync_mux into timer8 */
1353DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel,
1354 OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
1355 OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1356 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1357 timer5_fck_parents, dmic_fck_ops);
1358
1359/* Merged cm2_dm9_mux into timer9 */
1360DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1361 OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1362 OMAP4430_CLKSEL_MASK,
1363 OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1364 OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1365 abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1366
1367DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1368 OMAP4430_CM_L4PER_UART1_CLKCTRL,
1369 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1370 1097
1371DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0, 1098DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1372 OMAP4430_CM_L4PER_UART2_CLKCTRL, 1099 OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
1373 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1100 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1374 1101
1375DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0, 1102DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1376 OMAP4430_CM_L4PER_UART3_CLKCTRL, 1103 OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
1377 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1104 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1378 1105
1379DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0, 1106DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1380 OMAP4430_CM_L4PER_UART4_CLKCTRL, 1107 OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
1381 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL); 1108 timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1109
1110DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1111 OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
1112 abe_dpll_bypass_clk_mux_ck_parents,
1113 func_dmic_abe_gfclk_ops);
1382 1114
1383static struct clk usb_host_fs_fck; 1115static struct clk usb_host_fs_fck;
1384 1116
@@ -1512,18 +1244,6 @@ DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
1512 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT, 1244 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
1513 0x0, NULL); 1245 0x0, NULL);
1514 1246
1515DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1516 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1517 0x0, NULL);
1518
1519DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1520 OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1521 0x0, NULL);
1522
1523DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1524 OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1525 0x0, NULL);
1526
1527/* Remaining optional clocks */ 1247/* Remaining optional clocks */
1528static const char *pmd_stm_clock_mux_ck_parents[] = { 1248static const char *pmd_stm_clock_mux_ck_parents[] = {
1529 "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck", 1249 "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
@@ -1774,106 +1494,61 @@ static struct omap_clk omap44xx_clks[] = {
1774 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), 1494 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
1775 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), 1495 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
1776 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), 1496 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
1777 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
1778 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), 1497 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
1779 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X), 1498 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
1780 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X), 1499 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
1781 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
1782 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 1500 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
1783 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), 1501 CLK(NULL, "func_dmic_abe_gfclk", &func_dmic_abe_gfclk, CK_443X),
1784 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
1785 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X), 1502 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
1786 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X), 1503 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
1787 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X), 1504 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
1788 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X), 1505 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
1789 CLK(NULL, "dss_fck", &dss_fck, CK_443X), 1506 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
1790 CLK("omapdss_dss", "ick", &dss_fck, CK_443X), 1507 CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
1791 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
1792 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
1793 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
1794 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), 1508 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
1795 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
1796 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), 1509 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
1797 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
1798 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), 1510 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
1799 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
1800 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), 1511 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
1801 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
1802 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), 1512 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
1803 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
1804 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), 1513 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
1805 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
1806 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), 1514 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
1807 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), 1515 CLK(NULL, "sgx_clk_mux", &sgx_clk_mux, CK_443X),
1808 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
1809 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
1810 CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
1811 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), 1516 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
1812 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
1813 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
1814 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
1815 CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
1816 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
1817 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), 1517 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
1818 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
1819 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
1820 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
1821 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
1822 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
1823 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), 1518 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
1824 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), 1519 CLK(NULL, "func_mcasp_abe_gfclk", &func_mcasp_abe_gfclk, CK_443X),
1825 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), 1520 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
1826 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X), 1521 CLK(NULL, "func_mcbsp1_gfclk", &func_mcbsp1_gfclk, CK_443X),
1827 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), 1522 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
1828 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X), 1523 CLK(NULL, "func_mcbsp2_gfclk", &func_mcbsp2_gfclk, CK_443X),
1829 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), 1524 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
1830 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X), 1525 CLK(NULL, "func_mcbsp3_gfclk", &func_mcbsp3_gfclk, CK_443X),
1831 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), 1526 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
1832 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X), 1527 CLK(NULL, "per_mcbsp4_gfclk", &per_mcbsp4_gfclk, CK_443X),
1833 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), 1528 CLK(NULL, "hsmmc1_fclk", &hsmmc1_fclk, CK_443X),
1834 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X), 1529 CLK(NULL, "hsmmc2_fclk", &hsmmc2_fclk, CK_443X),
1835 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
1836 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
1837 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
1838 CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
1839 CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
1840 CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
1841 CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
1842 CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
1843 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
1844 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
1845 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
1846 CLK(NULL, "rng_ick", &rng_ick, CK_443X),
1847 CLK("omap_rng", "ick", &rng_ick, CK_443X),
1848 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), 1530 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
1849 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
1850 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), 1531 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
1851 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), 1532 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
1852 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), 1533 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
1853 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), 1534 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
1854 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
1855 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), 1535 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
1856 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), 1536 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
1857 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), 1537 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
1858 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
1859 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), 1538 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
1860 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), 1539 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
1861 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), 1540 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
1862 CLK(NULL, "timer1_fck", &timer1_fck, CK_443X), 1541 CLK(NULL, "dmt1_clk_mux", &dmt1_clk_mux, CK_443X),
1863 CLK(NULL, "timer10_fck", &timer10_fck, CK_443X), 1542 CLK(NULL, "cm2_dm10_mux", &cm2_dm10_mux, CK_443X),
1864 CLK(NULL, "timer11_fck", &timer11_fck, CK_443X), 1543 CLK(NULL, "cm2_dm11_mux", &cm2_dm11_mux, CK_443X),
1865 CLK(NULL, "timer2_fck", &timer2_fck, CK_443X), 1544 CLK(NULL, "cm2_dm2_mux", &cm2_dm2_mux, CK_443X),
1866 CLK(NULL, "timer3_fck", &timer3_fck, CK_443X), 1545 CLK(NULL, "cm2_dm3_mux", &cm2_dm3_mux, CK_443X),
1867 CLK(NULL, "timer4_fck", &timer4_fck, CK_443X), 1546 CLK(NULL, "cm2_dm4_mux", &cm2_dm4_mux, CK_443X),
1868 CLK(NULL, "timer5_fck", &timer5_fck, CK_443X), 1547 CLK(NULL, "timer5_sync_mux", &timer5_sync_mux, CK_443X),
1869 CLK(NULL, "timer6_fck", &timer6_fck, CK_443X), 1548 CLK(NULL, "timer6_sync_mux", &timer6_sync_mux, CK_443X),
1870 CLK(NULL, "timer7_fck", &timer7_fck, CK_443X), 1549 CLK(NULL, "timer7_sync_mux", &timer7_sync_mux, CK_443X),
1871 CLK(NULL, "timer8_fck", &timer8_fck, CK_443X), 1550 CLK(NULL, "timer8_sync_mux", &timer8_sync_mux, CK_443X),
1872 CLK(NULL, "timer9_fck", &timer9_fck, CK_443X), 1551 CLK(NULL, "cm2_dm9_mux", &cm2_dm9_mux, CK_443X),
1873 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
1874 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
1875 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
1876 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
1877 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), 1552 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
1878 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X), 1553 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
1879 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), 1554 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
@@ -1901,9 +1576,6 @@ static struct omap_clk omap44xx_clks[] = {
1901 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X), 1576 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
1902 CLK(NULL, "usim_ck", &usim_ck, CK_443X), 1577 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
1903 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), 1578 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
1904 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
1905 CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
1906 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
1907 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), 1579 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
1908 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), 1580 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
1909 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 1581 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
@@ -1980,15 +1652,6 @@ static struct omap_clk omap44xx_clks[] = {
1980 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X), 1652 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
1981}; 1653};
1982 1654
1983static const char *enable_init_clks[] = {
1984 "emif1_fck",
1985 "emif2_fck",
1986 "gpmc_ick",
1987 "l3_instr_ick",
1988 "l3_main_3_ick",
1989 "ocp_wp_noc_ick",
1990};
1991
1992int __init omap4xxx_clk_init(void) 1655int __init omap4xxx_clk_init(void)
1993{ 1656{
1994 u32 cpu_clkflg; 1657 u32 cpu_clkflg;
@@ -2019,9 +1682,6 @@ int __init omap4xxx_clk_init(void)
2019 1682
2020 omap2_clk_disable_autoidle_all(); 1683 omap2_clk_disable_autoidle_all();
2021 1684
2022 omap2_clk_enable_init_clocks(enable_init_clks,
2023 ARRAY_SIZE(enable_init_clks));
2024
2025 /* 1685 /*
2026 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power 1686 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
2027 * state when turning the ABE clock domain. Workaround this by 1687 * state when turning the ABE clock domain. Workaround this by
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-17 23:15:32 -0500