ARM: OMAP2+: raw read and write endian fix

All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.

Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.

Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index ac82512b9c8c..84cc1482e584 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -160,13 +160,13 @@ static u8 get_gpmc0_type(void)
         if (!fpga_map_addr)
                 return -ENOMEM;
 
-        if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV)))
+        if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV)))
                 /* we dont have an DEBUG FPGA??? */
                 /* Depend on #defines!! default to strata boot return param */
                 goto unmap;
 
         /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
-        cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
+        cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
 
         /* ES2.0 SDP's onwards 4 dip switches are provided for CS */
         if (omap_rev() >= OMAP3430_REV_ES1_0)