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authorArnd Bergmann <arnd@arndb.de>2012-03-02 08:05:00 -0500
committerArnd Bergmann <arnd@arndb.de>2012-03-02 08:05:00 -0500
commit1220547bfd7f7dd97f770a04b533323e5404b8e9 (patch)
treea4231b9570f3302f032a2d757fb3af24a4238d46 /arch/arm/mach-omap1/gpio16xx.c
parenta26d3c4fcd4bb875ae5adc32f27fab7a478bb00d (diff)
parentf86bcc302a8c570dd0f5a50097a6af96a0e717c2 (diff)
Merge branch 'depends/omap/gpio/runtime-pm-cleanup' into next/cleanup
Conflicts: arch/arm/mach-omap1/gpio16xx.c drivers/gpio/gpio-omap.c Merge in the runtime-pm-cleanup branch from the gpio tree into next/cleanup, this resolves a nonobvious merge conflict between the two branches. Both branches move parts of the gpio-omap driver into platform code, this takes the superset of both changes. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-omap1/gpio16xx.c')
-rw-r--r--arch/arm/mach-omap1/gpio16xx.c40
1 files changed, 32 insertions, 8 deletions
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 99cabc498ab5..1fb3b9ad496e 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -24,6 +24,9 @@
24#define OMAP1610_GPIO4_BASE 0xfffbbc00 24#define OMAP1610_GPIO4_BASE 0xfffbbc00
25#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE 25#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
26 26
27/* smart idle, enable wakeup */
28#define SYSCONFIG_WORD 0x14
29
27/* mpu gpio */ 30/* mpu gpio */
28static struct __initdata resource omap16xx_mpu_gpio_resources[] = { 31static struct __initdata resource omap16xx_mpu_gpio_resources[] = {
29 { 32 {
@@ -45,11 +48,12 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
45 .irqstatus = OMAP_MPUIO_GPIO_INT, 48 .irqstatus = OMAP_MPUIO_GPIO_INT,
46 .irqenable = OMAP_MPUIO_GPIO_MASKIT, 49 .irqenable = OMAP_MPUIO_GPIO_MASKIT,
47 .irqenable_inv = true, 50 .irqenable_inv = true,
51 .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE,
48}; 52};
49 53
50static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = { 54static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
51 .virtual_irq_start = IH_MPUIO_BASE, 55 .virtual_irq_start = IH_MPUIO_BASE,
52 .bank_type = METHOD_MPUIO, 56 .is_mpuio = true,
53 .bank_width = 16, 57 .bank_width = 16,
54 .bank_stride = 1, 58 .bank_stride = 1,
55 .regs = &omap16xx_mpuio_regs, 59 .regs = &omap16xx_mpuio_regs,
@@ -89,11 +93,13 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
89 .irqenable = OMAP1610_GPIO_IRQENABLE1, 93 .irqenable = OMAP1610_GPIO_IRQENABLE1,
90 .set_irqenable = OMAP1610_GPIO_SET_IRQENABLE1, 94 .set_irqenable = OMAP1610_GPIO_SET_IRQENABLE1,
91 .clr_irqenable = OMAP1610_GPIO_CLEAR_IRQENABLE1, 95 .clr_irqenable = OMAP1610_GPIO_CLEAR_IRQENABLE1,
96 .wkup_en = OMAP1610_GPIO_WAKEUPENABLE,
97 .edgectrl1 = OMAP1610_GPIO_EDGE_CTRL1,
98 .edgectrl2 = OMAP1610_GPIO_EDGE_CTRL2,
92}; 99};
93 100
94static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = { 101static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
95 .virtual_irq_start = IH_GPIO_BASE, 102 .virtual_irq_start = IH_GPIO_BASE,
96 .bank_type = METHOD_GPIO_1610,
97 .bank_width = 16, 103 .bank_width = 16,
98 .regs = &omap16xx_gpio_regs, 104 .regs = &omap16xx_gpio_regs,
99}; 105};
@@ -123,7 +129,6 @@ static struct __initdata resource omap16xx_gpio2_resources[] = {
123 129
124static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = { 130static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
125 .virtual_irq_start = IH_GPIO_BASE + 16, 131 .virtual_irq_start = IH_GPIO_BASE + 16,
126 .bank_type = METHOD_GPIO_1610,
127 .bank_width = 16, 132 .bank_width = 16,
128 .regs = &omap16xx_gpio_regs, 133 .regs = &omap16xx_gpio_regs,
129}; 134};
@@ -153,7 +158,6 @@ static struct __initdata resource omap16xx_gpio3_resources[] = {
153 158
154static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = { 159static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
155 .virtual_irq_start = IH_GPIO_BASE + 32, 160 .virtual_irq_start = IH_GPIO_BASE + 32,
156 .bank_type = METHOD_GPIO_1610,
157 .bank_width = 16, 161 .bank_width = 16,
158 .regs = &omap16xx_gpio_regs, 162 .regs = &omap16xx_gpio_regs,
159}; 163};
@@ -183,7 +187,6 @@ static struct __initdata resource omap16xx_gpio4_resources[] = {
183 187
184static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = { 188static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
185 .virtual_irq_start = IH_GPIO_BASE + 48, 189 .virtual_irq_start = IH_GPIO_BASE + 48,
186 .bank_type = METHOD_GPIO_1610,
187 .bank_width = 16, 190 .bank_width = 16,
188 .regs = &omap16xx_gpio_regs, 191 .regs = &omap16xx_gpio_regs,
189}; 192};
@@ -214,6 +217,10 @@ static struct __initdata platform_device * omap16xx_gpio_dev[] = {
214static int __init omap16xx_gpio_init(void) 217static int __init omap16xx_gpio_init(void)
215{ 218{
216 int i; 219 int i;
220 void __iomem *base;
221 struct resource *res;
222 struct platform_device *pdev;
223 struct omap_gpio_platform_data *pdata;
217 224
218 if (!cpu_is_omap16xx()) 225 if (!cpu_is_omap16xx())
219 return -EINVAL; 226 return -EINVAL;
@@ -225,10 +232,27 @@ static int __init omap16xx_gpio_init(void)
225 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, 232 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
226 ULPD_CAM_CLK_CTRL); 233 ULPD_CAM_CLK_CTRL);
227 234
228 for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) 235 for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) {
229 platform_device_register(omap16xx_gpio_dev[i]); 236 pdev = omap16xx_gpio_dev[i];
237 pdata = pdev->dev.platform_data;
238
239 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
240 if (unlikely(!res)) {
241 dev_err(&pdev->dev, "Invalid mem resource.\n");
242 return -ENODEV;
243 }
230 244
231 gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev); 245 base = ioremap(res->start, resource_size(res));
246 if (unlikely(!base)) {
247 dev_err(&pdev->dev, "ioremap failed.\n");
248 return -ENOMEM;
249 }
250
251 __raw_writel(SYSCONFIG_WORD, base + OMAP1610_GPIO_SYSCONFIG);
252 iounmap(base);
253
254 platform_device_register(omap16xx_gpio_dev[i]);
255 }
232 256
233 return 0; 257 return 0;
234} 258}