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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-26 15:42:29 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-26 15:42:29 -0400
commit27953437059c64d14086196eb96f43c78caa9db3 (patch)
tree0cfd5fb21262a6db3de0c64462847b4c0c43e9df /arch/arm/mach-mxs
parent2c757fd5d1a92086f225a75a8fac7cab242d11b0 (diff)
parent3c0dec5f58b3c7b3627715126d1bf9b030a076f0 (diff)
Merge tag 'clock' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc clock driver changes from Olof Johansson: "The new clock subsystem was merged in linux-3.4 without any users, this now moves the first three platforms over to it: imx, mxs and spear. The series also contains the changes for the clock subsystem itself, since Mike preferred to have it together with the platforms that require these changes, in order to avoid interdependencies and conflicts." Fix up trivial conflicts in arch/arm/mach-kirkwood/common.c (code removed in one branch, added OF support in another) and drivers/dma/imx-sdma.c (independent changes next to each other). * tag 'clock' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (97 commits) clk: Fix CLK_SET_RATE_GATE flag validation in clk_set_rate(). clk: Provide dummy clk_unregister() SPEAr: Update defconfigs SPEAr: Add SMI NOR partition info in dts files SPEAr: Switch to common clock framework SPEAr: Call clk_prepare() before calling clk_enable SPEAr: clk: Add General Purpose Timer Synthesizer clock SPEAr: clk: Add Fractional Synthesizer clock SPEAr: clk: Add Auxiliary Synthesizer clock SPEAr: clk: Add VCO-PLL Synthesizer clock SPEAr: Add DT bindings for SPEAr's timer ARM i.MX: remove now unused clock files ARM: i.MX6: implement clocks using common clock framework ARM i.MX35: implement clocks using common clock framework ARM i.MX5: implement clocks using common clock framework ARM: Kirkwood: Replace clock gating ARM: Orion: Audio: Add clk/clkdev support ARM: Orion: PCIE: Add support for clk ARM: Orion: XOR: Add support for clk ARM: Orion: CESA: Add support for clk ...
Diffstat (limited to 'arch/arm/mach-mxs')
-rw-r--r--arch/arm/mach-mxs/Makefile5
-rw-r--r--arch/arm/mach-mxs/clock-mx23.c536
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c803
-rw-r--r--arch/arm/mach-mxs/clock.c211
-rw-r--r--arch/arm/mach-mxs/include/mach/clock.h62
-rw-r--r--arch/arm/mach-mxs/include/mach/common.h6
-rw-r--r--arch/arm/mach-mxs/mach-mx28evk.c2
-rw-r--r--arch/arm/mach-mxs/regs-clkctrl-mx23.h331
-rw-r--r--arch/arm/mach-mxs/regs-clkctrl-mx28.h486
-rw-r--r--arch/arm/mach-mxs/system.c16
-rw-r--r--arch/arm/mach-mxs/timer.c11
11 files changed, 13 insertions, 2456 deletions
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 908bf9a567f1..6ce21a26412e 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,12 +1,9 @@
1# Common support 1# Common support
2obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o mm.o 2obj-y := devices.o icoll.o iomux.o system.o timer.o mm.o
3 3
4obj-$(CONFIG_MXS_OCOTP) += ocotp.o 4obj-$(CONFIG_MXS_OCOTP) += ocotp.o
5obj-$(CONFIG_PM) += pm.o 5obj-$(CONFIG_PM) += pm.o
6 6
7obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
8obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
9
10obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o 7obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
11obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o 8obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
12obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o 9obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
deleted file mode 100644
index e3ac52c34019..000000000000
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ /dev/null
@@ -1,536 +0,0 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/mm.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/jiffies.h>
24#include <linux/clkdev.h>
25
26#include <asm/clkdev.h>
27#include <asm/div64.h>
28
29#include <mach/mx23.h>
30#include <mach/common.h>
31#include <mach/clock.h>
32
33#include "regs-clkctrl-mx23.h"
34
35#define CLKCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
36#define DIGCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
37
38#define PARENT_RATE_SHIFT 8
39
40static int _raw_clk_enable(struct clk *clk)
41{
42 u32 reg;
43
44 if (clk->enable_reg) {
45 reg = __raw_readl(clk->enable_reg);
46 reg &= ~(1 << clk->enable_shift);
47 __raw_writel(reg, clk->enable_reg);
48 }
49
50 return 0;
51}
52
53static void _raw_clk_disable(struct clk *clk)
54{
55 u32 reg;
56
57 if (clk->enable_reg) {
58 reg = __raw_readl(clk->enable_reg);
59 reg |= 1 << clk->enable_shift;
60 __raw_writel(reg, clk->enable_reg);
61 }
62}
63
64/*
65 * ref_xtal_clk
66 */
67static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
68{
69 return 24000000;
70}
71
72static struct clk ref_xtal_clk = {
73 .get_rate = ref_xtal_clk_get_rate,
74};
75
76/*
77 * pll_clk
78 */
79static unsigned long pll_clk_get_rate(struct clk *clk)
80{
81 return 480000000;
82}
83
84static int pll_clk_enable(struct clk *clk)
85{
86 __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
87 BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
88 CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET);
89
90 /* Only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer
91 * and is incorrect (excessive). Per definition of the PLLCTRL0
92 * POWER field, waiting at least 10us.
93 */
94 udelay(10);
95
96 return 0;
97}
98
99static void pll_clk_disable(struct clk *clk)
100{
101 __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
102 BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
103 CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR);
104}
105
106static struct clk pll_clk = {
107 .get_rate = pll_clk_get_rate,
108 .enable = pll_clk_enable,
109 .disable = pll_clk_disable,
110 .parent = &ref_xtal_clk,
111};
112
113/*
114 * ref_clk
115 */
116#define _CLK_GET_RATE_REF(name, sr, ss) \
117static unsigned long name##_get_rate(struct clk *clk) \
118{ \
119 unsigned long parent_rate; \
120 u32 reg, div; \
121 \
122 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
123 div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
124 parent_rate = clk_get_rate(clk->parent); \
125 \
126 return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
127 div, PARENT_RATE_SHIFT); \
128}
129
130_CLK_GET_RATE_REF(ref_cpu_clk, FRAC, CPU)
131_CLK_GET_RATE_REF(ref_emi_clk, FRAC, EMI)
132_CLK_GET_RATE_REF(ref_pix_clk, FRAC, PIX)
133_CLK_GET_RATE_REF(ref_io_clk, FRAC, IO)
134
135#define _DEFINE_CLOCK_REF(name, er, es) \
136 static struct clk name = { \
137 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
138 .enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
139 .get_rate = name##_get_rate, \
140 .enable = _raw_clk_enable, \
141 .disable = _raw_clk_disable, \
142 .parent = &pll_clk, \
143 }
144
145_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC, CPU);
146_DEFINE_CLOCK_REF(ref_emi_clk, FRAC, EMI);
147_DEFINE_CLOCK_REF(ref_pix_clk, FRAC, PIX);
148_DEFINE_CLOCK_REF(ref_io_clk, FRAC, IO);
149
150/*
151 * General clocks
152 *
153 * clk_get_rate
154 */
155static unsigned long rtc_clk_get_rate(struct clk *clk)
156{
157 /* ref_xtal_clk is implemented as the only parent */
158 return clk_get_rate(clk->parent) / 768;
159}
160
161static unsigned long clk32k_clk_get_rate(struct clk *clk)
162{
163 return clk->parent->get_rate(clk->parent) / 750;
164}
165
166#define _CLK_GET_RATE(name, rs) \
167static unsigned long name##_get_rate(struct clk *clk) \
168{ \
169 u32 reg, div; \
170 \
171 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
172 \
173 if (clk->parent == &ref_xtal_clk) \
174 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
175 BP_CLKCTRL_##rs##_DIV_XTAL; \
176 else \
177 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
178 BP_CLKCTRL_##rs##_DIV_##rs; \
179 \
180 if (!div) \
181 return -EINVAL; \
182 \
183 return clk_get_rate(clk->parent) / div; \
184}
185
186_CLK_GET_RATE(cpu_clk, CPU)
187_CLK_GET_RATE(emi_clk, EMI)
188
189#define _CLK_GET_RATE1(name, rs) \
190static unsigned long name##_get_rate(struct clk *clk) \
191{ \
192 u32 reg, div; \
193 \
194 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
195 div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
196 \
197 if (!div) \
198 return -EINVAL; \
199 \
200 return clk_get_rate(clk->parent) / div; \
201}
202
203_CLK_GET_RATE1(hbus_clk, HBUS)
204_CLK_GET_RATE1(xbus_clk, XBUS)
205_CLK_GET_RATE1(ssp_clk, SSP)
206_CLK_GET_RATE1(gpmi_clk, GPMI)
207_CLK_GET_RATE1(lcdif_clk, PIX)
208
209#define _CLK_GET_RATE_STUB(name) \
210static unsigned long name##_get_rate(struct clk *clk) \
211{ \
212 return clk_get_rate(clk->parent); \
213}
214
215_CLK_GET_RATE_STUB(uart_clk)
216_CLK_GET_RATE_STUB(audio_clk)
217_CLK_GET_RATE_STUB(pwm_clk)
218
219/*
220 * clk_set_rate
221 */
222static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
223{
224 u32 reg, bm_busy, div_max, d, f, div, frac;
225 unsigned long diff, parent_rate, calc_rate;
226
227 parent_rate = clk_get_rate(clk->parent);
228
229 if (clk->parent == &ref_xtal_clk) {
230 div_max = BM_CLKCTRL_CPU_DIV_XTAL >> BP_CLKCTRL_CPU_DIV_XTAL;
231 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;
232 div = DIV_ROUND_UP(parent_rate, rate);
233 if (div == 0 || div > div_max)
234 return -EINVAL;
235 } else {
236 div_max = BM_CLKCTRL_CPU_DIV_CPU >> BP_CLKCTRL_CPU_DIV_CPU;
237 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;
238 rate >>= PARENT_RATE_SHIFT;
239 parent_rate >>= PARENT_RATE_SHIFT;
240 diff = parent_rate;
241 div = frac = 1;
242 for (d = 1; d <= div_max; d++) {
243 f = parent_rate * 18 / d / rate;
244 if ((parent_rate * 18 / d) % rate)
245 f++;
246 if (f < 18 || f > 35)
247 continue;
248
249 calc_rate = parent_rate * 18 / f / d;
250 if (calc_rate > rate)
251 continue;
252
253 if (rate - calc_rate < diff) {
254 frac = f;
255 div = d;
256 diff = rate - calc_rate;
257 }
258
259 if (diff == 0)
260 break;
261 }
262
263 if (diff == parent_rate)
264 return -EINVAL;
265
266 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
267 reg &= ~BM_CLKCTRL_FRAC_CPUFRAC;
268 reg |= frac;
269 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
270 }
271
272 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
273 reg &= ~BM_CLKCTRL_CPU_DIV_CPU;
274 reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
275 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
276
277 mxs_clkctrl_timeout(HW_CLKCTRL_CPU, bm_busy);
278
279 return 0;
280}
281
282#define _CLK_SET_RATE(name, dr) \
283static int name##_set_rate(struct clk *clk, unsigned long rate) \
284{ \
285 u32 reg, div_max, div; \
286 unsigned long parent_rate; \
287 \
288 parent_rate = clk_get_rate(clk->parent); \
289 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
290 \
291 div = DIV_ROUND_UP(parent_rate, rate); \
292 if (div == 0 || div > div_max) \
293 return -EINVAL; \
294 \
295 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
296 reg &= ~BM_CLKCTRL_##dr##_DIV; \
297 reg |= div << BP_CLKCTRL_##dr##_DIV; \
298 if (reg & (1 << clk->enable_shift)) { \
299 pr_err("%s: clock is gated\n", __func__); \
300 return -EINVAL; \
301 } \
302 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
303 \
304 mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY); \
305 return 0; \
306}
307
308_CLK_SET_RATE(xbus_clk, XBUS)
309_CLK_SET_RATE(ssp_clk, SSP)
310_CLK_SET_RATE(gpmi_clk, GPMI)
311_CLK_SET_RATE(lcdif_clk, PIX)
312
313#define _CLK_SET_RATE_STUB(name) \
314static int name##_set_rate(struct clk *clk, unsigned long rate) \
315{ \
316 return -EINVAL; \
317}
318
319_CLK_SET_RATE_STUB(emi_clk)
320_CLK_SET_RATE_STUB(uart_clk)
321_CLK_SET_RATE_STUB(audio_clk)
322_CLK_SET_RATE_STUB(pwm_clk)
323_CLK_SET_RATE_STUB(clk32k_clk)
324
325/*
326 * clk_set_parent
327 */
328#define _CLK_SET_PARENT(name, bit) \
329static int name##_set_parent(struct clk *clk, struct clk *parent) \
330{ \
331 if (parent != clk->parent) { \
332 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
333 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG); \
334 clk->parent = parent; \
335 } \
336 \
337 return 0; \
338}
339
340_CLK_SET_PARENT(cpu_clk, CPU)
341_CLK_SET_PARENT(emi_clk, EMI)
342_CLK_SET_PARENT(ssp_clk, SSP)
343_CLK_SET_PARENT(gpmi_clk, GPMI)
344_CLK_SET_PARENT(lcdif_clk, PIX)
345
346#define _CLK_SET_PARENT_STUB(name) \
347static int name##_set_parent(struct clk *clk, struct clk *parent) \
348{ \
349 if (parent != clk->parent) \
350 return -EINVAL; \
351 else \
352 return 0; \
353}
354
355_CLK_SET_PARENT_STUB(uart_clk)
356_CLK_SET_PARENT_STUB(audio_clk)
357_CLK_SET_PARENT_STUB(pwm_clk)
358_CLK_SET_PARENT_STUB(clk32k_clk)
359
360/*
361 * clk definition
362 */
363static struct clk cpu_clk = {
364 .get_rate = cpu_clk_get_rate,
365 .set_rate = cpu_clk_set_rate,
366 .set_parent = cpu_clk_set_parent,
367 .parent = &ref_cpu_clk,
368};
369
370static struct clk hbus_clk = {
371 .get_rate = hbus_clk_get_rate,
372 .parent = &cpu_clk,
373};
374
375static struct clk xbus_clk = {
376 .get_rate = xbus_clk_get_rate,
377 .set_rate = xbus_clk_set_rate,
378 .parent = &ref_xtal_clk,
379};
380
381static struct clk rtc_clk = {
382 .get_rate = rtc_clk_get_rate,
383 .parent = &ref_xtal_clk,
384};
385
386/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
387static struct clk usb_clk = {
388 .enable_reg = DIGCTRL_BASE_ADDR,
389 .enable_shift = 2,
390 .enable = _raw_clk_enable,
391 .disable = _raw_clk_disable,
392 .parent = &pll_clk,
393};
394
395#define _DEFINE_CLOCK(name, er, es, p) \
396 static struct clk name = { \
397 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
398 .enable_shift = BP_CLKCTRL_##er##_##es, \
399 .get_rate = name##_get_rate, \
400 .set_rate = name##_set_rate, \
401 .set_parent = name##_set_parent, \
402 .enable = _raw_clk_enable, \
403 .disable = _raw_clk_disable, \
404 .parent = p, \
405 }
406
407_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
408_DEFINE_CLOCK(ssp_clk, SSP, CLKGATE, &ref_xtal_clk);
409_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
410_DEFINE_CLOCK(lcdif_clk, PIX, CLKGATE, &ref_xtal_clk);
411_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
412_DEFINE_CLOCK(audio_clk, XTAL, FILT_CLK24M_GATE, &ref_xtal_clk);
413_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
414_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
415
416#define _REGISTER_CLOCK(d, n, c) \
417 { \
418 .dev_id = d, \
419 .con_id = n, \
420 .clk = &c, \
421 },
422
423static struct clk_lookup lookups[] = {
424 /* for amba bus driver */
425 _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
426 /* for amba-pl011 driver */
427 _REGISTER_CLOCK("duart", NULL, uart_clk)
428 _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
429 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
430 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
431 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
432 _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp_clk)
433 _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp_clk)
434 _REGISTER_CLOCK(NULL, "usb", usb_clk)
435 _REGISTER_CLOCK(NULL, "audio", audio_clk)
436 _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
437 _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
438 _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
439 _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
440 _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
441 _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
442 _REGISTER_CLOCK("imx23-gpmi-nand", NULL, gpmi_clk)
443};
444
445static int clk_misc_init(void)
446{
447 u32 reg;
448 int ret;
449
450 /* Fix up parent per register setting */
451 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
452 cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
453 &ref_xtal_clk : &ref_cpu_clk;
454 emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
455 &ref_xtal_clk : &ref_emi_clk;
456 ssp_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ?
457 &ref_xtal_clk : &ref_io_clk;
458 gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
459 &ref_xtal_clk : &ref_io_clk;
460 lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) ?
461 &ref_xtal_clk : &ref_pix_clk;
462
463 /* Use int div over frac when both are available */
464 __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
465 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
466 __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
467 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
468 __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
469 CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
470
471 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
472 reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
473 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
474
475 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
476 reg &= ~BM_CLKCTRL_SSP_DIV_FRAC_EN;
477 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
478
479 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
480 reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
481 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
482
483 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
484 reg &= ~BM_CLKCTRL_PIX_DIV_FRAC_EN;
485 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
486
487 /*
488 * Set safe hbus clock divider. A divider of 3 ensure that
489 * the Vddd voltage required for the cpu clock is sufficiently
490 * high for the hbus clock.
491 */
492 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
493 reg &= BM_CLKCTRL_HBUS_DIV;
494 reg |= 3 << BP_CLKCTRL_HBUS_DIV;
495 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
496
497 ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_BUSY);
498
499 /* Gate off cpu clock in WFI for power saving */
500 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
501 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
502
503 /*
504 * 480 MHz seems too high to be ssp clock source directly,
505 * so set frac to get a 288 MHz ref_io.
506 */
507 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
508 reg &= ~BM_CLKCTRL_FRAC_IOFRAC;
509 reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC;
510 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
511
512 return ret;
513}
514
515int __init mx23_clocks_init(void)
516{
517 clk_misc_init();
518
519 /*
520 * source ssp clock from ref_io than ref_xtal,
521 * as ref_xtal only provides 24 MHz as maximum.
522 */
523 clk_set_parent(&ssp_clk, &ref_io_clk);
524
525 clk_prepare_enable(&cpu_clk);
526 clk_prepare_enable(&hbus_clk);
527 clk_prepare_enable(&xbus_clk);
528 clk_prepare_enable(&emi_clk);
529 clk_prepare_enable(&uart_clk);
530
531 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
532
533 mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0);
534
535 return 0;
536}
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
deleted file mode 100644
index cea29c99e214..000000000000
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ /dev/null
@@ -1,803 +0,0 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/mm.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/jiffies.h>
24#include <linux/clkdev.h>
25#include <linux/spinlock.h>
26
27#include <asm/clkdev.h>
28#include <asm/div64.h>
29
30#include <mach/mx28.h>
31#include <mach/common.h>
32#include <mach/clock.h>
33#include <mach/digctl.h>
34
35#include "regs-clkctrl-mx28.h"
36
37#define CLKCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
38#define DIGCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
39
40#define PARENT_RATE_SHIFT 8
41
42static struct clk pll2_clk;
43static struct clk cpu_clk;
44static struct clk emi_clk;
45static struct clk saif0_clk;
46static struct clk saif1_clk;
47static struct clk clk32k_clk;
48static DEFINE_SPINLOCK(clkmux_lock);
49
50/*
51 * HW_SAIF_CLKMUX_SEL:
52 * DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
53 * clock pins selected for SAIF1 input clocks.
54 * CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
55 * SAIF0 clock inputs selected for SAIF1 input clocks.
56 * EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
57 * clocks.
58 * EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
59 * clocks.
60 */
61int mxs_saif_clkmux_select(unsigned int clkmux)
62{
63 if (clkmux > 0x3)
64 return -EINVAL;
65
66 spin_lock(&clkmux_lock);
67 __raw_writel(BM_DIGCTL_CTRL_SAIF_CLKMUX,
68 DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_CLR_ADDR);
69 __raw_writel(clkmux << BP_DIGCTL_CTRL_SAIF_CLKMUX,
70 DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_SET_ADDR);
71 spin_unlock(&clkmux_lock);
72
73 return 0;
74}
75
76static int _raw_clk_enable(struct clk *clk)
77{
78 u32 reg;
79
80 if (clk->enable_reg) {
81 reg = __raw_readl(clk->enable_reg);
82 reg &= ~(1 << clk->enable_shift);
83 __raw_writel(reg, clk->enable_reg);
84 }
85
86 return 0;
87}
88
89static void _raw_clk_disable(struct clk *clk)
90{
91 u32 reg;
92
93 if (clk->enable_reg) {
94 reg = __raw_readl(clk->enable_reg);
95 reg |= 1 << clk->enable_shift;
96 __raw_writel(reg, clk->enable_reg);
97 }
98}
99
100/*
101 * ref_xtal_clk
102 */
103static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
104{
105 return 24000000;
106}
107
108static struct clk ref_xtal_clk = {
109 .get_rate = ref_xtal_clk_get_rate,
110};
111
112/*
113 * pll_clk
114 */
115static unsigned long pll0_clk_get_rate(struct clk *clk)
116{
117 return 480000000;
118}
119
120static unsigned long pll1_clk_get_rate(struct clk *clk)
121{
122 return 480000000;
123}
124
125static unsigned long pll2_clk_get_rate(struct clk *clk)
126{
127 return 50000000;
128}
129
130#define _CLK_ENABLE_PLL(name, r, g) \
131static int name##_enable(struct clk *clk) \
132{ \
133 __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
134 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
135 udelay(10); \
136 \
137 if (clk == &pll2_clk) \
138 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
139 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
140 else \
141 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
142 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
143 \
144 return 0; \
145}
146
147_CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
148_CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
149_CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
150
151#define _CLK_DISABLE_PLL(name, r, g) \
152static void name##_disable(struct clk *clk) \
153{ \
154 __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
155 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
156 \
157 if (clk == &pll2_clk) \
158 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
159 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
160 else \
161 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
162 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
163 \
164}
165
166_CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
167_CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
168_CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
169
170#define _DEFINE_CLOCK_PLL(name) \
171 static struct clk name = { \
172 .get_rate = name##_get_rate, \
173 .enable = name##_enable, \
174 .disable = name##_disable, \
175 .parent = &ref_xtal_clk, \
176 }
177
178_DEFINE_CLOCK_PLL(pll0_clk);
179_DEFINE_CLOCK_PLL(pll1_clk);
180_DEFINE_CLOCK_PLL(pll2_clk);
181
182/*
183 * ref_clk
184 */
185#define _CLK_GET_RATE_REF(name, sr, ss) \
186static unsigned long name##_get_rate(struct clk *clk) \
187{ \
188 unsigned long parent_rate; \
189 u32 reg, div; \
190 \
191 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
192 div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
193 parent_rate = clk_get_rate(clk->parent); \
194 \
195 return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
196 div, PARENT_RATE_SHIFT); \
197}
198
199_CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
200_CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
201_CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
202_CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
203_CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
204_CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
205
206#define _DEFINE_CLOCK_REF(name, er, es) \
207 static struct clk name = { \
208 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
209 .enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
210 .get_rate = name##_get_rate, \
211 .enable = _raw_clk_enable, \
212 .disable = _raw_clk_disable, \
213 .parent = &pll0_clk, \
214 }
215
216_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
217_DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
218_DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
219_DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
220_DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
221_DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
222
223/*
224 * General clocks
225 *
226 * clk_get_rate
227 */
228static unsigned long lradc_clk_get_rate(struct clk *clk)
229{
230 return clk_get_rate(clk->parent) / 16;
231}
232
233static unsigned long rtc_clk_get_rate(struct clk *clk)
234{
235 /* ref_xtal_clk is implemented as the only parent */
236 return clk_get_rate(clk->parent) / 768;
237}
238
239static unsigned long clk32k_clk_get_rate(struct clk *clk)
240{
241 return clk->parent->get_rate(clk->parent) / 750;
242}
243
244static unsigned long spdif_clk_get_rate(struct clk *clk)
245{
246 return clk_get_rate(clk->parent) / 4;
247}
248
249#define _CLK_GET_RATE(name, rs) \
250static unsigned long name##_get_rate(struct clk *clk) \
251{ \
252 u32 reg, div; \
253 \
254 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
255 \
256 if (clk->parent == &ref_xtal_clk) \
257 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
258 BP_CLKCTRL_##rs##_DIV_XTAL; \
259 else \
260 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
261 BP_CLKCTRL_##rs##_DIV_##rs; \
262 \
263 if (!div) \
264 return -EINVAL; \
265 \
266 return clk_get_rate(clk->parent) / div; \
267}
268
269_CLK_GET_RATE(cpu_clk, CPU)
270_CLK_GET_RATE(emi_clk, EMI)
271
272#define _CLK_GET_RATE1(name, rs) \
273static unsigned long name##_get_rate(struct clk *clk) \
274{ \
275 u32 reg, div; \
276 \
277 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
278 div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
279 \
280 if (!div) \
281 return -EINVAL; \
282 \
283 if (clk == &saif0_clk || clk == &saif1_clk) \
284 return clk_get_rate(clk->parent) >> 16 * div; \
285 else \
286 return clk_get_rate(clk->parent) / div; \
287}
288
289_CLK_GET_RATE1(hbus_clk, HBUS)
290_CLK_GET_RATE1(xbus_clk, XBUS)
291_CLK_GET_RATE1(ssp0_clk, SSP0)
292_CLK_GET_RATE1(ssp1_clk, SSP1)
293_CLK_GET_RATE1(ssp2_clk, SSP2)
294_CLK_GET_RATE1(ssp3_clk, SSP3)
295_CLK_GET_RATE1(gpmi_clk, GPMI)
296_CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
297_CLK_GET_RATE1(saif0_clk, SAIF0)
298_CLK_GET_RATE1(saif1_clk, SAIF1)
299
300#define _CLK_GET_RATE_STUB(name) \
301static unsigned long name##_get_rate(struct clk *clk) \
302{ \
303 return clk_get_rate(clk->parent); \
304}
305
306_CLK_GET_RATE_STUB(uart_clk)
307_CLK_GET_RATE_STUB(pwm_clk)
308_CLK_GET_RATE_STUB(can0_clk)
309_CLK_GET_RATE_STUB(can1_clk)
310_CLK_GET_RATE_STUB(fec_clk)
311
312/*
313 * clk_set_rate
314 */
315/* fool compiler */
316#define BM_CLKCTRL_CPU_DIV 0
317#define BP_CLKCTRL_CPU_DIV 0
318#define BM_CLKCTRL_CPU_BUSY 0
319
320#define _CLK_SET_RATE(name, dr, fr, fs) \
321static int name##_set_rate(struct clk *clk, unsigned long rate) \
322{ \
323 u32 reg, bm_busy, div_max, d, f, div, frac; \
324 unsigned long diff, parent_rate, calc_rate; \
325 \
326 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
327 bm_busy = BM_CLKCTRL_##dr##_BUSY; \
328 \
329 if (clk->parent == &ref_xtal_clk) { \
330 parent_rate = clk_get_rate(clk->parent); \
331 div = DIV_ROUND_UP(parent_rate, rate); \
332 if (clk == &cpu_clk) { \
333 div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \
334 BP_CLKCTRL_CPU_DIV_XTAL; \
335 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL; \
336 } \
337 if (div == 0 || div > div_max) \
338 return -EINVAL; \
339 } else { \
340 /* \
341 * hack alert: this block modifies clk->parent, too, \
342 * so the base to use it the grand parent. \
343 */ \
344 parent_rate = clk_get_rate(clk->parent->parent); \
345 rate >>= PARENT_RATE_SHIFT; \
346 parent_rate >>= PARENT_RATE_SHIFT; \
347 diff = parent_rate; \
348 div = frac = 1; \
349 if (clk == &cpu_clk) { \
350 div_max = BM_CLKCTRL_CPU_DIV_CPU >> \
351 BP_CLKCTRL_CPU_DIV_CPU; \
352 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU; \
353 } \
354 for (d = 1; d <= div_max; d++) { \
355 f = parent_rate * 18 / d / rate; \
356 if ((parent_rate * 18 / d) % rate) \
357 f++; \
358 if (f < 18 || f > 35) \
359 continue; \
360 \
361 calc_rate = parent_rate * 18 / f / d; \
362 if (calc_rate > rate) \
363 continue; \
364 \
365 if (rate - calc_rate < diff) { \
366 frac = f; \
367 div = d; \
368 diff = rate - calc_rate; \
369 } \
370 \
371 if (diff == 0) \
372 break; \
373 } \
374 \
375 if (diff == parent_rate) \
376 return -EINVAL; \
377 \
378 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
379 reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \
380 reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC; \
381 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
382 } \
383 \
384 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
385 if (clk == &cpu_clk) { \
386 reg &= ~BM_CLKCTRL_CPU_DIV_CPU; \
387 reg |= div << BP_CLKCTRL_CPU_DIV_CPU; \
388 } else { \
389 reg &= ~BM_CLKCTRL_##dr##_DIV; \
390 reg |= div << BP_CLKCTRL_##dr##_DIV; \
391 if (reg & (1 << clk->enable_shift)) { \
392 pr_err("%s: clock is gated\n", __func__); \
393 return -EINVAL; \
394 } \
395 } \
396 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
397 \
398 return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, bm_busy); \
399}
400
401_CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
402_CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
403_CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
404_CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
405_CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
406_CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
407_CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
408
409#define _CLK_SET_RATE1(name, dr) \
410static int name##_set_rate(struct clk *clk, unsigned long rate) \
411{ \
412 u32 reg, div_max, div; \
413 unsigned long parent_rate; \
414 \
415 parent_rate = clk_get_rate(clk->parent); \
416 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
417 \
418 div = DIV_ROUND_UP(parent_rate, rate); \
419 if (div == 0 || div > div_max) \
420 return -EINVAL; \
421 \
422 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
423 reg &= ~BM_CLKCTRL_##dr##_DIV; \
424 reg |= div << BP_CLKCTRL_##dr##_DIV; \
425 if (reg & (1 << clk->enable_shift)) { \
426 pr_err("%s: clock is gated\n", __func__); \
427 return -EINVAL; \
428 } \
429 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
430 \
431 return mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY);\
432}
433
434_CLK_SET_RATE1(xbus_clk, XBUS)
435
436/* saif clock uses 16 bits frac div */
437#define _CLK_SET_RATE_SAIF(name, rs) \
438static int name##_set_rate(struct clk *clk, unsigned long rate) \
439{ \
440 u16 div; \
441 u32 reg; \
442 u64 lrate; \
443 unsigned long parent_rate; \
444 \
445 parent_rate = clk_get_rate(clk->parent); \
446 if (rate > parent_rate) \
447 return -EINVAL; \
448 \
449 lrate = (u64)rate << 16; \
450 do_div(lrate, parent_rate); \
451 div = (u16)lrate; \
452 \
453 if (!div) \
454 return -EINVAL; \
455 \
456 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
457 reg &= ~BM_CLKCTRL_##rs##_DIV; \
458 reg |= div << BP_CLKCTRL_##rs##_DIV; \
459 if (reg & (1 << clk->enable_shift)) { \
460 pr_err("%s: clock is gated\n", __func__); \
461 return -EINVAL; \
462 } \
463 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
464 \
465 return mxs_clkctrl_timeout(HW_CLKCTRL_##rs, BM_CLKCTRL_##rs##_BUSY);\
466}
467
468_CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
469_CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
470
471#define _CLK_SET_RATE_STUB(name) \
472static int name##_set_rate(struct clk *clk, unsigned long rate) \
473{ \
474 return -EINVAL; \
475}
476
477_CLK_SET_RATE_STUB(emi_clk)
478_CLK_SET_RATE_STUB(uart_clk)
479_CLK_SET_RATE_STUB(pwm_clk)
480_CLK_SET_RATE_STUB(spdif_clk)
481_CLK_SET_RATE_STUB(clk32k_clk)
482_CLK_SET_RATE_STUB(can0_clk)
483_CLK_SET_RATE_STUB(can1_clk)
484_CLK_SET_RATE_STUB(fec_clk)
485
486/*
487 * clk_set_parent
488 */
489#define _CLK_SET_PARENT(name, bit) \
490static int name##_set_parent(struct clk *clk, struct clk *parent) \
491{ \
492 if (parent != clk->parent) { \
493 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
494 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG); \
495 clk->parent = parent; \
496 } \
497 \
498 return 0; \
499}
500
501_CLK_SET_PARENT(cpu_clk, CPU)
502_CLK_SET_PARENT(emi_clk, EMI)
503_CLK_SET_PARENT(ssp0_clk, SSP0)
504_CLK_SET_PARENT(ssp1_clk, SSP1)
505_CLK_SET_PARENT(ssp2_clk, SSP2)
506_CLK_SET_PARENT(ssp3_clk, SSP3)
507_CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
508_CLK_SET_PARENT(gpmi_clk, GPMI)
509_CLK_SET_PARENT(saif0_clk, SAIF0)
510_CLK_SET_PARENT(saif1_clk, SAIF1)
511
512#define _CLK_SET_PARENT_STUB(name) \
513static int name##_set_parent(struct clk *clk, struct clk *parent) \
514{ \
515 if (parent != clk->parent) \
516 return -EINVAL; \
517 else \
518 return 0; \
519}
520
521_CLK_SET_PARENT_STUB(pwm_clk)
522_CLK_SET_PARENT_STUB(uart_clk)
523_CLK_SET_PARENT_STUB(clk32k_clk)
524_CLK_SET_PARENT_STUB(spdif_clk)
525_CLK_SET_PARENT_STUB(fec_clk)
526_CLK_SET_PARENT_STUB(can0_clk)
527_CLK_SET_PARENT_STUB(can1_clk)
528
529/*
530 * clk definition
531 */
532static struct clk cpu_clk = {
533 .get_rate = cpu_clk_get_rate,
534 .set_rate = cpu_clk_set_rate,
535 .set_parent = cpu_clk_set_parent,
536 .parent = &ref_cpu_clk,
537};
538
539static struct clk hbus_clk = {
540 .get_rate = hbus_clk_get_rate,
541 .parent = &cpu_clk,
542};
543
544static struct clk xbus_clk = {
545 .get_rate = xbus_clk_get_rate,
546 .set_rate = xbus_clk_set_rate,
547 .parent = &ref_xtal_clk,
548};
549
550static struct clk lradc_clk = {
551 .get_rate = lradc_clk_get_rate,
552 .parent = &clk32k_clk,
553};
554
555static struct clk rtc_clk = {
556 .get_rate = rtc_clk_get_rate,
557 .parent = &ref_xtal_clk,
558};
559
560/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
561static struct clk usb0_clk = {
562 .enable_reg = DIGCTRL_BASE_ADDR,
563 .enable_shift = 2,
564 .enable = _raw_clk_enable,
565 .disable = _raw_clk_disable,
566 .parent = &pll0_clk,
567};
568
569static struct clk usb1_clk = {
570 .enable_reg = DIGCTRL_BASE_ADDR,
571 .enable_shift = 16,
572 .enable = _raw_clk_enable,
573 .disable = _raw_clk_disable,
574 .parent = &pll1_clk,
575};
576
577#define _DEFINE_CLOCK(name, er, es, p) \
578 static struct clk name = { \
579 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
580 .enable_shift = BP_CLKCTRL_##er##_##es, \
581 .get_rate = name##_get_rate, \
582 .set_rate = name##_set_rate, \
583 .set_parent = name##_set_parent, \
584 .enable = _raw_clk_enable, \
585 .disable = _raw_clk_disable, \
586 .parent = p, \
587 }
588
589_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
590_DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
591_DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
592_DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
593_DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
594_DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
595_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
596_DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
597_DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
598_DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
599_DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
600_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
601_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
602_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
603_DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
604_DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
605
606#define _REGISTER_CLOCK(d, n, c) \
607 { \
608 .dev_id = d, \
609 .con_id = n, \
610 .clk = &c, \
611 },
612
613static struct clk_lookup lookups[] = {
614 /* for amba bus driver */
615 _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
616 /* for amba-pl011 driver */
617 _REGISTER_CLOCK("duart", NULL, uart_clk)
618 _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
619 _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
620 _REGISTER_CLOCK("imx28-gpmi-nand", NULL, gpmi_clk)
621 _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
622 _REGISTER_CLOCK("mxs-auart.1", NULL, uart_clk)
623 _REGISTER_CLOCK("mxs-auart.2", NULL, uart_clk)
624 _REGISTER_CLOCK("mxs-auart.3", NULL, uart_clk)
625 _REGISTER_CLOCK("mxs-auart.4", NULL, uart_clk)
626 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
627 _REGISTER_CLOCK("pll2", NULL, pll2_clk)
628 _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
629 _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
630 _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp0_clk)
631 _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp1_clk)
632 _REGISTER_CLOCK("mxs-mmc.2", NULL, ssp2_clk)
633 _REGISTER_CLOCK("mxs-mmc.3", NULL, ssp3_clk)
634 _REGISTER_CLOCK("flexcan.0", NULL, can0_clk)
635 _REGISTER_CLOCK("flexcan.1", NULL, can1_clk)
636 _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
637 _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
638 _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
639 _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
640 _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
641 _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
642 _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
643 _REGISTER_CLOCK("mxs-pwm.5", NULL, pwm_clk)
644 _REGISTER_CLOCK("mxs-pwm.6", NULL, pwm_clk)
645 _REGISTER_CLOCK("mxs-pwm.7", NULL, pwm_clk)
646 _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
647 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
648 _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
649 _REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
650 _REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
651};
652
653static int clk_misc_init(void)
654{
655 u32 reg;
656 int ret;
657
658 /* Fix up parent per register setting */
659 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
660 cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
661 &ref_xtal_clk : &ref_cpu_clk;
662 emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
663 &ref_xtal_clk : &ref_emi_clk;
664 ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
665 &ref_xtal_clk : &ref_io0_clk;
666 ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
667 &ref_xtal_clk : &ref_io0_clk;
668 ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
669 &ref_xtal_clk : &ref_io1_clk;
670 ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
671 &ref_xtal_clk : &ref_io1_clk;
672 lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
673 &ref_xtal_clk : &ref_pix_clk;
674 gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
675 &ref_xtal_clk : &ref_gpmi_clk;
676 saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
677 &ref_xtal_clk : &pll0_clk;
678 saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
679 &ref_xtal_clk : &pll0_clk;
680
681 /* Use int div over frac when both are available */
682 __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
683 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
684 __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
685 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
686 __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
687 CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
688
689 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
690 reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
691 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
692
693 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
694 reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
695 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
696
697 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
698 reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
699 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
700
701 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
702 reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
703 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
704
705 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
706 reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
707 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
708
709 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
710 reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
711 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
712
713 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
714 reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
715 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
716
717 /* SAIF has to use frac div for functional operation */
718 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
719 reg |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
720 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
721
722 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
723 reg |= BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
724 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
725
726 /*
727 * Set safe hbus clock divider. A divider of 3 ensure that
728 * the Vddd voltage required for the cpu clock is sufficiently
729 * high for the hbus clock.
730 */
731 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
732 reg &= BM_CLKCTRL_HBUS_DIV;
733 reg |= 3 << BP_CLKCTRL_HBUS_DIV;
734 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
735
736 ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_ASM_BUSY);
737
738 /* Gate off cpu clock in WFI for power saving */
739 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
740 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
741
742 /*
743 * Extra fec clock setting
744 * The DENX M28 uses an external clock source
745 * and the clock output must not be enabled
746 */
747 if (!machine_is_m28evk()) {
748 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
749 reg &= ~BM_CLKCTRL_ENET_SLEEP;
750 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
751 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
752 }
753
754 /*
755 * 480 MHz seems too high to be ssp clock source directly,
756 * so set frac0 to get a 288 MHz ref_io0.
757 */
758 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
759 reg &= ~BM_CLKCTRL_FRAC0_IO0FRAC;
760 reg |= 30 << BP_CLKCTRL_FRAC0_IO0FRAC;
761 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
762
763 return ret;
764}
765
766int __init mx28_clocks_init(void)
767{
768 clk_misc_init();
769
770 /*
771 * source ssp clock from ref_io0 than ref_xtal,
772 * as ref_xtal only provides 24 MHz as maximum.
773 */
774 clk_set_parent(&ssp0_clk, &ref_io0_clk);
775 clk_set_parent(&ssp1_clk, &ref_io0_clk);
776 clk_set_parent(&ssp2_clk, &ref_io1_clk);
777 clk_set_parent(&ssp3_clk, &ref_io1_clk);
778
779 clk_prepare_enable(&cpu_clk);
780 clk_prepare_enable(&hbus_clk);
781 clk_prepare_enable(&xbus_clk);
782 clk_prepare_enable(&emi_clk);
783 clk_prepare_enable(&uart_clk);
784
785 clk_set_parent(&lcdif_clk, &ref_pix_clk);
786 clk_set_parent(&saif0_clk, &pll0_clk);
787 clk_set_parent(&saif1_clk, &pll0_clk);
788
789 /*
790 * Set an initial clock rate for the saif internal logic to work
791 * properly. This is important when working in EXTMASTER mode that
792 * uses the other saif's BITCLK&LRCLK but it still needs a basic
793 * clock which should be fast enough for the internal logic.
794 */
795 clk_set_rate(&saif0_clk, 24000000);
796 clk_set_rate(&saif1_clk, 24000000);
797
798 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
799
800 mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
801
802 return 0;
803}
diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c
deleted file mode 100644
index 97a6f4acc6cc..000000000000
--- a/arch/arm/mach-mxs/clock.c
+++ /dev/null
@@ -1,211 +0,0 @@
1/*
2 * Based on arch/arm/plat-omap/clock.c
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
7 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
8 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25/* #define DEBUG */
26
27#include <linux/clk.h>
28#include <linux/err.h>
29#include <linux/errno.h>
30#include <linux/init.h>
31#include <linux/io.h>
32#include <linux/kernel.h>
33#include <linux/list.h>
34#include <linux/module.h>
35#include <linux/mutex.h>
36#include <linux/platform_device.h>
37#include <linux/proc_fs.h>
38#include <linux/semaphore.h>
39#include <linux/string.h>
40
41#include <mach/clock.h>
42
43static LIST_HEAD(clocks);
44static DEFINE_MUTEX(clocks_mutex);
45
46/*-------------------------------------------------------------------------
47 * Standard clock functions defined in include/linux/clk.h
48 *-------------------------------------------------------------------------*/
49
50static void __clk_disable(struct clk *clk)
51{
52 if (clk == NULL || IS_ERR(clk))
53 return;
54 WARN_ON(!clk->usecount);
55
56 if (!(--clk->usecount)) {
57 if (clk->disable)
58 clk->disable(clk);
59 __clk_disable(clk->parent);
60 }
61}
62
63static int __clk_enable(struct clk *clk)
64{
65 if (clk == NULL || IS_ERR(clk))
66 return -EINVAL;
67
68 if (clk->usecount++ == 0) {
69 __clk_enable(clk->parent);
70
71 if (clk->enable)
72 clk->enable(clk);
73 }
74 return 0;
75}
76
77/*
78 * The clk_enable/clk_disable could be called by drivers in atomic context,
79 * so they should not really hold mutex. Instead, clk_prepare/clk_unprepare
80 * can hold a mutex, as the pair will only be called in non-atomic context.
81 * Before migrating to common clk framework, we can have __clk_enable and
82 * __clk_disable called in clk_prepare/clk_unprepare with mutex held and
83 * leave clk_enable/clk_disable as the dummy functions.
84 */
85int clk_prepare(struct clk *clk)
86{
87 int ret = 0;
88
89 if (clk == NULL || IS_ERR(clk))
90 return -EINVAL;
91
92 mutex_lock(&clocks_mutex);
93 ret = __clk_enable(clk);
94 mutex_unlock(&clocks_mutex);
95
96 return ret;
97}
98EXPORT_SYMBOL(clk_prepare);
99
100void clk_unprepare(struct clk *clk)
101{
102 if (clk == NULL || IS_ERR(clk))
103 return;
104
105 mutex_lock(&clocks_mutex);
106 __clk_disable(clk);
107 mutex_unlock(&clocks_mutex);
108}
109EXPORT_SYMBOL(clk_unprepare);
110
111int clk_enable(struct clk *clk)
112{
113 return 0;
114}
115EXPORT_SYMBOL(clk_enable);
116
117void clk_disable(struct clk *clk)
118{
119 /* nothing to do */
120}
121EXPORT_SYMBOL(clk_disable);
122
123/* Retrieve the *current* clock rate. If the clock itself
124 * does not provide a special calculation routine, ask
125 * its parent and so on, until one is able to return
126 * a valid clock rate
127 */
128unsigned long clk_get_rate(struct clk *clk)
129{
130 if (clk == NULL || IS_ERR(clk))
131 return 0UL;
132
133 if (clk->get_rate)
134 return clk->get_rate(clk);
135
136 return clk_get_rate(clk->parent);
137}
138EXPORT_SYMBOL(clk_get_rate);
139
140/* Round the requested clock rate to the nearest supported
141 * rate that is less than or equal to the requested rate.
142 * This is dependent on the clock's current parent.
143 */
144long clk_round_rate(struct clk *clk, unsigned long rate)
145{
146 if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
147 return 0;
148
149 return clk->round_rate(clk, rate);
150}
151EXPORT_SYMBOL(clk_round_rate);
152
153/* Set the clock to the requested clock rate. The rate must
154 * match a supported rate exactly based on what clk_round_rate returns
155 */
156int clk_set_rate(struct clk *clk, unsigned long rate)
157{
158 int ret = -EINVAL;
159
160 if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
161 return ret;
162
163 mutex_lock(&clocks_mutex);
164 ret = clk->set_rate(clk, rate);
165 mutex_unlock(&clocks_mutex);
166
167 return ret;
168}
169EXPORT_SYMBOL(clk_set_rate);
170
171/* Set the clock's parent to another clock source */
172int clk_set_parent(struct clk *clk, struct clk *parent)
173{
174 int ret = -EINVAL;
175 struct clk *old;
176
177 if (clk == NULL || IS_ERR(clk) || parent == NULL ||
178 IS_ERR(parent) || clk->set_parent == NULL)
179 return ret;
180
181 if (clk->usecount)
182 clk_prepare_enable(parent);
183
184 mutex_lock(&clocks_mutex);
185 ret = clk->set_parent(clk, parent);
186 if (ret == 0) {
187 old = clk->parent;
188 clk->parent = parent;
189 } else {
190 old = parent;
191 }
192 mutex_unlock(&clocks_mutex);
193
194 if (clk->usecount)
195 clk_disable(old);
196
197 return ret;
198}
199EXPORT_SYMBOL(clk_set_parent);
200
201/* Retrieve the clock's parent clock source */
202struct clk *clk_get_parent(struct clk *clk)
203{
204 struct clk *ret = NULL;
205
206 if (clk == NULL || IS_ERR(clk))
207 return ret;
208
209 return clk->parent;
210}
211EXPORT_SYMBOL(clk_get_parent);
diff --git a/arch/arm/mach-mxs/include/mach/clock.h b/arch/arm/mach-mxs/include/mach/clock.h
deleted file mode 100644
index 592c9ab5d760..000000000000
--- a/arch/arm/mach-mxs/include/mach/clock.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __MACH_MXS_CLOCK_H__
21#define __MACH_MXS_CLOCK_H__
22
23#ifndef __ASSEMBLY__
24#include <linux/list.h>
25
26struct module;
27
28struct clk {
29 int id;
30 /* Source clock this clk depends on */
31 struct clk *parent;
32 /* Reference count of clock enable/disable */
33 __s8 usecount;
34 /* Register bit position for clock's enable/disable control. */
35 u8 enable_shift;
36 /* Register address for clock's enable/disable control. */
37 void __iomem *enable_reg;
38 u32 flags;
39 /* get the current clock rate (always a fresh value) */
40 unsigned long (*get_rate) (struct clk *);
41 /* Function ptr to set the clock to a new rate. The rate must match a
42 supported rate returned from round_rate. Leave blank if clock is not
43 programmable */
44 int (*set_rate) (struct clk *, unsigned long);
45 /* Function ptr to round the requested clock rate to the nearest
46 supported rate that is less than or equal to the requested rate. */
47 unsigned long (*round_rate) (struct clk *, unsigned long);
48 /* Function ptr to enable the clock. Leave blank if clock can not
49 be gated. */
50 int (*enable) (struct clk *);
51 /* Function ptr to disable the clock. Leave blank if clock can not
52 be gated. */
53 void (*disable) (struct clk *);
54 /* Function ptr to set the parent clock of the clock. */
55 int (*set_parent) (struct clk *, struct clk *);
56};
57
58int clk_register(struct clk *clk);
59void clk_unregister(struct clk *clk);
60
61#endif /* __ASSEMBLY__ */
62#endif /* __MACH_MXS_CLOCK_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index 8d88399b73ef..84af61cf6a62 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -11,11 +11,9 @@
11#ifndef __MACH_MXS_COMMON_H__ 11#ifndef __MACH_MXS_COMMON_H__
12#define __MACH_MXS_COMMON_H__ 12#define __MACH_MXS_COMMON_H__
13 13
14struct clk;
15
16extern const u32 *mxs_get_ocotp(void); 14extern const u32 *mxs_get_ocotp(void);
17extern int mxs_reset_block(void __iomem *); 15extern int mxs_reset_block(void __iomem *);
18extern void mxs_timer_init(struct clk *, int); 16extern void mxs_timer_init(int);
19extern void mxs_restart(char, const char *); 17extern void mxs_restart(char, const char *);
20extern int mxs_saif_clkmux_select(unsigned int clkmux); 18extern int mxs_saif_clkmux_select(unsigned int clkmux);
21 19
@@ -33,6 +31,4 @@ extern void mx28_init_irq(void);
33 31
34extern void icoll_init_irq(void); 32extern void icoll_init_irq(void);
35 33
36extern int mxs_clkctrl_timeout(unsigned int reg_offset, unsigned int mask);
37
38#endif /* __MACH_MXS_COMMON_H__ */ 34#endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index da4610ebe9e6..dafd48e86c8c 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -226,7 +226,7 @@ static void __init mx28evk_fec_reset(void)
226 struct clk *clk; 226 struct clk *clk;
227 227
228 /* Enable fec phy clock */ 228 /* Enable fec phy clock */
229 clk = clk_get_sys("pll2", NULL); 229 clk = clk_get_sys("enet_out", NULL);
230 if (!IS_ERR(clk)) 230 if (!IS_ERR(clk))
231 clk_prepare_enable(clk); 231 clk_prepare_enable(clk);
232 232
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
deleted file mode 100644
index 0ea5c9d0e2b2..000000000000
--- a/arch/arm/mach-mxs/regs-clkctrl-mx23.h
+++ /dev/null
@@ -1,331 +0,0 @@
1/*
2 * Freescale CLKCTRL Register Definitions
3 *
4 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
5 * Copyright 2008-2010 Freescale Semiconductor, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * This file is created by xml file. Don't Edit it.
22 *
23 * Xml Revision: 1.48
24 * Template revision: 26195
25 */
26
27#ifndef __REGS_CLKCTRL_MX23_H__
28#define __REGS_CLKCTRL_MX23_H__
29
30
31#define HW_CLKCTRL_PLLCTRL0 (0x00000000)
32#define HW_CLKCTRL_PLLCTRL0_SET (0x00000004)
33#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
34#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
35
36#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28
37#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000
38#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \
39 (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL)
40#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0
41#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1
42#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2
43#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
44#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24
45#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000
46#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \
47 (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL)
48#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0
49#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1
50#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2
51#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
52#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20
53#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000
54#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \
55 (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL)
56#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0
57#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1
58#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2
59#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
60#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
61#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000
62
63#define HW_CLKCTRL_PLLCTRL1 (0x00000010)
64
65#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000
66#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
67#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
68#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF
69#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \
70 (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT)
71
72#define HW_CLKCTRL_CPU (0x00000020)
73#define HW_CLKCTRL_CPU_SET (0x00000024)
74#define HW_CLKCTRL_CPU_CLR (0x00000028)
75#define HW_CLKCTRL_CPU_TOG (0x0000002c)
76
77#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
78#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
79#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
80#define BP_CLKCTRL_CPU_DIV_XTAL 16
81#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
82#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
83 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
84#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
85#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
86#define BP_CLKCTRL_CPU_DIV_CPU 0
87#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
88#define BF_CLKCTRL_CPU_DIV_CPU(v) \
89 (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
90
91#define HW_CLKCTRL_HBUS (0x00000030)
92#define HW_CLKCTRL_HBUS_SET (0x00000034)
93#define HW_CLKCTRL_HBUS_CLR (0x00000038)
94#define HW_CLKCTRL_HBUS_TOG (0x0000003c)
95
96#define BM_CLKCTRL_HBUS_BUSY 0x20000000
97#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000
98#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000
99#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
100#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
101#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
102#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
103#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
104#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
105#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000
106#define BP_CLKCTRL_HBUS_SLOW_DIV 16
107#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
108#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
109 (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
110#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
111#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
112#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
113#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
114#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
115#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
116#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
117#define BP_CLKCTRL_HBUS_DIV 0
118#define BM_CLKCTRL_HBUS_DIV 0x0000001F
119#define BF_CLKCTRL_HBUS_DIV(v) \
120 (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
121
122#define HW_CLKCTRL_XBUS (0x00000040)
123
124#define BM_CLKCTRL_XBUS_BUSY 0x80000000
125#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
126#define BP_CLKCTRL_XBUS_DIV 0
127#define BM_CLKCTRL_XBUS_DIV 0x000003FF
128#define BF_CLKCTRL_XBUS_DIV(v) \
129 (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
130
131#define HW_CLKCTRL_XTAL (0x00000050)
132#define HW_CLKCTRL_XTAL_SET (0x00000054)
133#define HW_CLKCTRL_XTAL_CLR (0x00000058)
134#define HW_CLKCTRL_XTAL_TOG (0x0000005c)
135
136#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
137#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
138#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30
139#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000
140#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
141#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
142#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
143#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000
144#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
145#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
146#define BP_CLKCTRL_XTAL_DIV_UART 0
147#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
148#define BF_CLKCTRL_XTAL_DIV_UART(v) \
149 (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
150
151#define HW_CLKCTRL_PIX (0x00000060)
152
153#define BP_CLKCTRL_PIX_CLKGATE 31
154#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
155#define BM_CLKCTRL_PIX_BUSY 0x20000000
156#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000
157#define BP_CLKCTRL_PIX_DIV 0
158#define BM_CLKCTRL_PIX_DIV 0x00000FFF
159#define BF_CLKCTRL_PIX_DIV(v) \
160 (((v) << 0) & BM_CLKCTRL_PIX_DIV)
161
162#define HW_CLKCTRL_SSP (0x00000070)
163
164#define BP_CLKCTRL_SSP_CLKGATE 31
165#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
166#define BM_CLKCTRL_SSP_BUSY 0x20000000
167#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200
168#define BP_CLKCTRL_SSP_DIV 0
169#define BM_CLKCTRL_SSP_DIV 0x000001FF
170#define BF_CLKCTRL_SSP_DIV(v) \
171 (((v) << 0) & BM_CLKCTRL_SSP_DIV)
172
173#define HW_CLKCTRL_GPMI (0x00000080)
174
175#define BP_CLKCTRL_GPMI_CLKGATE 31
176#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
177#define BM_CLKCTRL_GPMI_BUSY 0x20000000
178#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
179#define BP_CLKCTRL_GPMI_DIV 0
180#define BM_CLKCTRL_GPMI_DIV 0x000003FF
181#define BF_CLKCTRL_GPMI_DIV(v) \
182 (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
183
184#define HW_CLKCTRL_SPDIF (0x00000090)
185
186#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
187
188#define HW_CLKCTRL_EMI (0x000000a0)
189
190#define BP_CLKCTRL_EMI_CLKGATE 31
191#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
192#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
193#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
194#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
195#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
196#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
197#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
198#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
199#define BP_CLKCTRL_EMI_DIV_XTAL 8
200#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
201#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
202 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
203#define BP_CLKCTRL_EMI_DIV_EMI 0
204#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
205#define BF_CLKCTRL_EMI_DIV_EMI(v) \
206 (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
207
208#define HW_CLKCTRL_IR (0x000000b0)
209
210#define BM_CLKCTRL_IR_CLKGATE 0x80000000
211#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
212#define BM_CLKCTRL_IR_IR_BUSY 0x10000000
213#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
214#define BP_CLKCTRL_IR_IROV_DIV 16
215#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000
216#define BF_CLKCTRL_IR_IROV_DIV(v) \
217 (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
218#define BP_CLKCTRL_IR_IR_DIV 0
219#define BM_CLKCTRL_IR_IR_DIV 0x000003FF
220#define BF_CLKCTRL_IR_IR_DIV(v) \
221 (((v) << 0) & BM_CLKCTRL_IR_IR_DIV)
222
223#define HW_CLKCTRL_SAIF (0x000000c0)
224
225#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
226#define BM_CLKCTRL_SAIF_BUSY 0x20000000
227#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000
228#define BP_CLKCTRL_SAIF_DIV 0
229#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF
230#define BF_CLKCTRL_SAIF_DIV(v) \
231 (((v) << 0) & BM_CLKCTRL_SAIF_DIV)
232
233#define HW_CLKCTRL_TV (0x000000d0)
234
235#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000
236#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000
237
238#define HW_CLKCTRL_ETM (0x000000e0)
239
240#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
241#define BM_CLKCTRL_ETM_BUSY 0x20000000
242#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040
243#define BP_CLKCTRL_ETM_DIV 0
244#define BM_CLKCTRL_ETM_DIV 0x0000003F
245#define BF_CLKCTRL_ETM_DIV(v) \
246 (((v) << 0) & BM_CLKCTRL_ETM_DIV)
247
248#define HW_CLKCTRL_FRAC (0x000000f0)
249#define HW_CLKCTRL_FRAC_SET (0x000000f4)
250#define HW_CLKCTRL_FRAC_CLR (0x000000f8)
251#define HW_CLKCTRL_FRAC_TOG (0x000000fc)
252
253#define BP_CLKCTRL_FRAC_CLKGATEIO 31
254#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000
255#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000
256#define BP_CLKCTRL_FRAC_IOFRAC 24
257#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000
258#define BF_CLKCTRL_FRAC_IOFRAC(v) \
259 (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC)
260#define BP_CLKCTRL_FRAC_CLKGATEPIX 23
261#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
262#define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000
263#define BP_CLKCTRL_FRAC_PIXFRAC 16
264#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
265#define BF_CLKCTRL_FRAC_PIXFRAC(v) \
266 (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC)
267#define BP_CLKCTRL_FRAC_CLKGATEEMI 15
268#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000
269#define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000
270#define BP_CLKCTRL_FRAC_EMIFRAC 8
271#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
272#define BF_CLKCTRL_FRAC_EMIFRAC(v) \
273 (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC)
274#define BP_CLKCTRL_FRAC_CLKGATECPU 7
275#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080
276#define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040
277#define BP_CLKCTRL_FRAC_CPUFRAC 0
278#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
279#define BF_CLKCTRL_FRAC_CPUFRAC(v) \
280 (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC)
281
282#define HW_CLKCTRL_FRAC1 (0x00000100)
283#define HW_CLKCTRL_FRAC1_SET (0x00000104)
284#define HW_CLKCTRL_FRAC1_CLR (0x00000108)
285#define HW_CLKCTRL_FRAC1_TOG (0x0000010c)
286
287#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000
288#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000
289
290#define HW_CLKCTRL_CLKSEQ (0x00000110)
291#define HW_CLKCTRL_CLKSEQ_SET (0x00000114)
292#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118)
293#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c)
294
295#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
296#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
297#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
298#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
299#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
300#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
301#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
302#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
303
304#define HW_CLKCTRL_RESET (0x00000120)
305
306#define BM_CLKCTRL_RESET_CHIP 0x00000002
307#define BM_CLKCTRL_RESET_DIG 0x00000001
308
309#define HW_CLKCTRL_STATUS (0x00000130)
310
311#define BP_CLKCTRL_STATUS_CPU_LIMIT 30
312#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
313#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
314 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
315
316#define HW_CLKCTRL_VERSION (0x00000140)
317
318#define BP_CLKCTRL_VERSION_MAJOR 24
319#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
320#define BF_CLKCTRL_VERSION_MAJOR(v) \
321 (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
322#define BP_CLKCTRL_VERSION_MINOR 16
323#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
324#define BF_CLKCTRL_VERSION_MINOR(v) \
325 (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
326#define BP_CLKCTRL_VERSION_STEP 0
327#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
328#define BF_CLKCTRL_VERSION_STEP(v) \
329 (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
330
331#endif /* __REGS_CLKCTRL_MX23_H__ */
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
deleted file mode 100644
index 7d1b061d7943..000000000000
--- a/arch/arm/mach-mxs/regs-clkctrl-mx28.h
+++ /dev/null
@@ -1,486 +0,0 @@
1/*
2 * Freescale CLKCTRL Register Definitions
3 *
4 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * This file is created by xml file. Don't Edit it.
21 *
22 * Xml Revision: 1.48
23 * Template revision: 26195
24 */
25
26#ifndef __REGS_CLKCTRL_MX28_H__
27#define __REGS_CLKCTRL_MX28_H__
28
29#define HW_CLKCTRL_PLL0CTRL0 (0x00000000)
30#define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004)
31#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008)
32#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c)
33
34#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28
35#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000
36#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \
37 (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL)
38#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0
39#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1
40#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2
41#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
42#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24
43#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000
44#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \
45 (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL)
46#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0
47#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1
48#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2
49#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
50#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20
51#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000
52#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \
53 (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL)
54#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0
55#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1
56#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2
57#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
58#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000
59#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000
60
61#define HW_CLKCTRL_PLL0CTRL1 (0x00000010)
62
63#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000
64#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
65#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
66#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
67#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \
68 (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT)
69
70#define HW_CLKCTRL_PLL1CTRL0 (0x00000020)
71#define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024)
72#define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028)
73#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c)
74
75#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
76#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28
77#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000
78#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \
79 (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL)
80#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0
81#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1
82#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2
83#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
84#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24
85#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000
86#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \
87 (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL)
88#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0
89#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1
90#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2
91#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
92#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20
93#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000
94#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \
95 (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL)
96#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0
97#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1
98#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2
99#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
100#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000
101#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000
102
103#define HW_CLKCTRL_PLL1CTRL1 (0x00000030)
104
105#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000
106#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
107#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
108#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
109#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \
110 (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT)
111
112#define HW_CLKCTRL_PLL2CTRL0 (0x00000040)
113#define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044)
114#define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048)
115#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c)
116
117#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000
118#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28
119#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000
120#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \
121 (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
122#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000
123#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24
124#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000
125#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \
126 (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
127#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000
128
129#define HW_CLKCTRL_CPU (0x00000050)
130#define HW_CLKCTRL_CPU_SET (0x00000054)
131#define HW_CLKCTRL_CPU_CLR (0x00000058)
132#define HW_CLKCTRL_CPU_TOG (0x0000005c)
133
134#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
135#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
136#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
137#define BP_CLKCTRL_CPU_DIV_XTAL 16
138#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
139#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
140 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
141#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
142#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
143#define BP_CLKCTRL_CPU_DIV_CPU 0
144#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
145#define BF_CLKCTRL_CPU_DIV_CPU(v) \
146 (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
147
148#define HW_CLKCTRL_HBUS (0x00000060)
149#define HW_CLKCTRL_HBUS_SET (0x00000064)
150#define HW_CLKCTRL_HBUS_CLR (0x00000068)
151#define HW_CLKCTRL_HBUS_TOG (0x0000006c)
152
153#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000
154#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000
155#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000
156#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000
157#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
158#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
159#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
160#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
161#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
162#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
163#define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000
164#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000
165#define BP_CLKCTRL_HBUS_SLOW_DIV 16
166#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
167#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
168 (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
169#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
170#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
171#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
172#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
173#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
174#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
175#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
176#define BP_CLKCTRL_HBUS_DIV 0
177#define BM_CLKCTRL_HBUS_DIV 0x0000001F
178#define BF_CLKCTRL_HBUS_DIV(v) \
179 (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
180
181#define HW_CLKCTRL_XBUS (0x00000070)
182
183#define BM_CLKCTRL_XBUS_BUSY 0x80000000
184#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800
185#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
186#define BP_CLKCTRL_XBUS_DIV 0
187#define BM_CLKCTRL_XBUS_DIV 0x000003FF
188#define BF_CLKCTRL_XBUS_DIV(v) \
189 (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
190
191#define HW_CLKCTRL_XTAL (0x00000080)
192#define HW_CLKCTRL_XTAL_SET (0x00000084)
193#define HW_CLKCTRL_XTAL_CLR (0x00000088)
194#define HW_CLKCTRL_XTAL_TOG (0x0000008c)
195
196#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
197#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
198#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
199#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
200#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
201#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
202#define BP_CLKCTRL_XTAL_DIV_UART 0
203#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
204#define BF_CLKCTRL_XTAL_DIV_UART(v) \
205 (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
206
207#define HW_CLKCTRL_SSP0 (0x00000090)
208
209#define BP_CLKCTRL_SSP0_CLKGATE 31
210#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
211#define BM_CLKCTRL_SSP0_BUSY 0x20000000
212#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200
213#define BP_CLKCTRL_SSP0_DIV 0
214#define BM_CLKCTRL_SSP0_DIV 0x000001FF
215#define BF_CLKCTRL_SSP0_DIV(v) \
216 (((v) << 0) & BM_CLKCTRL_SSP0_DIV)
217
218#define HW_CLKCTRL_SSP1 (0x000000a0)
219
220#define BP_CLKCTRL_SSP1_CLKGATE 31
221#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
222#define BM_CLKCTRL_SSP1_BUSY 0x20000000
223#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200
224#define BP_CLKCTRL_SSP1_DIV 0
225#define BM_CLKCTRL_SSP1_DIV 0x000001FF
226#define BF_CLKCTRL_SSP1_DIV(v) \
227 (((v) << 0) & BM_CLKCTRL_SSP1_DIV)
228
229#define HW_CLKCTRL_SSP2 (0x000000b0)
230
231#define BP_CLKCTRL_SSP2_CLKGATE 31
232#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
233#define BM_CLKCTRL_SSP2_BUSY 0x20000000
234#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200
235#define BP_CLKCTRL_SSP2_DIV 0
236#define BM_CLKCTRL_SSP2_DIV 0x000001FF
237#define BF_CLKCTRL_SSP2_DIV(v) \
238 (((v) << 0) & BM_CLKCTRL_SSP2_DIV)
239
240#define HW_CLKCTRL_SSP3 (0x000000c0)
241
242#define BP_CLKCTRL_SSP3_CLKGATE 31
243#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
244#define BM_CLKCTRL_SSP3_BUSY 0x20000000
245#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200
246#define BP_CLKCTRL_SSP3_DIV 0
247#define BM_CLKCTRL_SSP3_DIV 0x000001FF
248#define BF_CLKCTRL_SSP3_DIV(v) \
249 (((v) << 0) & BM_CLKCTRL_SSP3_DIV)
250
251#define HW_CLKCTRL_GPMI (0x000000d0)
252
253#define BP_CLKCTRL_GPMI_CLKGATE 31
254#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
255#define BM_CLKCTRL_GPMI_BUSY 0x20000000
256#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
257#define BP_CLKCTRL_GPMI_DIV 0
258#define BM_CLKCTRL_GPMI_DIV 0x000003FF
259#define BF_CLKCTRL_GPMI_DIV(v) \
260 (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
261
262#define HW_CLKCTRL_SPDIF (0x000000e0)
263
264#define BP_CLKCTRL_SPDIF_CLKGATE 31
265#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
266
267#define HW_CLKCTRL_EMI (0x000000f0)
268
269#define BP_CLKCTRL_EMI_CLKGATE 31
270#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
271#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
272#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
273#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
274#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
275#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
276#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
277#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
278#define BP_CLKCTRL_EMI_DIV_XTAL 8
279#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
280#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
281 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
282#define BP_CLKCTRL_EMI_DIV_EMI 0
283#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
284#define BF_CLKCTRL_EMI_DIV_EMI(v) \
285 (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
286
287#define HW_CLKCTRL_SAIF0 (0x00000100)
288
289#define BP_CLKCTRL_SAIF0_CLKGATE 31
290#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000
291#define BM_CLKCTRL_SAIF0_BUSY 0x20000000
292#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000
293#define BP_CLKCTRL_SAIF0_DIV 0
294#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF
295#define BF_CLKCTRL_SAIF0_DIV(v) \
296 (((v) << 0) & BM_CLKCTRL_SAIF0_DIV)
297
298#define HW_CLKCTRL_SAIF1 (0x00000110)
299
300#define BP_CLKCTRL_SAIF1_CLKGATE 31
301#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000
302#define BM_CLKCTRL_SAIF1_BUSY 0x20000000
303#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000
304#define BP_CLKCTRL_SAIF1_DIV 0
305#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF
306#define BF_CLKCTRL_SAIF1_DIV(v) \
307 (((v) << 0) & BM_CLKCTRL_SAIF1_DIV)
308
309#define HW_CLKCTRL_DIS_LCDIF (0x00000120)
310
311#define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31
312#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000
313#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000
314#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000
315#define BP_CLKCTRL_DIS_LCDIF_DIV 0
316#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF
317#define BF_CLKCTRL_DIS_LCDIF_DIV(v) \
318 (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV)
319
320#define HW_CLKCTRL_ETM (0x00000130)
321
322#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
323#define BM_CLKCTRL_ETM_BUSY 0x20000000
324#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080
325#define BP_CLKCTRL_ETM_DIV 0
326#define BM_CLKCTRL_ETM_DIV 0x0000007F
327#define BF_CLKCTRL_ETM_DIV(v) \
328 (((v) << 0) & BM_CLKCTRL_ETM_DIV)
329
330#define HW_CLKCTRL_ENET (0x00000140)
331
332#define BM_CLKCTRL_ENET_SLEEP 0x80000000
333#define BP_CLKCTRL_ENET_DISABLE 30
334#define BM_CLKCTRL_ENET_DISABLE 0x40000000
335#define BM_CLKCTRL_ENET_STATUS 0x20000000
336#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000
337#define BP_CLKCTRL_ENET_DIV_TIME 21
338#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000
339#define BF_CLKCTRL_ENET_DIV_TIME(v) \
340 (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME)
341#define BM_CLKCTRL_ENET_BUSY 0x08000000
342#define BP_CLKCTRL_ENET_DIV 21
343#define BM_CLKCTRL_ENET_DIV 0x07E00000
344#define BF_CLKCTRL_ENET_DIV(v) \
345 (((v) << 21) & BM_CLKCTRL_ENET_DIV)
346#define BP_CLKCTRL_ENET_TIME_SEL 19
347#define BM_CLKCTRL_ENET_TIME_SEL 0x00180000
348#define BF_CLKCTRL_ENET_TIME_SEL(v) \
349 (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL)
350#define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0
351#define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1
352#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2
353#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3
354#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000
355#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000
356#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000
357
358#define HW_CLKCTRL_HSADC (0x00000150)
359
360#define BM_CLKCTRL_HSADC_RESETB 0x40000000
361#define BP_CLKCTRL_HSADC_FREQDIV 28
362#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000
363#define BF_CLKCTRL_HSADC_FREQDIV(v) \
364 (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
365
366#define HW_CLKCTRL_FLEXCAN (0x00000160)
367
368#define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30
369#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000
370#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000
371#define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28
372#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000
373#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000
374
375#define HW_CLKCTRL_FRAC0 (0x000001b0)
376#define HW_CLKCTRL_FRAC0_SET (0x000001b4)
377#define HW_CLKCTRL_FRAC0_CLR (0x000001b8)
378#define HW_CLKCTRL_FRAC0_TOG (0x000001bc)
379
380#define BP_CLKCTRL_FRAC0_CLKGATEIO0 31
381#define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000
382#define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000
383#define BP_CLKCTRL_FRAC0_IO0FRAC 24
384#define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000
385#define BF_CLKCTRL_FRAC0_IO0FRAC(v) \
386 (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC)
387#define BP_CLKCTRL_FRAC0_CLKGATEIO1 23
388#define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000
389#define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000
390#define BP_CLKCTRL_FRAC0_IO1FRAC 16
391#define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000
392#define BF_CLKCTRL_FRAC0_IO1FRAC(v) \
393 (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC)
394#define BP_CLKCTRL_FRAC0_CLKGATEEMI 15
395#define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000
396#define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000
397#define BP_CLKCTRL_FRAC0_EMIFRAC 8
398#define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00
399#define BF_CLKCTRL_FRAC0_EMIFRAC(v) \
400 (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC)
401#define BP_CLKCTRL_FRAC0_CLKGATECPU 7
402#define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080
403#define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040
404#define BP_CLKCTRL_FRAC0_CPUFRAC 0
405#define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F
406#define BF_CLKCTRL_FRAC0_CPUFRAC(v) \
407 (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC)
408
409#define HW_CLKCTRL_FRAC1 (0x000001c0)
410#define HW_CLKCTRL_FRAC1_SET (0x000001c4)
411#define HW_CLKCTRL_FRAC1_CLR (0x000001c8)
412#define HW_CLKCTRL_FRAC1_TOG (0x000001cc)
413
414#define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23
415#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000
416#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000
417#define BP_CLKCTRL_FRAC1_GPMIFRAC 16
418#define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000
419#define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \
420 (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC)
421#define BP_CLKCTRL_FRAC1_CLKGATEHSADC 15
422#define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000
423#define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000
424#define BP_CLKCTRL_FRAC1_HSADCFRAC 8
425#define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00
426#define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \
427 (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC)
428#define BP_CLKCTRL_FRAC1_CLKGATEPIX 7
429#define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080
430#define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040
431#define BP_CLKCTRL_FRAC1_PIXFRAC 0
432#define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F
433#define BF_CLKCTRL_FRAC1_PIXFRAC(v) \
434 (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC)
435
436#define HW_CLKCTRL_CLKSEQ (0x000001d0)
437#define HW_CLKCTRL_CLKSEQ_SET (0x000001d4)
438#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8)
439#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc)
440
441#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000
442#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000
443#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
444#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0
445#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
446#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080
447#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040
448#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020
449#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010
450#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008
451#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004
452#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002
453#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001
454
455#define HW_CLKCTRL_RESET (0x000001e0)
456
457#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020
458#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010
459#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008
460#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004
461#define BM_CLKCTRL_RESET_CHIP 0x00000002
462#define BM_CLKCTRL_RESET_DIG 0x00000001
463
464#define HW_CLKCTRL_STATUS (0x000001f0)
465
466#define BP_CLKCTRL_STATUS_CPU_LIMIT 30
467#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
468#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
469 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
470
471#define HW_CLKCTRL_VERSION (0x00000200)
472
473#define BP_CLKCTRL_VERSION_MAJOR 24
474#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
475#define BF_CLKCTRL_VERSION_MAJOR(v) \
476 (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
477#define BP_CLKCTRL_VERSION_MINOR 16
478#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
479#define BF_CLKCTRL_VERSION_MINOR(v) \
480 (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
481#define BP_CLKCTRL_VERSION_STEP 0
482#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
483#define BF_CLKCTRL_VERSION_STEP(v) \
484 (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
485
486#endif /* __REGS_CLKCTRL_MX28_H__ */
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 80ac1fca8a00..30042e23bfa7 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -37,8 +37,6 @@
37#define MXS_MODULE_CLKGATE (1 << 30) 37#define MXS_MODULE_CLKGATE (1 << 30)
38#define MXS_MODULE_SFTRST (1 << 31) 38#define MXS_MODULE_SFTRST (1 << 31)
39 39
40#define CLKCTRL_TIMEOUT 10 /* 10 ms */
41
42static void __iomem *mxs_clkctrl_reset_addr; 40static void __iomem *mxs_clkctrl_reset_addr;
43 41
44/* 42/*
@@ -139,17 +137,3 @@ error:
139 return -ETIMEDOUT; 137 return -ETIMEDOUT;
140} 138}
141EXPORT_SYMBOL(mxs_reset_block); 139EXPORT_SYMBOL(mxs_reset_block);
142
143int mxs_clkctrl_timeout(unsigned int reg_offset, unsigned int mask)
144{
145 unsigned long timeout = jiffies + msecs_to_jiffies(CLKCTRL_TIMEOUT);
146 while (readl_relaxed(MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR)
147 + reg_offset) & mask) {
148 if (time_after(jiffies, timeout)) {
149 pr_err("Timeout at CLKCTRL + 0x%x\n", reg_offset);
150 return -ETIMEDOUT;
151 }
152 }
153
154 return 0;
155}
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index 564a63279f18..02d36de9c4e8 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -20,6 +20,7 @@
20 * MA 02110-1301, USA. 20 * MA 02110-1301, USA.
21 */ 21 */
22 22
23#include <linux/err.h>
23#include <linux/interrupt.h> 24#include <linux/interrupt.h>
24#include <linux/irq.h> 25#include <linux/irq.h>
25#include <linux/clockchips.h> 26#include <linux/clockchips.h>
@@ -243,8 +244,16 @@ static int __init mxs_clocksource_init(struct clk *timer_clk)
243 return 0; 244 return 0;
244} 245}
245 246
246void __init mxs_timer_init(struct clk *timer_clk, int irq) 247void __init mxs_timer_init(int irq)
247{ 248{
249 struct clk *timer_clk;
250
251 timer_clk = clk_get_sys("timrot", NULL);
252 if (IS_ERR(timer_clk)) {
253 pr_err("%s: failed to get clk\n", __func__);
254 return;
255 }
256
248 clk_prepare_enable(timer_clk); 257 clk_prepare_enable(timer_clk);
249 258
250 /* 259 /*
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 03:32:04 -0400