iMX51: introduce IMX_GPIO_NR

Currently, to define a GPIO number, we're using something like :

#define EFIKAMX_PCBID0         (2*32 + 16)

to define GPIO 3 16.

This is not really readable and it's error prone imho (note the 3 vs 2).
So, I'm introducing a new macro to define this in a better way. Now, the
code sample become :

#define EFIKAMX_PCBID0         IMX_GPIO_NR(3, 16)

v2:
- move to gpio.h
- add parens & spaces
- switch to IMX_GPIO_NR instead of MX51_GPIO_NR

Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 5 insertions, 5 deletions

diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 5ff5522ff6fd..6ab002d08a56 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -40,11 +40,11 @@
 #include "devices-imx51.h"
 #include "devices.h"
 
-#define CPUIMX51_USBH1_STP      (0*32 + 27)
-#define CPUIMX51_QUARTA_GPIO    (2*32 + 28)
-#define CPUIMX51_QUARTB_GPIO    (2*32 + 25)
-#define CPUIMX51_QUARTC_GPIO    (2*32 + 26)
-#define CPUIMX51_QUARTD_GPIO    (2*32 + 27)
+#define CPUIMX51_USBH1_STP      IMX_GPIO_NR(1, 27)
+#define CPUIMX51_QUARTA_GPIO    IMX_GPIO_NR(3, 28)
+#define CPUIMX51_QUARTB_GPIO    IMX_GPIO_NR(3, 25)
+#define CPUIMX51_QUARTC_GPIO    IMX_GPIO_NR(3, 26)
+#define CPUIMX51_QUARTD_GPIO    IMX_GPIO_NR(3, 27)
 #define CPUIMX51_QUARTA_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
 #define CPUIMX51_QUARTB_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
 #define CPUIMX51_QUARTC_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)