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authorValentin Longchamp <valentin.longchamp@epfl.ch>2009-01-28 09:13:52 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2009-03-13 05:34:02 -0400
commit945c10b87c4d72ac9ad392132d19d17f3ebdb310 (patch)
tree02b3b10f64356498dc1c4ccdbb3956aced24a342 /arch/arm/mach-mx3/mx31ads.c
parentbfbc6a1fc1d4d4ecbf73bcb7eefcd2a2ca5ddf2a (diff)
mx31ads: use of new iomux implementation
This was only compilation tested. Signed-off-by: Valentin Longchamp <valentin.longchamp@epfl.ch> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-mx3/mx31ads.c')
-rw-r--r--arch/arm/mach-mx3/mx31ads.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index 6804fbe266ef..7941db3caf6f 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -94,13 +94,16 @@ static struct imxuart_platform_data uart_pdata = {
94 .flags = IMXUART_HAVE_RTSCTS, 94 .flags = IMXUART_HAVE_RTSCTS,
95}; 95};
96 96
97static int uart_pins[] = {
98 MX31_PIN_CTS1__CTS1,
99 MX31_PIN_RTS1__RTS1,
100 MX31_PIN_TXD1__TXD1,
101 MX31_PIN_RXD1__RXD1
102};
103
97static inline void mxc_init_imx_uart(void) 104static inline void mxc_init_imx_uart(void)
98{ 105{
99 mxc_iomux_mode(MX31_PIN_CTS1__CTS1); 106 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
100 mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
101 mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
102 mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
103
104 mxc_register_device(&mxc_uart_device0, &uart_pdata); 107 mxc_register_device(&mxc_uart_device0, &uart_pdata);
105} 108}
106#else /* !SERIAL_IMX */ 109#else /* !SERIAL_IMX */
@@ -176,7 +179,7 @@ static void __init mx31ads_init_expio(void)
176 /* 179 /*
177 * Configure INT line as GPIO input 180 * Configure INT line as GPIO input
178 */ 181 */
179 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO)); 182 mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
180 183
181 /* disable the interrupt and clear the status */ 184 /* disable the interrupt and clear the status */
182 __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); 185 __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);