Merge branch 'imx' into devel

Conflicts:

	arch/arm/mm/Kconfig

13 files changed, 3103 insertions, 0 deletions

diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
new file mode 100644
index 000000000000..1eaa97cb716d
--- /dev/null
+++ b/arch/arm/mach-mx2/Kconfig
@@ -0,0 +1,39 @@
+comment "MX2 family CPU support"
+        depends on ARCH_MX2
+
+config MACH_MX27
+        bool "i.MX27 support"
+        depends on ARCH_MX2
+        help
+          This enables support for Freescale's MX2 based i.MX27 processor.
+
+comment "MX2 Platforms"
+        depends on ARCH_MX2
+
+config MACH_MX27ADS
+        bool "MX27ADS platform"
+        depends on MACH_MX27
+        help
+          Include support for MX27ADS platform. This includes specific
+          configurations for the board and its peripherals.
+
+config MACH_PCM038
+        bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
+        depends on MACH_MX27
+        help
+          Include support for phyCORE-i.MX27 (aka pcm038) platform. This
+          includes specific configurations for the module and its peripherals.
+
+choice
+        prompt "Baseboard"
+        depends on MACH_PCM038
+        default MACH_PCM970_BASEBOARD
+
+config MACH_PCM970_BASEBOARD
+        prompt "PHYTEC PCM970 development board"
+        bool
+        help
+          This adds board specific devices that can be found on Phytec's
+          PCM970 evaluation board.
+
+endchoice
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
new file mode 100644
index 000000000000..382d86080e86
--- /dev/null
+++ b/arch/arm/mach-mx2/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y   :=  system.o generic.o devices.o serial.o
+
+obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
+obj-$(CONFIG_MACH_MX27) += clock_imx27.o
+
+obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o
+obj-$(CONFIG_MACH_PCM038) += pcm038.o
+obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-mx2/Makefile.boot
new file mode 100644
index 000000000000..696831dcd485
--- /dev/null
+++ b/arch/arm/mach-mx2/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0xA0008000
+params_phys-y   := 0xA0000100
+initrd_phys-y   := 0xA0800000
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
new file mode 100644
index 000000000000..0a29ef29c73a
--- /dev/null
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -0,0 +1,1626 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/common.h>
+#include <asm/div64.h>
+#include <asm/mach-types.h>
+
+#include "crm_regs.h"
+
+static struct clk ckil_clk;
+static struct clk mpll_clk;
+static struct clk mpll_main_clk[];
+static struct clk spll_clk;
+
+static int _clk_enable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+
+        return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_spll_enable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg |= CCM_CSCR_SPEN;
+        __raw_writel(reg, CCM_CSCR);
+
+        while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0)
+                ;
+
+        return 0;
+}
+
+static void _clk_spll_disable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_CSCR);
+        reg &= ~CCM_CSCR_SPEN;
+        __raw_writel(reg, CCM_CSCR);
+}
+
+static void _clk_pccr01_enable(unsigned long mask0, unsigned long mask1)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR0);
+        reg |= mask0;
+        __raw_writel(reg, CCM_PCCR0);
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg |= mask1;
+        __raw_writel(reg, CCM_PCCR1);
+
+}
+
+static void _clk_pccr01_disable(unsigned long mask0, unsigned long mask1)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR0);
+        reg &= ~mask0;
+        __raw_writel(reg, CCM_PCCR0);
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg &= ~mask1;
+        __raw_writel(reg, CCM_PCCR1);
+}
+
+static void _clk_pccr10_enable(unsigned long mask1, unsigned long mask0)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg |= mask1;
+        __raw_writel(reg, CCM_PCCR1);
+
+        reg = __raw_readl(CCM_PCCR0);
+        reg |= mask0;
+        __raw_writel(reg, CCM_PCCR0);
+}
+
+static void _clk_pccr10_disable(unsigned long mask1, unsigned long mask0)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg &= ~mask1;
+        __raw_writel(reg, CCM_PCCR1);
+
+        reg = __raw_readl(CCM_PCCR0);
+        reg &= ~mask0;
+        __raw_writel(reg, CCM_PCCR0);
+}
+
+static int _clk_dma_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
+
+        return 0;
+}
+
+static void _clk_dma_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
+}
+
+static int _clk_rtic_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
+
+        return 0;
+}
+
+static void _clk_rtic_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
+}
+
+static int _clk_emma_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
+
+        return 0;
+}
+
+static void _clk_emma_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
+}
+
+static int _clk_slcdc_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
+
+        return 0;
+}
+
+static void _clk_slcdc_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
+}
+
+static int _clk_fec_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
+
+        return 0;
+}
+
+static void _clk_fec_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
+}
+
+static int _clk_vpu_enable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg |= CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK;
+        __raw_writel(reg, CCM_PCCR1);
+
+        return 0;
+}
+
+static void _clk_vpu_disable(struct clk *clk)
+{
+        unsigned long reg;
+
+        reg = __raw_readl(CCM_PCCR1);
+        reg &= ~(CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK);
+        __raw_writel(reg, CCM_PCCR1);
+}
+
+static int _clk_sahara2_enable(struct clk *clk)
+{
+        _clk_pccr01_enable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
+
+        return 0;
+}
+
+static void _clk_sahara2_disable(struct clk *clk)
+{
+        _clk_pccr01_disable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
+}
+
+static int _clk_mstick1_enable(struct clk *clk)
+{
+        _clk_pccr10_enable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
+
+        return 0;
+}
+
+static void _clk_mstick1_disable(struct clk *clk)
+{
+        _clk_pccr10_disable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
+}
+
+#define CSCR() (__raw_readl(CCM_CSCR))
+#define PCDR0() (__raw_readl(CCM_PCDR0))
+#define PCDR1() (__raw_readl(CCM_PCDR1))
+
+static int _clk_cpu_set_parent(struct clk *clk, struct clk *parent)
+{
+        int cscr = CSCR();
+
+        if (clk->parent == parent)
+                return 0;
+
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                if (parent == &mpll_main_clk[0]) {
+                        cscr |= CCM_CSCR_ARM_SRC;
+                } else {
+                        if (parent == &mpll_main_clk[1])
+                                cscr &= ~CCM_CSCR_ARM_SRC;
+                        else
+                                return -EINVAL;
+                }
+                __raw_writel(cscr, CCM_CSCR);
+        } else
+                return -ENODEV;
+
+        clk->parent = parent;
+        return 0;
+}
+
+static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate)
+{
+        int div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 4)
+                div = 4;
+
+        return parent_rate / div;
+}
+
+static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned int div;
+        uint32_t reg;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 4 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+
+        div--;
+
+        reg = __raw_readl(CCM_CSCR);
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                reg &= ~CCM_CSCR_ARM_MASK;
+                reg |= div << CCM_CSCR_ARM_OFFSET;
+                reg &= ~0x06;
+                __raw_writel(reg | 0x80000000, CCM_CSCR);
+        } else {
+                printk(KERN_ERR "Cant set CPU frequency!\n");
+        }
+
+        return 0;
+}
+
+static unsigned long _clk_perclkx_round_rate(struct clk *clk,
+                                             unsigned long rate)
+{
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 64)
+                div = 64;
+
+        return parent_rate / div;
+}
+
+static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->id < 0 || clk->id > 3)
+                return -EINVAL;
+
+        div = parent_rate / rate;
+        if (div > 64 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+        div--;
+
+        reg =
+            __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
+                                       (clk->id << 3));
+        reg |= div << (clk->id << 3);
+        __raw_writel(reg, CCM_PCDR1);
+
+        return 0;
+}
+
+static unsigned long _clk_usb_recalc(struct clk *clk)
+{
+        unsigned long usb_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
+
+        return parent_rate / (usb_pdf + 1U);
+}
+
+static unsigned long _clk_ssi1_recalc(struct clk *clk)
+{
+        unsigned long ssi1_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        ssi1_pdf = (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) >>
+                                        CCM_PCDR0_SSI1BAUDDIV_OFFSET;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                ssi1_pdf += 4;
+        else
+                ssi1_pdf = (ssi1_pdf < 2) ? 124UL : ssi1_pdf;
+
+        return 2UL * parent_rate / ssi1_pdf;
+}
+
+static unsigned long _clk_ssi2_recalc(struct clk *clk)
+{
+        unsigned long ssi2_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        ssi2_pdf = (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
+            CCM_PCDR0_SSI2BAUDDIV_OFFSET;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                ssi2_pdf += 4;
+        else
+                ssi2_pdf = (ssi2_pdf < 2) ? 124UL : ssi2_pdf;
+
+        return 2UL * parent_rate / ssi2_pdf;
+}
+
+static unsigned long _clk_nfc_recalc(struct clk *clk)
+{
+        unsigned long nfc_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                nfc_pdf =
+                    (PCDR0() & CCM_PCDR0_NFCDIV2_MASK) >>
+                    CCM_PCDR0_NFCDIV2_OFFSET;
+        } else {
+                nfc_pdf =
+                    (PCDR0() & CCM_PCDR0_NFCDIV_MASK) >>
+                    CCM_PCDR0_NFCDIV_OFFSET;
+        }
+
+        return parent_rate / (nfc_pdf + 1);
+}
+
+static unsigned long _clk_vpu_recalc(struct clk *clk)
+{
+        unsigned long vpu_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                vpu_pdf =
+                    (PCDR0() & CCM_PCDR0_VPUDIV2_MASK) >>
+                    CCM_PCDR0_VPUDIV2_OFFSET;
+                vpu_pdf += 4;
+        } else {
+                vpu_pdf =
+                    (PCDR0() & CCM_PCDR0_VPUDIV_MASK) >>
+                    CCM_PCDR0_VPUDIV_OFFSET;
+                vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
+        }
+        return 2UL * parent_rate / vpu_pdf;
+}
+
+static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->round_rate(clk->parent, rate);
+}
+
+static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
+{
+        return clk->parent->set_rate(clk->parent, rate);
+}
+
+/* in Hz */
+static unsigned long external_high_reference = 26000000;
+
+static unsigned long get_high_reference_clock_rate(struct clk *clk)
+{
+        return external_high_reference;
+}
+
+/*
+ * the high frequency external clock reference
+ * Default case is 26MHz. Could be changed at runtime
+ * with a call to change_external_high_reference()
+ */
+static struct clk ckih_clk = {
+        .name = "ckih",
+        .get_rate = get_high_reference_clock_rate,
+};
+
+/* in Hz */
+static unsigned long external_low_reference = 32768;
+
+static unsigned long get_low_reference_clock_rate(struct clk *clk)
+{
+        return external_low_reference;
+}
+
+/*
+ * the low frequency external clock reference
+ * Default case is 32.768kHz Could be changed at runtime
+ * with a call to change_external_low_reference()
+ */
+static struct clk ckil_clk = {
+        .name = "ckil",
+        .get_rate = get_low_reference_clock_rate,
+};
+
+static unsigned long get_mpll_clk(struct clk *clk)
+{
+        uint32_t reg;
+        unsigned long ref_clk;
+        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+        unsigned long long temp;
+
+        ref_clk = clk_get_rate(clk->parent);
+
+        reg = __raw_readl(CCM_MPCTL0);
+        pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET;
+        mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
+        mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
+        mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
+
+        mfi = (mfi <= 5) ? 5 : mfi;
+        temp = 2LL * ref_clk * mfn;
+        do_div(temp, mfd + 1);
+        temp = 2LL * ref_clk * mfi + temp;
+        do_div(temp, pdf + 1);
+
+        return (unsigned long)temp;
+}
+
+static struct clk mpll_clk = {
+        .name = "mpll",
+        .parent = &ckih_clk,
+        .get_rate = get_mpll_clk,
+};
+
+static unsigned long _clk_mpll_main_get_rate(struct clk *clk)
+{
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        /* i.MX27 TO2:
+         * clk->id == 0: arm clock source path 1 which is from 2*MPLL/DIV_2
+         * clk->id == 1: arm clock source path 2 which is from 2*MPLL/DIV_3
+         */
+
+        if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
+                return 2UL * parent_rate / 3UL;
+
+        return parent_rate;
+}
+
+static struct clk mpll_main_clk[] = {
+        {
+                /* For i.MX27 TO2, it is the MPLL path 1 of ARM core
+                 * It provide the clock source whose rate is same as MPLL
+                 */
+                .name = "mpll_main",
+                .id = 0,
+                .parent = &mpll_clk,
+                .get_rate = _clk_mpll_main_get_rate
+        }, {
+                /* For i.MX27 TO2, it is the MPLL path 2 of ARM core
+                 * It provide the clock source whose rate is same MPLL * 2/3
+                 */
+                .name = "mpll_main",
+                .id = 1,
+                .parent = &mpll_clk,
+                .get_rate = _clk_mpll_main_get_rate
+        }
+};
+
+static unsigned long get_spll_clk(struct clk *clk)
+{
+        uint32_t reg;
+        unsigned long ref_clk;
+        unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
+        unsigned long long temp;
+
+        ref_clk = clk_get_rate(clk->parent);
+
+        reg = __raw_readl(CCM_SPCTL0);
+        /*TODO: This is TO2 Bug */
+        if (mx27_revision() >= CHIP_REV_2_0)
+                __raw_writel(reg, CCM_SPCTL0);
+
+        pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
+        mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
+        mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
+        mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
+
+        mfi = (mfi <= 5) ? 5 : mfi;
+        temp = 2LL * ref_clk * mfn;
+        do_div(temp, mfd + 1);
+        temp = 2LL * ref_clk * mfi + temp;
+        do_div(temp, pdf + 1);
+
+        return (unsigned long)temp;
+}
+
+static struct clk spll_clk = {
+        .name = "spll",
+        .parent = &ckih_clk,
+        .get_rate = get_spll_clk,
+        .enable = _clk_spll_enable,
+        .disable = _clk_spll_disable,
+};
+
+static unsigned long get_cpu_clk(struct clk *clk)
+{
+        u32 div;
+        unsigned long rate;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                div = (CSCR() & CCM_CSCR_ARM_MASK) >> CCM_CSCR_ARM_OFFSET;
+        else
+                div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (div + 1);
+}
+
+static struct clk cpu_clk = {
+        .name = "cpu_clk",
+        .parent = &mpll_main_clk[1],
+        .set_parent = _clk_cpu_set_parent,
+        .round_rate = _clk_cpu_round_rate,
+        .get_rate = get_cpu_clk,
+        .set_rate = _clk_cpu_set_rate,
+};
+
+static unsigned long get_ahb_clk(struct clk *clk)
+{
+        unsigned long rate;
+        unsigned long bclk_pdf;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                bclk_pdf = (CSCR() & CCM_CSCR_AHB_MASK)
+                                        >> CCM_CSCR_AHB_OFFSET;
+        else
+                bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK)
+                                        >> CCM_CSCR_BCLK_OFFSET;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (bclk_pdf + 1);
+}
+
+static struct clk ahb_clk = {
+        .name = "ahb_clk",
+        .parent = &mpll_main_clk[1],
+        .get_rate = get_ahb_clk,
+};
+
+static unsigned long get_ipg_clk(struct clk *clk)
+{
+        unsigned long rate;
+        unsigned long ipg_pdf;
+
+        if (mx27_revision() >= CHIP_REV_2_0)
+                return clk_get_rate(clk->parent);
+        else
+                ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
+
+        rate = clk_get_rate(clk->parent);
+        return rate / (ipg_pdf + 1);
+}
+
+static struct clk ipg_clk = {
+        .name = "ipg_clk",
+        .parent = &ahb_clk,
+        .get_rate = get_ipg_clk,
+};
+
+static unsigned long _clk_perclkx_recalc(struct clk *clk)
+{
+        unsigned long perclk_pdf;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        if (clk->id < 0 || clk->id > 3)
+                return 0;
+
+        perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK;
+
+        return parent_rate / (perclk_pdf + 1);
+}
+
+static struct clk per_clk[] = {
+        {
+                .name = "per_clk",
+                .id = 0,
+                .parent = &mpll_main_clk[1],
+                .get_rate = _clk_perclkx_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_PERCLK1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "per_clk",
+                .id = 1,
+                .parent = &mpll_main_clk[1],
+                .get_rate = _clk_perclkx_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_PERCLK2_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "per_clk",
+                .id = 2,
+                .parent = &mpll_main_clk[1],
+                .round_rate = _clk_perclkx_round_rate,
+                .set_rate = _clk_perclkx_set_rate,
+                .get_rate = _clk_perclkx_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_PERCLK3_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "per_clk",
+                .id = 3,
+                .parent = &mpll_main_clk[1],
+                .round_rate = _clk_perclkx_round_rate,
+                .set_rate = _clk_perclkx_set_rate,
+                .get_rate = _clk_perclkx_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_PERCLK4_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart1_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 0,
+                .parent = &per_clk[0],
+                .secondary = &uart1_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART1_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart2_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 1,
+                .parent = &per_clk[0],
+                .secondary = &uart2_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart3_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 2,
+                .parent = &per_clk[0],
+                .secondary = &uart3_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart4_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 3,
+                .parent = &per_clk[0],
+                .secondary = &uart4_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 3,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART4_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart5_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 4,
+                .parent = &per_clk[0],
+                .secondary = &uart5_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 4,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART5_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+struct clk uart6_clk[] = {
+        {
+                .name = "uart_clk",
+                .id = 5,
+                .parent = &per_clk[0],
+                .secondary = &uart6_clk[1],
+        }, {
+                .name = "uart_ipg_clk",
+                .id = 5,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_UART6_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt1_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 0,
+                .parent = &per_clk[0],
+                .secondary = &gpt1_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT1_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt2_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 1,
+                .parent = &per_clk[0],
+                .secondary = &gpt2_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt3_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 2,
+                .parent = &per_clk[0],
+                .secondary = &gpt3_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt4_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 3,
+                .parent = &per_clk[0],
+                .secondary = &gpt4_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 3,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT4_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt5_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 4,
+                .parent = &per_clk[0],
+                .secondary = &gpt5_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 4,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT5_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk gpt6_clk[] = {
+        {
+                .name = "gpt_clk",
+                .id = 5,
+                .parent = &per_clk[0],
+                .secondary = &gpt6_clk[1],
+        }, {
+                .name = "gpt_ipg_clk",
+                .id = 5,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_GPT6_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk pwm_clk[] = {
+        {
+                .name = "pwm_clk",
+                .parent = &per_clk[0],
+                .secondary = &pwm_clk[1],
+        }, {
+                .name = "pwm_clk",
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_PWM_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk sdhc1_clk[] = {
+        {
+                .name = "sdhc_clk",
+                .id = 0,
+                .parent = &per_clk[1],
+                .secondary = &sdhc1_clk[1],
+        }, {
+                .name = "sdhc_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SDHC1_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk sdhc2_clk[] = {
+        {
+                .name = "sdhc_clk",
+                .id = 1,
+                .parent = &per_clk[1],
+                .secondary = &sdhc2_clk[1],
+        }, {
+                .name = "sdhc_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SDHC2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk sdhc3_clk[] = {
+        {
+                .name = "sdhc_clk",
+                .id = 2,
+                .parent = &per_clk[1],
+                .secondary = &sdhc3_clk[1],
+        }, {
+                .name = "sdhc_ipg_clk",
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SDHC3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk cspi1_clk[] = {
+        {
+                .name = "cspi_clk",
+                .id = 0,
+                .parent = &per_clk[1],
+                .secondary = &cspi1_clk[1],
+        }, {
+                .name = "cspi_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_CSPI1_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk cspi2_clk[] = {
+        {
+                .name = "cspi_clk",
+                .id = 1,
+                .parent = &per_clk[1],
+                .secondary = &cspi2_clk[1],
+        }, {
+                .name = "cspi_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_CSPI2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk cspi3_clk[] = {
+        {
+                .name = "cspi_clk",
+                .id = 2,
+                .parent = &per_clk[1],
+                .secondary = &cspi3_clk[1],
+        }, {
+                .name = "cspi_ipg_clk",
+                .id = 2,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_CSPI3_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk lcdc_clk[] = {
+        {
+                .name = "lcdc_clk",
+                .parent = &per_clk[2],
+                .secondary = &lcdc_clk[1],
+                .round_rate = _clk_parent_round_rate,
+                .set_rate = _clk_parent_set_rate,
+        }, {
+                .name = "lcdc_ipg_clk",
+                .parent = &ipg_clk,
+                .secondary = &lcdc_clk[2],
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_LCDC_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "lcdc_ahb_clk",
+                .parent = &ahb_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_HCLK_LCDC_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk csi_clk[] = {
+        {
+                .name = "csi_perclk",
+                .parent = &per_clk[3],
+                .secondary = &csi_clk[1],
+                .round_rate = _clk_parent_round_rate,
+                .set_rate = _clk_parent_set_rate,
+        }, {
+                .name = "csi_ahb_clk",
+                .parent = &ahb_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_HCLK_CSI_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk usb_clk[] = {
+        {
+                .name = "usb_clk",
+                .parent = &spll_clk,
+                .get_rate = _clk_usb_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_USBOTG_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "usb_ahb_clk",
+                .parent = &ahb_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_HCLK_USBOTG_OFFSET,
+                .disable = _clk_disable,
+        }
+};
+
+static struct clk ssi1_clk[] = {
+        {
+                .name = "ssi_clk",
+                .id = 0,
+                .parent = &mpll_main_clk[1],
+                .secondary = &ssi1_clk[1],
+                .get_rate = _clk_ssi1_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_SSI1_BAUD_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "ssi_ipg_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SSI1_IPG_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk ssi2_clk[] = {
+        {
+                .name = "ssi_clk",
+                .id = 1,
+                .parent = &mpll_main_clk[1],
+                .secondary = &ssi2_clk[1],
+                .get_rate = _clk_ssi2_recalc,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR1,
+                .enable_shift = CCM_PCCR1_SSI2_BAUD_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "ssi_ipg_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_SSI2_IPG_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk nfc_clk = {
+        .name = "nfc_clk",
+        .parent = &cpu_clk,
+        .get_rate = _clk_nfc_recalc,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_NFC_BAUD_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk vpu_clk = {
+        .name = "vpu_clk",
+        .parent = &mpll_main_clk[1],
+        .get_rate = _clk_vpu_recalc,
+        .enable = _clk_vpu_enable,
+        .disable = _clk_vpu_disable,
+};
+
+static struct clk dma_clk = {
+        .name = "dma_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_dma_enable,
+        .disable = _clk_dma_disable,
+};
+
+static struct clk rtic_clk = {
+        .name = "rtic_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_rtic_enable,
+        .disable = _clk_rtic_disable,
+};
+
+static struct clk brom_clk = {
+        .name = "brom_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_HCLK_BROM_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk emma_clk = {
+        .name = "emma_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_emma_enable,
+        .disable = _clk_emma_disable,
+};
+
+static struct clk slcdc_clk = {
+        .name = "slcdc_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_slcdc_enable,
+        .disable = _clk_slcdc_disable,
+};
+
+static struct clk fec_clk = {
+        .name = "fec_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_fec_enable,
+        .disable = _clk_fec_disable,
+};
+
+static struct clk emi_clk = {
+        .name = "emi_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_HCLK_EMI_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk sahara2_clk = {
+        .name = "sahara_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_sahara2_enable,
+        .disable = _clk_sahara2_disable,
+};
+
+static struct clk ata_clk = {
+        .name = "ata_clk",
+        .parent = &ahb_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_HCLK_ATA_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk mstick1_clk = {
+        .name = "mstick1_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_mstick1_enable,
+        .disable = _clk_mstick1_disable,
+};
+
+static struct clk wdog_clk = {
+        .name = "wdog_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR1_WDT_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk gpio_clk = {
+        .name = "gpio_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR1,
+        .enable_shift = CCM_PCCR0_GPIO_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk i2c_clk[] = {
+        {
+                .name = "i2c_clk",
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_I2C1_OFFSET,
+                .disable = _clk_disable,
+        }, {
+                .name = "i2c_clk",
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable = _clk_enable,
+                .enable_reg = CCM_PCCR0,
+                .enable_shift = CCM_PCCR0_I2C2_OFFSET,
+                .disable = _clk_disable,
+        },
+};
+
+static struct clk iim_clk = {
+        .name = "iim_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_IIM_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk kpp_clk = {
+        .name = "kpp_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_KPP_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk owire_clk = {
+        .name = "owire_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_OWIRE_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk rtc_clk = {
+        .name = "rtc_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_RTC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static struct clk scc_clk = {
+        .name = "scc_clk",
+        .parent = &ipg_clk,
+        .enable = _clk_enable,
+        .enable_reg = CCM_PCCR0,
+        .enable_shift = CCM_PCCR0_SCC_OFFSET,
+        .disable = _clk_disable,
+};
+
+static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+        div = parent_rate / rate;
+        if (parent_rate % rate)
+                div++;
+
+        if (div > 8)
+                div = 8;
+
+        return parent_rate / div;
+}
+
+static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 reg;
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = parent_rate / rate;
+
+        if (div > 8 || div < 1 || ((parent_rate / div) != rate))
+                return -EINVAL;
+        div--;
+
+        reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKODIV_MASK;
+        reg |= div << CCM_PCDR0_CLKODIV_OFFSET;
+        __raw_writel(reg, CCM_PCDR0);
+
+        return 0;
+}
+
+static unsigned long _clk_clko_recalc(struct clk *clk)
+{
+        u32 div;
+        unsigned long parent_rate;
+
+        parent_rate = clk_get_rate(clk->parent);
+
+        div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_CLKODIV_MASK >>
+                CCM_PCDR0_CLKODIV_OFFSET;
+        div++;
+
+        return parent_rate / div;
+}
+
+static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
+
+        if (parent == &ckil_clk)
+                reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ckih_clk)
+                reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == mpll_clk.parent)
+                reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == spll_clk.parent)
+                reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &mpll_clk)
+                reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &spll_clk)
+                reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &cpu_clk)
+                reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ahb_clk)
+                reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ipg_clk)
+                reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[0])
+                reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[1])
+                reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[2])
+                reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &per_clk[3])
+                reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ssi1_clk[0])
+                reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &ssi2_clk[0])
+                reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &nfc_clk)
+                reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &mstick1_clk)
+                reg |= 0x11 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &vpu_clk)
+                reg |= 0x12 << CCM_CCSR_CLKOSEL_OFFSET;
+        else if (parent == &usb_clk[0])
+                reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
+        else
+                return -EINVAL;
+
+        __raw_writel(reg, CCM_CCSR);
+
+        return 0;
+}
+
+static int _clk_clko_enable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_PCDR0) | CCM_PCDR0_CLKO_EN;
+        __raw_writel(reg, CCM_PCDR0);
+
+        return 0;
+}
+
+static void _clk_clko_disable(struct clk *clk)
+{
+        u32 reg;
+
+        reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKO_EN;
+        __raw_writel(reg, CCM_PCDR0);
+}
+
+static struct clk clko_clk = {
+        .name = "clko_clk",
+        .get_rate = _clk_clko_recalc,
+        .set_rate = _clk_clko_set_rate,
+        .round_rate = _clk_clko_round_rate,
+        .set_parent = _clk_clko_set_parent,
+        .enable = _clk_clko_enable,
+        .disable = _clk_clko_disable,
+};
+
+static struct clk *mxc_clks[] = {
+        &ckih_clk,
+        &ckil_clk,
+        &mpll_clk,
+        &mpll_main_clk[0],
+        &mpll_main_clk[1],
+        &spll_clk,
+        &cpu_clk,
+        &ahb_clk,
+        &ipg_clk,
+        &per_clk[0],
+        &per_clk[1],
+        &per_clk[2],
+        &per_clk[3],
+        &clko_clk,
+        &uart1_clk[0],
+        &uart1_clk[1],
+        &uart2_clk[0],
+        &uart2_clk[1],
+        &uart3_clk[0],
+        &uart3_clk[1],
+        &uart4_clk[0],
+        &uart4_clk[1],
+        &uart5_clk[0],
+        &uart5_clk[1],
+        &uart6_clk[0],
+        &uart6_clk[1],
+        &gpt1_clk[0],
+        &gpt1_clk[1],
+        &gpt2_clk[0],
+        &gpt2_clk[1],
+        &gpt3_clk[0],
+        &gpt3_clk[1],
+        &gpt4_clk[0],
+        &gpt4_clk[1],
+        &gpt5_clk[0],
+        &gpt5_clk[1],
+        &gpt6_clk[0],
+        &gpt6_clk[1],
+        &pwm_clk[0],
+        &pwm_clk[1],
+        &sdhc1_clk[0],
+        &sdhc1_clk[1],
+        &sdhc2_clk[0],
+        &sdhc2_clk[1],
+        &sdhc3_clk[0],
+        &sdhc3_clk[1],
+        &cspi1_clk[0],
+        &cspi1_clk[1],
+        &cspi2_clk[0],
+        &cspi2_clk[1],
+        &cspi3_clk[0],
+        &cspi3_clk[1],
+        &lcdc_clk[0],
+        &lcdc_clk[1],
+        &lcdc_clk[2],
+        &csi_clk[0],
+        &csi_clk[1],
+        &usb_clk[0],
+        &usb_clk[1],
+        &ssi1_clk[0],
+        &ssi1_clk[1],
+        &ssi2_clk[0],
+        &ssi2_clk[1],
+        &nfc_clk,
+        &vpu_clk,
+        &dma_clk,
+        &rtic_clk,
+        &brom_clk,
+        &emma_clk,
+        &slcdc_clk,
+        &fec_clk,
+        &emi_clk,
+        &sahara2_clk,
+        &ata_clk,
+        &mstick1_clk,
+        &wdog_clk,
+        &gpio_clk,
+        &i2c_clk[0],
+        &i2c_clk[1],
+        &iim_clk,
+        &kpp_clk,
+        &owire_clk,
+        &rtc_clk,
+        &scc_clk,
+};
+
+void __init change_external_low_reference(unsigned long new_ref)
+{
+        external_low_reference = new_ref;
+}
+
+unsigned long __init clk_early_get_timer_rate(void)
+{
+        return clk_get_rate(&per_clk[0]);
+}
+
+static void __init probe_mxc_clocks(void)
+{
+        int i;
+
+        if (mx27_revision() >= CHIP_REV_2_0) {
+                if (CSCR() & 0x8000)
+                        cpu_clk.parent = &mpll_main_clk[0];
+
+                if (!(CSCR() & 0x00800000))
+                        ssi2_clk[0].parent = &spll_clk;
+
+                if (!(CSCR() & 0x00400000))
+                        ssi1_clk[0].parent = &spll_clk;
+
+                if (!(CSCR() & 0x00200000))
+                        vpu_clk.parent = &spll_clk;
+        } else {
+                cpu_clk.parent = &mpll_clk;
+                cpu_clk.set_parent = NULL;
+                cpu_clk.round_rate = NULL;
+                cpu_clk.set_rate = NULL;
+                ahb_clk.parent = &mpll_clk;
+
+                for (i = 0; i < sizeof(per_clk) / sizeof(per_clk[0]); i++)
+                        per_clk[i].parent = &mpll_clk;
+
+                ssi1_clk[0].parent = &mpll_clk;
+                ssi2_clk[0].parent = &mpll_clk;
+
+                vpu_clk.parent = &mpll_clk;
+        }
+}
+
+/*
+ * must be called very early to get information about the
+ * available clock rate when the timer framework starts
+ */
+int __init mxc_clocks_init(unsigned long fref)
+{
+        u32 cscr;
+        struct clk **clkp;
+
+        external_high_reference = fref;
+
+        /* detect clock reference for both system PLL */
+        cscr = CSCR();
+        if (cscr & CCM_CSCR_MCU)
+                mpll_clk.parent = &ckih_clk;
+        else
+                mpll_clk.parent = &ckil_clk;
+
+        if (cscr & CCM_CSCR_SP)
+                spll_clk.parent = &ckih_clk;
+        else
+                spll_clk.parent = &ckil_clk;
+
+        probe_mxc_clocks();
+
+        per_clk[0].enable(&per_clk[0]);
+        gpt1_clk[1].enable(&gpt1_clk[1]);
+
+        for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
+                clk_register(*clkp);
+
+        /* Turn off all possible clocks */
+        __raw_writel(CCM_PCCR0_GPT1_MASK, CCM_PCCR0);
+        __raw_writel(CCM_PCCR1_PERCLK1_MASK | CCM_PCCR1_HCLK_EMI_MASK,
+                     CCM_PCCR1);
+        spll_clk.disable(&spll_clk);
+
+        /* This will propagate to all children and init all the clock rates */
+
+        clk_enable(&emi_clk);
+        clk_enable(&gpio_clk);
+        clk_enable(&iim_clk);
+        clk_enable(&gpt1_clk[0]);
+#ifdef CONFIG_DEBUG_LL_CONSOLE
+        clk_enable(&uart1_clk[0]);
+#endif
+        return 0;
+}
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c
new file mode 100644
index 000000000000..d6b5c2e3377f
--- /dev/null
+++ b/arch/arm/mach-mx2/cpu_imx27.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+/*
+ * i.MX27 specific CPU detection code
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+
+#include <asm/hardware.h>
+
+#include "crm_regs.h"
+
+static int cpu_silicon_rev = -1;
+static int cpu_partnumber;
+
+static void query_silicon_parameter(void)
+{
+        u32 val;
+        /*
+         * now we have access to the IO registers. As we need
+         * the silicon revision very early we read it here to
+         * avoid any further hooks
+        */
+        val = __raw_readl(IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_CHIP_ID);
+
+        cpu_silicon_rev = (int)(val >> 28);
+        cpu_partnumber = (int)((val >> 12) & 0xFFFF);
+}
+
+/*
+ * Returns:
+ *      the silicon revision of the cpu
+ *      -EINVAL - not a mx27
+ */
+int mx27_revision(void)
+{
+        if (cpu_silicon_rev == -1)
+                query_silicon_parameter();
+
+        if (cpu_partnumber != 0x8821)
+                return -EINVAL;
+
+        return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx27_revision);
diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h
new file mode 100644
index 000000000000..a40a9b950ce9
--- /dev/null
+++ b/arch/arm/mach-mx2/crm_regs.h
@@ -0,0 +1,273 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ARCH_ARM_MACH_MX2_CRM_REGS_H__
+#define __ARCH_ARM_MACH_MX2_CRM_REGS_H__
+
+#include <asm/arch/hardware.h>
+
+/* Register offsets */
+#define CCM_CSCR                (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
+#define CCM_MPCTL0              (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
+#define CCM_MPCTL1              (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
+#define CCM_SPCTL0              (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
+#define CCM_SPCTL1              (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
+#define CCM_OSC26MCTL           (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
+#define CCM_PCDR0               (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
+#define CCM_PCDR1               (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
+#define CCM_PCCR0               (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
+#define CCM_PCCR1               (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
+#define CCM_CCSR                (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
+#define CCM_PMCTL               (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
+#define CCM_PMCOUNT             (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
+#define CCM_WKGDCTL             (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
+
+#define CCM_CSCR_USB_OFFSET     28
+#define CCM_CSCR_USB_MASK       (0x7 << 28)
+#define CCM_CSCR_SD_OFFSET      24
+#define CCM_CSCR_SD_MASK        (0x3 << 24)
+#define CCM_CSCR_SSI2           (1 << 23)
+#define CCM_CSCR_SSI2_OFFSET    23
+#define CCM_CSCR_SSI1           (1 << 22)
+#define CCM_CSCR_SSI1_OFFSET    22
+#define CCM_CSCR_VPU           (1 << 21)
+#define CCM_CSCR_VPU_OFFSET    21
+#define CCM_CSCR_MSHC           (1 << 20)
+#define CCM_CSCR_SPLLRES        (1 << 19)
+#define CCM_CSCR_MPLLRES        (1 << 18)
+#define CCM_CSCR_SP             (1 << 17)
+#define CCM_CSCR_MCU            (1 << 16)
+/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_ARM_SRC        (1 << 15)
+#define CCM_CSCR_ARM_OFFSET     12
+#define CCM_CSCR_ARM_MASK       (0x3 << 12)
+/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_PRESC_OFFSET   13
+#define CCM_CSCR_PRESC_MASK     (0x7 << 13)
+#define CCM_CSCR_BCLK_OFFSET    9
+#define CCM_CSCR_BCLK_MASK      (0xf << 9)
+#define CCM_CSCR_IPDIV_OFFSET   8
+#define CCM_CSCR_IPDIV          (1 << 8)
+/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_AHB_OFFSET     8
+#define CCM_CSCR_AHB_MASK       (0x3 << 8)
+/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_OSC26MDIV      (1 << 4)
+#define CCM_CSCR_OSC26M         (1 << 3)
+#define CCM_CSCR_FPM            (1 << 2)
+#define CCM_CSCR_SPEN           (1 << 1)
+#define CCM_CSCR_MPEN           1
+
+#define CCM_MPCTL0_CPLM         (1 << 31)
+#define CCM_MPCTL0_PD_OFFSET    26
+#define CCM_MPCTL0_PD_MASK      (0xf << 26)
+#define CCM_MPCTL0_MFD_OFFSET   16
+#define CCM_MPCTL0_MFD_MASK     (0x3ff << 16)
+#define CCM_MPCTL0_MFI_OFFSET   10
+#define CCM_MPCTL0_MFI_MASK     (0xf << 10)
+#define CCM_MPCTL0_MFN_OFFSET   0
+#define CCM_MPCTL0_MFN_MASK     0x3ff
+
+#define CCM_MPCTL1_LF           (1 << 15)
+#define CCM_MPCTL1_BRMO         (1 << 6)
+
+#define CCM_SPCTL0_CPLM         (1 << 31)
+#define CCM_SPCTL0_PD_OFFSET    26
+#define CCM_SPCTL0_PD_MASK      (0xf << 26)
+#define CCM_SPCTL0_MFD_OFFSET   16
+#define CCM_SPCTL0_MFD_MASK     (0x3ff << 16)
+#define CCM_SPCTL0_MFI_OFFSET   10
+#define CCM_SPCTL0_MFI_MASK     (0xf << 10)
+#define CCM_SPCTL0_MFN_OFFSET   0
+#define CCM_SPCTL0_MFN_MASK     0x3ff
+
+#define CCM_SPCTL1_LF           (1 << 15)
+#define CCM_SPCTL1_BRMO         (1 << 6)
+
+#define CCM_OSC26MCTL_PEAK_OFFSET       16
+#define CCM_OSC26MCTL_PEAK_MASK         (0x3 << 16)
+#define CCM_OSC26MCTL_AGC_OFFSET        8
+#define CCM_OSC26MCTL_AGC_MASK          (0x3f << 8)
+#define CCM_OSC26MCTL_ANATEST_OFFSET    0
+#define CCM_OSC26MCTL_ANATEST_MASK      0x3f
+
+#define CCM_PCDR0_SSI2BAUDDIV_OFFSET    26
+#define CCM_PCDR0_SSI2BAUDDIV_MASK      (0x3f << 26)
+#define CCM_PCDR0_CLKO_EN               25
+#define CCM_PCDR0_CLKODIV_OFFSET        22
+#define CCM_PCDR0_CLKODIV_MASK          (0x7 << 22)
+#define CCM_PCDR0_SSI1BAUDDIV_OFFSET    16
+#define CCM_PCDR0_SSI1BAUDDIV_MASK      (0x3f << 16)
+/*The difinition for i.MX27 TO2*/
+#define CCM_PCDR0_VPUDIV2_OFFSET        10
+#define CCM_PCDR0_VPUDIV2_MASK          (0x3f << 10)
+#define CCM_PCDR0_NFCDIV2_OFFSET         6
+#define CCM_PCDR0_NFCDIV2_MASK           (0xf << 6)
+#define CCM_PCDR0_MSHCDIV2_MASK          0x3f
+/*The difinition for i.MX27 TO2*/
+#define CCM_PCDR0_NFCDIV_OFFSET         12
+#define CCM_PCDR0_NFCDIV_MASK           (0xf << 12)
+#define CCM_PCDR0_VPUDIV_OFFSET        8
+#define CCM_PCDR0_VPUDIV_MASK          (0xf << 8)
+#define CCM_PCDR0_MSHCDIV_OFFSET        0
+#define CCM_PCDR0_MSHCDIV_MASK          0x1f
+
+#define CCM_PCDR1_PERDIV4_OFFSET        24
+#define CCM_PCDR1_PERDIV4_MASK          (0x3f << 24)
+#define CCM_PCDR1_PERDIV3_OFFSET        16
+#define CCM_PCDR1_PERDIV3_MASK          (0x3f << 16)
+#define CCM_PCDR1_PERDIV2_OFFSET        8
+#define CCM_PCDR1_PERDIV2_MASK          (0x3f << 8)
+#define CCM_PCDR1_PERDIV1_OFFSET        0
+#define CCM_PCDR1_PERDIV1_MASK          0x3f
+
+#define CCM_PCCR0_CSPI1_OFFSET          31
+#define CCM_PCCR0_CSPI1_MASK            (1 << 31)
+#define CCM_PCCR0_CSPI2_OFFSET          30
+#define CCM_PCCR0_CSPI2_MASK            (1 << 30)
+#define CCM_PCCR0_CSPI3_OFFSET          29
+#define CCM_PCCR0_CSPI3_MASK            (1 << 29)
+#define CCM_PCCR0_DMA_OFFSET            28
+#define CCM_PCCR0_DMA_MASK              (1 << 28)
+#define CCM_PCCR0_EMMA_OFFSET           27
+#define CCM_PCCR0_EMMA_MASK             (1 << 27)
+#define CCM_PCCR0_FEC_OFFSET            26
+#define CCM_PCCR0_FEC_MASK              (1 << 26)
+#define CCM_PCCR0_GPIO_OFFSET           25
+#define CCM_PCCR0_GPIO_MASK             (1 << 25)
+#define CCM_PCCR0_GPT1_OFFSET           24
+#define CCM_PCCR0_GPT1_MASK             (1 << 24)
+#define CCM_PCCR0_GPT2_OFFSET           23
+#define CCM_PCCR0_GPT2_MASK             (1 << 23)
+#define CCM_PCCR0_GPT3_OFFSET           22
+#define CCM_PCCR0_GPT3_MASK             (1 << 22)
+#define CCM_PCCR0_GPT4_OFFSET           21
+#define CCM_PCCR0_GPT4_MASK             (1 << 21)
+#define CCM_PCCR0_GPT5_OFFSET           20
+#define CCM_PCCR0_GPT5_MASK             (1 << 20)
+#define CCM_PCCR0_GPT6_OFFSET           19
+#define CCM_PCCR0_GPT6_MASK             (1 << 19)
+#define CCM_PCCR0_I2C1_OFFSET           18
+#define CCM_PCCR0_I2C1_MASK             (1 << 18)
+#define CCM_PCCR0_I2C2_OFFSET           17
+#define CCM_PCCR0_I2C2_MASK             (1 << 17)
+#define CCM_PCCR0_IIM_OFFSET            16
+#define CCM_PCCR0_IIM_MASK              (1 << 16)
+#define CCM_PCCR0_KPP_OFFSET            15
+#define CCM_PCCR0_KPP_MASK              (1 << 15)
+#define CCM_PCCR0_LCDC_OFFSET           14
+#define CCM_PCCR0_LCDC_MASK             (1 << 14)
+#define CCM_PCCR0_MSHC_OFFSET           13
+#define CCM_PCCR0_MSHC_MASK             (1 << 13)
+#define CCM_PCCR0_OWIRE_OFFSET          12
+#define CCM_PCCR0_OWIRE_MASK            (1 << 12)
+#define CCM_PCCR0_PWM_OFFSET            11
+#define CCM_PCCR0_PWM_MASK              (1 << 11)
+#define CCM_PCCR0_RTC_OFFSET            9
+#define CCM_PCCR0_RTC_MASK              (1 << 9)
+#define CCM_PCCR0_RTIC_OFFSET           8
+#define CCM_PCCR0_RTIC_MASK             (1 << 8)
+#define CCM_PCCR0_SAHARA_OFFSET         7
+#define CCM_PCCR0_SAHARA_MASK           (1 << 7)
+#define CCM_PCCR0_SCC_OFFSET            6
+#define CCM_PCCR0_SCC_MASK              (1 << 6)
+#define CCM_PCCR0_SDHC1_OFFSET          5
+#define CCM_PCCR0_SDHC1_MASK            (1 << 5)
+#define CCM_PCCR0_SDHC2_OFFSET          4
+#define CCM_PCCR0_SDHC2_MASK            (1 << 4)
+#define CCM_PCCR0_SDHC3_OFFSET          3
+#define CCM_PCCR0_SDHC3_MASK            (1 << 3)
+#define CCM_PCCR0_SLCDC_OFFSET          2
+#define CCM_PCCR0_SLCDC_MASK            (1 << 2)
+#define CCM_PCCR0_SSI1_IPG_OFFSET       1
+#define CCM_PCCR0_SSI1_IPG_MASK         (1 << 1)
+#define CCM_PCCR0_SSI2_IPG_OFFSET       0
+#define CCM_PCCR0_SSI2_IPG_MASK         (1 << 0)
+
+#define CCM_PCCR1_UART1_OFFSET          31
+#define CCM_PCCR1_UART1_MASK            (1 << 31)
+#define CCM_PCCR1_UART2_OFFSET          30
+#define CCM_PCCR1_UART2_MASK            (1 << 30)
+#define CCM_PCCR1_UART3_OFFSET          29
+#define CCM_PCCR1_UART3_MASK            (1 << 29)
+#define CCM_PCCR1_UART4_OFFSET          28
+#define CCM_PCCR1_UART4_MASK            (1 << 28)
+#define CCM_PCCR1_UART5_OFFSET          27
+#define CCM_PCCR1_UART5_MASK            (1 << 27)
+#define CCM_PCCR1_UART6_OFFSET          26
+#define CCM_PCCR1_UART6_MASK            (1 << 26)
+#define CCM_PCCR1_USBOTG_OFFSET         25
+#define CCM_PCCR1_USBOTG_MASK           (1 << 25)
+#define CCM_PCCR1_WDT_OFFSET            24
+#define CCM_PCCR1_WDT_MASK              (1 << 24)
+#define CCM_PCCR1_HCLK_ATA_OFFSET       23
+#define CCM_PCCR1_HCLK_ATA_MASK         (1 << 23)
+#define CCM_PCCR1_HCLK_BROM_OFFSET      22
+#define CCM_PCCR1_HCLK_BROM_MASK        (1 << 22)
+#define CCM_PCCR1_HCLK_CSI_OFFSET       21
+#define CCM_PCCR1_HCLK_CSI_MASK         (1 << 21)
+#define CCM_PCCR1_HCLK_DMA_OFFSET       20
+#define CCM_PCCR1_HCLK_DMA_MASK         (1 << 20)
+#define CCM_PCCR1_HCLK_EMI_OFFSET       19
+#define CCM_PCCR1_HCLK_EMI_MASK         (1 << 19)
+#define CCM_PCCR1_HCLK_EMMA_OFFSET      18
+#define CCM_PCCR1_HCLK_EMMA_MASK        (1 << 18)
+#define CCM_PCCR1_HCLK_FEC_OFFSET       17
+#define CCM_PCCR1_HCLK_FEC_MASK         (1 << 17)
+#define CCM_PCCR1_HCLK_VPU_OFFSET       16
+#define CCM_PCCR1_HCLK_VPU_MASK         (1 << 16)
+#define CCM_PCCR1_HCLK_LCDC_OFFSET      15
+#define CCM_PCCR1_HCLK_LCDC_MASK        (1 << 15)
+#define CCM_PCCR1_HCLK_RTIC_OFFSET      14
+#define CCM_PCCR1_HCLK_RTIC_MASK        (1 << 14)
+#define CCM_PCCR1_HCLK_SAHARA_OFFSET    13
+#define CCM_PCCR1_HCLK_SAHARA_MASK      (1 << 13)
+#define CCM_PCCR1_HCLK_SLCDC_OFFSET     12
+#define CCM_PCCR1_HCLK_SLCDC_MASK       (1 << 12)
+#define CCM_PCCR1_HCLK_USBOTG_OFFSET    11
+#define CCM_PCCR1_HCLK_USBOTG_MASK      (1 << 11)
+#define CCM_PCCR1_PERCLK1_OFFSET        10
+#define CCM_PCCR1_PERCLK1_MASK          (1 << 10)
+#define CCM_PCCR1_PERCLK2_OFFSET        9
+#define CCM_PCCR1_PERCLK2_MASK          (1 << 9)
+#define CCM_PCCR1_PERCLK3_OFFSET        8
+#define CCM_PCCR1_PERCLK3_MASK          (1 << 8)
+#define CCM_PCCR1_PERCLK4_OFFSET        7
+#define CCM_PCCR1_PERCLK4_MASK          (1 << 7)
+#define CCM_PCCR1_VPU_BAUD_OFFSET       6
+#define CCM_PCCR1_VPU_BAUD_MASK         (1 << 6)
+#define CCM_PCCR1_SSI1_BAUD_OFFSET      5
+#define CCM_PCCR1_SSI1_BAUD_MASK        (1 << 5)
+#define CCM_PCCR1_SSI2_BAUD_OFFSET      4
+#define CCM_PCCR1_SSI2_BAUD_MASK        (1 << 4)
+#define CCM_PCCR1_NFC_BAUD_OFFSET       3
+#define CCM_PCCR1_NFC_BAUD_MASK         (1 << 3)
+#define CCM_PCCR1_MSHC_BAUD_OFFSET      2
+#define CCM_PCCR1_MSHC_BAUD_MASK        (1 << 2)
+
+#define CCM_CCSR_32KSR          (1 << 15)
+#define CCM_CCSR_CLKMODE1       (1 << 9)
+#define CCM_CCSR_CLKMODE0       (1 << 8)
+#define CCM_CCSR_CLKOSEL_OFFSET 0
+#define CCM_CCSR_CLKOSEL_MASK   0x1f
+
+#define SYS_FMCR                0x14    /*  Functional Muxing Control Reg */
+#define SYS_CHIP_ID             0x00    /* The offset of CHIP ID register */
+
+#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
new file mode 100644
index 000000000000..a1f44c3c5315
--- /dev/null
+++ b/arch/arm/mach-mx2/devices.c
@@ -0,0 +1,231 @@
+/*
+ * Author: MontaVista Software, Inc.
+ *       <source@mvista.com>
+ *
+ * Based on the OMAP devices.c
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+
+#include <asm/hardware.h>
+
+/*
+ * Resource definition for the MXC IrDA
+ */
+static struct resource mxc_irda_resources[] = {
+        [0] = {
+                .start   = UART3_BASE_ADDR,
+                .end     = UART3_BASE_ADDR + SZ_4K - 1,
+                .flags   = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start   = MXC_INT_UART3,
+                .end     = MXC_INT_UART3,
+                .flags   = IORESOURCE_IRQ,
+        },
+};
+
+/* Platform Data for MXC IrDA */
+struct platform_device mxc_irda_device = {
+        .name = "mxc_irda",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_irda_resources),
+        .resource = mxc_irda_resources,
+};
+
+/*
+ * General Purpose Timer
+ * - i.MX1: 2 timer (slighly different register handling)
+ * - i.MX21: 3 timer
+ * - i.MX27: 6 timer
+ */
+
+/* We use gpt0 as system timer, so do not add a device for this one */
+
+static struct resource timer1_resources[] = {
+        [0] = {
+                .start  = GPT2_BASE_ADDR,
+                .end    = GPT2_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT2,
+                .end     = MXC_INT_GPT2,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt1 = {
+        .name = "imx_gpt",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(timer1_resources),
+        .resource = timer1_resources
+};
+
+static struct resource timer2_resources[] = {
+        [0] = {
+                .start  = GPT3_BASE_ADDR,
+                .end    = GPT3_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT3,
+                .end     = MXC_INT_GPT3,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt2 = {
+        .name = "imx_gpt",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(timer2_resources),
+        .resource = timer2_resources
+};
+
+#ifdef CONFIG_MACH_MX27
+static struct resource timer3_resources[] = {
+        [0] = {
+                .start  = GPT4_BASE_ADDR,
+                .end    = GPT4_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT4,
+                .end     = MXC_INT_GPT4,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt3 = {
+        .name = "imx_gpt",
+        .id = 3,
+        .num_resources = ARRAY_SIZE(timer3_resources),
+        .resource = timer3_resources
+};
+
+static struct resource timer4_resources[] = {
+        [0] = {
+                .start  = GPT5_BASE_ADDR,
+                .end    = GPT5_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT5,
+                .end     = MXC_INT_GPT5,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt4 = {
+        .name = "imx_gpt",
+        .id = 4,
+        .num_resources = ARRAY_SIZE(timer4_resources),
+        .resource = timer4_resources
+};
+
+static struct resource timer5_resources[] = {
+        [0] = {
+                .start  = GPT6_BASE_ADDR,
+                .end    = GPT6_BASE_ADDR + 0x17,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start   = MXC_INT_GPT6,
+                .end     = MXC_INT_GPT6,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+
+struct platform_device mxc_gpt5 = {
+        .name = "imx_gpt",
+        .id = 5,
+        .num_resources = ARRAY_SIZE(timer5_resources),
+        .resource = timer5_resources
+};
+#endif
+
+/*
+ * Watchdog:
+ * - i.MX1
+ * - i.MX21
+ * - i.MX27
+ */
+static struct resource mxc_wdt_resources[] = {
+        {
+                .start  = WDOG_BASE_ADDR,
+                .end    = WDOG_BASE_ADDR + 0x30,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device mxc_wdt = {
+        .name = "mxc_wdt",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_wdt_resources),
+        .resource = mxc_wdt_resources,
+};
+
+/* GPIO port description */
+static struct mxc_gpio_port imx_gpio_ports[] = {
+        [0] = {
+                .chip.label = "gpio-0",
+                .irq = MXC_INT_GPIO,
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0),
+                .virtual_irq_start = MXC_MAX_INT_LINES,
+        },
+        [1] = {
+                .chip.label = "gpio-1",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 32,
+        },
+        [2] = {
+                .chip.label = "gpio-2",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 64,
+        },
+        [3] = {
+                .chip.label = "gpio-3",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 96,
+        },
+        [4] = {
+                .chip.label = "gpio-4",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 128,
+        },
+        [5] = {
+                .chip.label = "gpio-5",
+                .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5),
+                .virtual_irq_start = MXC_MAX_INT_LINES + 160,
+        }
+};
+
+int __init mxc_register_gpios(void)
+{
+        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
+}
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c
new file mode 100644
index 000000000000..07875cf00de9
--- /dev/null
+++ b/arch/arm/mach-mx2/generic.c
@@ -0,0 +1,74 @@
+/*
+ * generic.c
+ *
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <asm/hardware.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+/* MX27 memory map definition */
+static struct map_desc mxc_io_desc[] __initdata = {
+        /*
+         * this fixed mapping covers:
+         * - AIPI1
+         * - AIPI2
+         * - AITC
+         * - ROM Patch
+         * - and some reserved space
+         */
+        {
+                .virtual = AIPI_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(AIPI_BASE_ADDR),
+                .length = AIPI_SIZE,
+                .type = MT_DEVICE
+        },
+        /*
+         * this fixed mapping covers:
+         * - CSI
+         * - ATA
+         */
+        {
+                .virtual = SAHB1_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(SAHB1_BASE_ADDR),
+                .length = SAHB1_SIZE,
+                .type = MT_DEVICE
+        },
+        /*
+         * this fixed mapping covers:
+         * - EMI
+         */
+        {
+                .virtual = X_MEMC_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
+                .length = X_MEMC_SIZE,
+                .type = MT_DEVICE
+        }
+};
+
+/*
+ * Initialize the memory map. It is called during the
+ * system startup to create static physical to virtual
+ * memory map for the IO modules.
+ */
+void __init mxc_map_io(void)
+{
+        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
new file mode 100644
index 000000000000..a9ff01fff137
--- /dev/null
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -0,0 +1,304 @@
+/*
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <asm/arch/common.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/imx-uart.h>
+#include <asm/arch/iomux-mx1-mx2.h>
+#include <asm/arch/board-mx27ads.h>
+
+/* ADS's NOR flash */
+static struct physmap_flash_data mx27ads_flash_data = {
+        .width = 2,
+};
+
+static struct resource mx27ads_flash_resource = {
+        .start = 0xc0000000,
+        .end = 0xc0000000 + 0x02000000 - 1,
+        .flags = IORESOURCE_MEM,
+
+};
+
+static struct platform_device mx27ads_nor_mtd_device = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &mx27ads_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &mx27ads_flash_resource,
+};
+
+static int mxc_uart0_pins[] = {
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS
+};
+
+static int uart_mxc_port0_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
+                        ARRAY_SIZE(mxc_uart0_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
+}
+
+static int uart_mxc_port0_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
+                        ARRAY_SIZE(mxc_uart0_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART0");
+}
+
+static int mxc_uart1_pins[] = {
+        PE3_PF_UART2_CTS,
+        PE4_PF_UART2_RTS,
+        PE6_PF_UART2_TXD,
+        PE7_PF_UART2_RXD
+};
+
+static int uart_mxc_port1_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
+}
+
+static int uart_mxc_port1_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART1");
+}
+
+static int mxc_uart2_pins[] = {
+        PE8_PF_UART3_TXD,
+        PE9_PF_UART3_RXD,
+        PE10_PF_UART3_CTS,
+        PE11_PF_UART3_RTS
+};
+
+static int uart_mxc_port2_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+                        ARRAY_SIZE(mxc_uart2_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
+}
+
+static int uart_mxc_port2_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+                        ARRAY_SIZE(mxc_uart2_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART2");
+}
+
+static int mxc_uart3_pins[] = {
+        PB26_AF_UART4_RTS,
+        PB28_AF_UART4_TXD,
+        PB29_AF_UART4_CTS,
+        PB31_AF_UART4_RXD
+};
+
+static int uart_mxc_port3_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
+                        ARRAY_SIZE(mxc_uart3_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART3");
+}
+
+static int uart_mxc_port3_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
+                        ARRAY_SIZE(mxc_uart3_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART3");
+}
+
+static int mxc_uart4_pins[] = {
+        PB18_AF_UART5_TXD,
+        PB19_AF_UART5_RXD,
+        PB20_AF_UART5_CTS,
+        PB21_AF_UART5_RTS
+};
+
+static int uart_mxc_port4_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
+                        ARRAY_SIZE(mxc_uart4_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART4");
+}
+
+static int uart_mxc_port4_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
+                        ARRAY_SIZE(mxc_uart4_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART4");
+}
+
+static int mxc_uart5_pins[] = {
+        PB10_AF_UART6_TXD,
+        PB12_AF_UART6_CTS,
+        PB11_AF_UART6_RXD,
+        PB13_AF_UART6_RTS
+};
+
+static int uart_mxc_port5_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
+                        ARRAY_SIZE(mxc_uart5_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART5");
+}
+
+static int uart_mxc_port5_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
+                        ARRAY_SIZE(mxc_uart5_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART5");
+}
+
+static struct platform_device *platform_devices[] __initdata = {
+        &mx27ads_nor_mtd_device,
+};
+
+static int mxc_fec_pins[] = {
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_CLR,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN
+};
+
+static void gpio_fec_active(void)
+{
+        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
+                        ARRAY_SIZE(mxc_fec_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
+}
+
+static void gpio_fec_inactive(void)
+{
+        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
+                        ARRAY_SIZE(mxc_fec_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
+}
+
+static struct imxuart_platform_data uart_pdata[] = {
+        {
+                .init = uart_mxc_port0_init,
+                .exit = uart_mxc_port0_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port1_init,
+                .exit = uart_mxc_port1_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port2_init,
+                .exit = uart_mxc_port2_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port3_init,
+                .exit = uart_mxc_port3_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port4_init,
+                .exit = uart_mxc_port4_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port5_init,
+                .exit = uart_mxc_port5_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+};
+
+static void __init mx27ads_board_init(void)
+{
+        int i;
+
+        gpio_fec_active();
+
+        for (i = 0; i < 6; i++)
+                imx_init_uart(i, &uart_pdata[i]);
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init mx27ads_timer_init(void)
+{
+        unsigned long fref = 26000000;
+
+        if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
+                fref = 27000000;
+
+        mxc_clocks_init(fref);
+        mxc_timer_init("gpt_clk.0");
+}
+
+struct sys_timer mx27ads_timer = {
+        .init   = mx27ads_timer_init,
+};
+
+static struct map_desc mx27ads_io_desc[] __initdata = {
+        {
+                .virtual = PBC_BASE_ADDRESS,
+                .pfn = __phys_to_pfn(CS4_BASE_ADDR),
+                .length = SZ_1M,
+                .type = MT_DEVICE,
+        },
+};
+
+void __init mx27ads_map_io(void)
+{
+        mxc_map_io();
+        iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
+}
+
+MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
+        /* maintainer: Freescale Semiconductor, Inc. */
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx27ads_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = mx27ads_board_init,
+        .timer          = &mx27ads_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
new file mode 100644
index 000000000000..a9a28f58e714
--- /dev/null
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/arch/common.h>
+#include <asm/hardware.h>
+#include <asm/arch/iomux-mx1-mx2.h>
+#include <asm/mach/time.h>
+#include <asm/arch/imx-uart.h>
+#include <asm/arch/board-pcm038.h>
+
+/*
+ * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
+ * 16 bit width
+ */
+static struct physmap_flash_data pcm038_flash_data = {
+        .width = 2,
+};
+
+static struct resource pcm038_flash_resource = {
+        .start = 0xc0000000,
+        .end   = 0xc1ffffff,
+        .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device pcm038_nor_mtd_device = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &pcm038_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &pcm038_flash_resource,
+};
+
+static int mxc_uart0_pins[] = {
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS
+};
+
+static int uart_mxc_port0_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
+                        ARRAY_SIZE(mxc_uart0_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
+}
+
+static int uart_mxc_port0_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
+                        ARRAY_SIZE(mxc_uart0_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART0");
+}
+
+static int mxc_uart1_pins[] = {
+        PE3_PF_UART2_CTS,
+        PE4_PF_UART2_RTS,
+        PE6_PF_UART2_TXD,
+        PE7_PF_UART2_RXD
+};
+
+static int uart_mxc_port1_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
+}
+
+static int uart_mxc_port1_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+                        ARRAY_SIZE(mxc_uart1_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART1");
+}
+
+static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS,
+                                PE9_PF_UART3_RXD,
+                                PE10_PF_UART3_CTS,
+                                PE9_PF_UART3_RXD };
+
+static int uart_mxc_port2_init(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+                        ARRAY_SIZE(mxc_uart2_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
+}
+
+static int uart_mxc_port2_exit(struct platform_device *pdev)
+{
+        return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
+                        ARRAY_SIZE(mxc_uart2_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "UART2");
+}
+
+static struct imxuart_platform_data uart_pdata[] = {
+        {
+                .init = uart_mxc_port0_init,
+                .exit = uart_mxc_port0_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port1_init,
+                .exit = uart_mxc_port1_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .init = uart_mxc_port2_init,
+                .exit = uart_mxc_port2_exit,
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+};
+
+static int mxc_fec_pins[] = {
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_CLR,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN
+};
+
+static void gpio_fec_active(void)
+{
+        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
+                        ARRAY_SIZE(mxc_fec_pins),
+                        MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
+}
+
+static void gpio_fec_inactive(void)
+{
+        mxc_gpio_setup_multiple_pins(mxc_fec_pins,
+                        ARRAY_SIZE(mxc_fec_pins),
+                        MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
+}
+
+static struct platform_device *platform_devices[] __initdata = {
+        &pcm038_nor_mtd_device,
+};
+
+static void __init pcm038_init(void)
+{
+        int i;
+        gpio_fec_active();
+
+        for (i = 0; i < 3; i++)
+                imx_init_uart(i, &uart_pdata[i]);
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+#ifdef CONFIG_MACH_PCM970_BASEBOARD
+        pcm970_baseboard_init();
+#endif
+}
+
+static void __init pcm038_timer_init(void)
+{
+        mxc_clocks_init(26000000);
+        mxc_timer_init("gpt_clk.0");
+}
+
+struct sys_timer pcm038_timer = {
+        .init = pcm038_timer_init,
+};
+
+MACHINE_START(PCM038, "phyCORE-i.MX27")
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mxc_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = pcm038_init,
+        .timer          = &pcm038_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
new file mode 100644
index 000000000000..028ac4d33684
--- /dev/null
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/platform_device.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+/*
+ * system init for baseboard usage. Will be called by pcm038 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init pcm970_baseboard_init(void)
+{
+}
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
new file mode 100644
index 000000000000..570c02b8e5df
--- /dev/null
+++ b/arch/arm/mach-mx2/serial.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <asm/hardware.h>
+#include <asm/arch/imx-uart.h>
+
+static struct resource uart0[] = {
+        {
+                .start = UART1_BASE_ADDR,
+                .end = UART1_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART1,
+                .end = MXC_INT_UART1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device0 = {
+        .name = "imx-uart",
+        .id = 0,
+        .resource = uart0,
+        .num_resources = ARRAY_SIZE(uart0),
+};
+
+static struct resource uart1[] = {
+        {
+                .start = UART2_BASE_ADDR,
+                .end = UART2_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART2,
+                .end = MXC_INT_UART2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device1 = {
+        .name = "imx-uart",
+        .id = 1,
+        .resource = uart1,
+        .num_resources = ARRAY_SIZE(uart1),
+};
+
+static struct resource uart2[] = {
+        {
+                .start = UART3_BASE_ADDR,
+                .end = UART3_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART3,
+                .end = MXC_INT_UART3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device2 = {
+        .name = "imx-uart",
+        .id = 2,
+        .resource = uart2,
+        .num_resources = ARRAY_SIZE(uart2),
+};
+
+static struct resource uart3[] = {
+        {
+                .start = UART4_BASE_ADDR,
+                .end = UART4_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART4,
+                .end = MXC_INT_UART4,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device3 = {
+        .name = "imx-uart",
+        .id = 3,
+        .resource = uart3,
+        .num_resources = ARRAY_SIZE(uart3),
+};
+
+static struct resource uart4[] = {
+        {
+                .start = UART5_BASE_ADDR,
+                .end = UART5_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART5,
+                .end = MXC_INT_UART5,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device4 = {
+        .name = "imx-uart",
+        .id = 4,
+        .resource = uart4,
+        .num_resources = ARRAY_SIZE(uart4),
+};
+
+static struct resource uart5[] = {
+        {
+                .start = UART6_BASE_ADDR,
+                .end = UART6_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_UART6,
+                .end = MXC_INT_UART6,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mxc_uart_device5 = {
+        .name = "imx-uart",
+        .id = 5,
+        .resource = uart5,
+        .num_resources = ARRAY_SIZE(uart5),
+};
+
+/*
+ * Register only those UARTs that physically exists
+ */
+int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata)
+{
+        switch (uart_no) {
+        case 0:
+                mxc_uart_device0.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device0);
+                break;
+        case 1:
+                mxc_uart_device1.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device1);
+                break;
+#ifndef CONFIG_MXC_IRDA
+        case 2:
+                mxc_uart_device2.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device2);
+                break;
+#endif
+        case 3:
+                mxc_uart_device3.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device3);
+                break;
+        case 4:
+                mxc_uart_device4.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device4);
+                break;
+        case 5:
+                mxc_uart_device5.dev.platform_data = pdata;
+                platform_device_register(&mxc_uart_device5);
+                break;
+        default:
+                return -ENODEV;
+        }
+
+        return 0;
+}
diff --git a/arch/arm/mach-mx2/system.c b/arch/arm/mach-mx2/system.c
new file mode 100644
index 000000000000..99304645299d
--- /dev/null
+++ b/arch/arm/mach-mx2/system.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 1999 ARM Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/arch/hardware.h>
+#include <asm/proc-fns.h>
+#include <asm/system.h>
+
+/*
+ * Put the CPU into idle mode. It is called by default_idle()
+ * in process.c file.
+ */
+void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks.
+         */
+        cpu_do_idle();
+}
+
+#define WDOG_WCR_REG                    IO_ADDRESS(WDOG_BASE_ADDR)
+#define WDOG_WCR_SRS                    (1 << 4)
+
+/*
+ * Reset the system. It is called by machine_restart().
+ */
+void arch_reset(char mode)
+{
+        struct clk *clk;
+
+        clk = clk_get(NULL, "wdog_clk");
+        if (!clk) {
+                printk(KERN_ERR"Cannot activate the watchdog. Giving up\n");
+                return;
+        }
+
+        clk_enable(clk);
+
+        /* Assert SRS signal */
+        __raw_writew(__raw_readw(WDOG_WCR_REG) & ~WDOG_WCR_SRS, WDOG_WCR_REG);
+}