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authorLinus Torvalds <torvalds@linux-foundation.org>2009-06-14 16:42:43 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-06-14 16:42:43 -0400
commit2cf4d4514d5b43c1f3b64bd0ec8b9853bde8f1dc (patch)
treee35a625496acc6ac852846d40b8851186b9d1ac4 /arch/arm/mach-mx2
parent44b7532b8b464f606053562400719c9c21276037 (diff)
parentce53895a5d24e0ee19fb92f56c17323fb4c9ab27 (diff)
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (417 commits) MAINTAINERS: EB110ATX is not ebsa110 MAINTAINERS: update Eric Miao's email address and status fb: add support of LCD display controller on pxa168/910 (base layer) [ARM] 5552/1: ep93xx get_uart_rate(): use EP93XX_SYSCON_PWRCNT and EP93XX_SYSCON_PWRCN [ARM] pxa/sharpsl_pm: zaurus needs generic pxa suspend/resume routines [ARM] 5544/1: Trust PrimeCell resource sizes [ARM] pxa/sharpsl_pm: cleanup of gpio-related code. [ARM] pxa/sharpsl_pm: drop set_irq_type calls [ARM] pxa/sharpsl_pm: merge pxa-specific code into generic one [ARM] pxa/sharpsl_pm: merge the two sharpsl_pm.c since it's now pxa specific [ARM] sa1100: remove unused collie_pm.c [ARM] pxa: fix the conflicting non-static declarations of global_gpios[] [ARM] 5550/1: Add default configure file for w90p910 platform [ARM] 5549/1: Add clock api for w90p910 platform. [ARM] 5548/1: Add gpio api for w90p910 platform [ARM] 5551/1: Add multi-function pin api for w90p910 platform. [ARM] Make ARM_VIC_NR depend on ARM_VIC [ARM] 5546/1: ARM PL022 SSP/SPI driver v3 ARM: OMAP4: SMP: Update defconfig for OMAP4430 ARM: OMAP4: SMP: Enable SMP support for OMAP4430 ...
Diffstat (limited to 'arch/arm/mach-mx2')
-rw-r--r--arch/arm/mach-mx2/Kconfig21
-rw-r--r--arch/arm/mach-mx2/Makefile4
-rw-r--r--arch/arm/mach-mx2/clock_imx21.c77
-rw-r--r--arch/arm/mach-mx2/generic.c12
-rw-r--r--arch/arm/mach-mx2/mx21ads.c286
-rw-r--r--arch/arm/mach-mx2/mx27ads.c315
-rw-r--r--arch/arm/mach-mx2/mx27lite.c95
-rw-r--r--arch/arm/mach-mx2/mx27pdk.c95
-rw-r--r--arch/arm/mach-mx2/pcm038.c195
-rw-r--r--arch/arm/mach-mx2/pcm970-baseboard.c123
10 files changed, 880 insertions, 343 deletions
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
index 42a788842f49..c77da586b71d 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-mx2/Kconfig
@@ -18,6 +18,13 @@ endchoice
18 18
19comment "MX2 platforms:" 19comment "MX2 platforms:"
20 20
21config MACH_MX21ADS
22 bool "MX21ADS platform"
23 depends on MACH_MX21
24 help
25 Include support for MX21ADS platform. This includes specific
26 configurations for the board and its peripherals.
27
21config MACH_MX27ADS 28config MACH_MX27ADS
22 bool "MX27ADS platform" 29 bool "MX27ADS platform"
23 depends on MACH_MX27 30 depends on MACH_MX27
@@ -46,4 +53,18 @@ config MACH_PCM970_BASEBOARD
46 53
47endchoice 54endchoice
48 55
56config MACH_MX27_3DS
57 bool "MX27PDK platform"
58 depends on MACH_MX27
59 help
60 Include support for MX27PDK platform. This includes specific
61 configurations for the board and its peripherals.
62
63config MACH_MX27LITE
64 bool "LogicPD MX27 LITEKIT platform"
65 depends on MACH_MX27
66 help
67 Include support for MX27 LITEKIT platform. This includes specific
68 configurations for the board and its peripherals.
69
49endif 70endif
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index 950649a91540..b9b1cca4e9bc 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -11,6 +11,10 @@ obj-$(CONFIG_MACH_MX21) += clock_imx21.o
11obj-$(CONFIG_MACH_MX27) += cpu_imx27.o 11obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
12obj-$(CONFIG_MACH_MX27) += clock_imx27.o 12obj-$(CONFIG_MACH_MX27) += clock_imx27.o
13 13
14obj-$(CONFIG_MACH_MX21ADS) += mx21ads.o
14obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o 15obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o
15obj-$(CONFIG_MACH_PCM038) += pcm038.o 16obj-$(CONFIG_MACH_PCM038) += pcm038.o
16obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o 17obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
18obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o
19obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o
20
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
index e4b08ca804ea..0850fb88ec15 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -48,6 +48,25 @@ static void _clk_disable(struct clk *clk)
48 __raw_writel(reg, clk->enable_reg); 48 __raw_writel(reg, clk->enable_reg);
49} 49}
50 50
51static unsigned long _clk_generic_round_rate(struct clk *clk,
52 unsigned long rate,
53 u32 max_divisor)
54{
55 u32 div;
56 unsigned long parent_rate;
57
58 parent_rate = clk_get_rate(clk->parent);
59
60 div = parent_rate / rate;
61 if (parent_rate % rate)
62 div++;
63
64 if (div > max_divisor)
65 div = max_divisor;
66
67 return parent_rate / div;
68}
69
51static int _clk_spll_enable(struct clk *clk) 70static int _clk_spll_enable(struct clk *clk)
52{ 71{
53 u32 reg; 72 u32 reg;
@@ -78,19 +97,7 @@ static void _clk_spll_disable(struct clk *clk)
78static unsigned long _clk_perclkx_round_rate(struct clk *clk, 97static unsigned long _clk_perclkx_round_rate(struct clk *clk,
79 unsigned long rate) 98 unsigned long rate)
80{ 99{
81 u32 div; 100 return _clk_generic_round_rate(clk, rate, 64);
82 unsigned long parent_rate;
83
84 parent_rate = clk_get_rate(clk->parent);
85
86 div = parent_rate / rate;
87 if (parent_rate % rate)
88 div++;
89
90 if (div > 64)
91 div = 64;
92
93 return parent_rate / div;
94} 101}
95 102
96static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) 103static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
@@ -130,6 +137,32 @@ static unsigned long _clk_usb_recalc(struct clk *clk)
130 return parent_rate / (usb_pdf + 1U); 137 return parent_rate / (usb_pdf + 1U);
131} 138}
132 139
140static unsigned long _clk_usb_round_rate(struct clk *clk,
141 unsigned long rate)
142{
143 return _clk_generic_round_rate(clk, rate, 8);
144}
145
146static int _clk_usb_set_rate(struct clk *clk, unsigned long rate)
147{
148 u32 reg;
149 u32 div;
150 unsigned long parent_rate;
151
152 parent_rate = clk_get_rate(clk->parent);
153
154 div = parent_rate / rate;
155 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
156 return -EINVAL;
157 div--;
158
159 reg = CSCR() & ~CCM_CSCR_USB_MASK;
160 reg |= div << CCM_CSCR_USB_OFFSET;
161 __raw_writel(reg, CCM_CSCR);
162
163 return 0;
164}
165
133static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf) 166static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf)
134{ 167{
135 unsigned long parent_rate; 168 unsigned long parent_rate;
@@ -595,11 +628,14 @@ static struct clk csi_clk[] = {
595static struct clk usb_clk[] = { 628static struct clk usb_clk[] = {
596 { 629 {
597 .parent = &spll_clk, 630 .parent = &spll_clk,
631 .secondary = &usb_clk[1],
598 .get_rate = _clk_usb_recalc, 632 .get_rate = _clk_usb_recalc,
599 .enable = _clk_enable, 633 .enable = _clk_enable,
600 .enable_reg = CCM_PCCR_USBOTG_REG, 634 .enable_reg = CCM_PCCR_USBOTG_REG,
601 .enable_shift = CCM_PCCR_USBOTG_OFFSET, 635 .enable_shift = CCM_PCCR_USBOTG_OFFSET,
602 .disable = _clk_disable, 636 .disable = _clk_disable,
637 .round_rate = _clk_usb_round_rate,
638 .set_rate = _clk_usb_set_rate,
603 }, { 639 }, {
604 .parent = &hclk_clk, 640 .parent = &hclk_clk,
605 .enable = _clk_enable, 641 .enable = _clk_enable,
@@ -768,18 +804,7 @@ static struct clk rtc_clk = {
768 804
769static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate) 805static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
770{ 806{
771 u32 div; 807 return _clk_generic_round_rate(clk, rate, 8);
772 unsigned long parent_rate;
773
774 parent_rate = clk_get_rate(clk->parent);
775 div = parent_rate / rate;
776 if (parent_rate % rate)
777 div++;
778
779 if (div > 8)
780 div = 8;
781
782 return parent_rate / div;
783} 808}
784 809
785static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) 810static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
@@ -921,7 +946,7 @@ static struct clk_lookup lookups[] = {
921 _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2]) 946 _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2])
922 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0]) 947 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0])
923 _REGISTER_CLOCK(NULL, "csi", csi_clk[0]) 948 _REGISTER_CLOCK(NULL, "csi", csi_clk[0])
924 _REGISTER_CLOCK(NULL, "usb", usb_clk[0]) 949 _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0])
925 _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0]) 950 _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0])
926 _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1]) 951 _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1])
927 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) 952 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c
index bd51dd04948e..169372f69d8f 100644
--- a/arch/arm/mach-mx2/generic.c
+++ b/arch/arm/mach-mx2/generic.c
@@ -69,7 +69,17 @@ static struct map_desc mxc_io_desc[] __initdata = {
69 * system startup to create static physical to virtual 69 * system startup to create static physical to virtual
70 * memory map for the IO modules. 70 * memory map for the IO modules.
71 */ 71 */
72void __init mxc_map_io(void) 72void __init mx21_map_io(void)
73{ 73{
74 mxc_set_cpu_type(MXC_CPU_MX21);
75
74 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 76 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
75} 77}
78
79void __init mx27_map_io(void)
80{
81 mxc_set_cpu_type(MXC_CPU_MX27);
82
83 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
84}
85
diff --git a/arch/arm/mach-mx2/mx21ads.c b/arch/arm/mach-mx2/mx21ads.c
new file mode 100644
index 000000000000..a5ee461cb405
--- /dev/null
+++ b/arch/arm/mach-mx2/mx21ads.c
@@ -0,0 +1,286 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/platform_device.h>
22#include <linux/mtd/mtd.h>
23#include <linux/mtd/physmap.h>
24#include <linux/gpio.h>
25#include <mach/common.h>
26#include <mach/hardware.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/time.h>
30#include <asm/mach/map.h>
31#include <mach/imx-uart.h>
32#include <mach/imxfb.h>
33#include <mach/iomux.h>
34#include <mach/mxc_nand.h>
35#include <mach/mmc.h>
36#include <mach/board-mx21ads.h>
37
38#include "devices.h"
39
40static unsigned int mx21ads_pins[] = {
41
42 /* CS8900A */
43 (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
44
45 /* UART1 */
46 PE12_PF_UART1_TXD,
47 PE13_PF_UART1_RXD,
48 PE14_PF_UART1_CTS,
49 PE15_PF_UART1_RTS,
50
51 /* UART3 (IrDA) - only TXD and RXD */
52 PE8_PF_UART3_TXD,
53 PE9_PF_UART3_RXD,
54
55 /* UART4 */
56 PB26_AF_UART4_RTS,
57 PB28_AF_UART4_TXD,
58 PB29_AF_UART4_CTS,
59 PB31_AF_UART4_RXD,
60
61 /* LCDC */
62 PA5_PF_LSCLK,
63 PA6_PF_LD0,
64 PA7_PF_LD1,
65 PA8_PF_LD2,
66 PA9_PF_LD3,
67 PA10_PF_LD4,
68 PA11_PF_LD5,
69 PA12_PF_LD6,
70 PA13_PF_LD7,
71 PA14_PF_LD8,
72 PA15_PF_LD9,
73 PA16_PF_LD10,
74 PA17_PF_LD11,
75 PA18_PF_LD12,
76 PA19_PF_LD13,
77 PA20_PF_LD14,
78 PA21_PF_LD15,
79 PA22_PF_LD16,
80 PA24_PF_REV, /* Sharp panel dedicated signal */
81 PA25_PF_CLS, /* Sharp panel dedicated signal */
82 PA26_PF_PS, /* Sharp panel dedicated signal */
83 PA27_PF_SPL_SPR, /* Sharp panel dedicated signal */
84 PA28_PF_HSYNC,
85 PA29_PF_VSYNC,
86 PA30_PF_CONTRAST,
87 PA31_PF_OE_ACD,
88
89 /* MMC/SDHC */
90 PE18_PF_SD1_D0,
91 PE19_PF_SD1_D1,
92 PE20_PF_SD1_D2,
93 PE21_PF_SD1_D3,
94 PE22_PF_SD1_CMD,
95 PE23_PF_SD1_CLK,
96
97 /* NFC */
98 PF0_PF_NRFB,
99 PF1_PF_NFCE,
100 PF2_PF_NFWP,
101 PF3_PF_NFCLE,
102 PF4_PF_NFALE,
103 PF5_PF_NFRE,
104 PF6_PF_NFWE,
105 PF7_PF_NFIO0,
106 PF8_PF_NFIO1,
107 PF9_PF_NFIO2,
108 PF10_PF_NFIO3,
109 PF11_PF_NFIO4,
110 PF12_PF_NFIO5,
111 PF13_PF_NFIO6,
112 PF14_PF_NFIO7,
113};
114
115/* ADS's NOR flash: 2x AM29BDS128HE9VKI on 32-bit bus */
116static struct physmap_flash_data mx21ads_flash_data = {
117 .width = 4,
118};
119
120static struct resource mx21ads_flash_resource = {
121 .start = CS0_BASE_ADDR,
122 .end = CS0_BASE_ADDR + 0x02000000 - 1,
123 .flags = IORESOURCE_MEM,
124};
125
126static struct platform_device mx21ads_nor_mtd_device = {
127 .name = "physmap-flash",
128 .id = 0,
129 .dev = {
130 .platform_data = &mx21ads_flash_data,
131 },
132 .num_resources = 1,
133 .resource = &mx21ads_flash_resource,
134};
135
136static struct imxuart_platform_data uart_pdata = {
137 .flags = IMXUART_HAVE_RTSCTS,
138};
139
140static struct imxuart_platform_data uart_norts_pdata = {
141};
142
143
144static int mx21ads_fb_init(struct platform_device *pdev)
145{
146 u16 tmp;
147
148 tmp = __raw_readw(MX21ADS_IO_REG);
149 tmp |= MX21ADS_IO_LCDON;
150 __raw_writew(tmp, MX21ADS_IO_REG);
151 return 0;
152}
153
154static void mx21ads_fb_exit(struct platform_device *pdev)
155{
156 u16 tmp;
157
158 tmp = __raw_readw(MX21ADS_IO_REG);
159 tmp &= ~MX21ADS_IO_LCDON;
160 __raw_writew(tmp, MX21ADS_IO_REG);
161}
162
163/*
164 * Connected is a portrait Sharp-QVGA display
165 * of type: LQ035Q7DB02
166 */
167static struct imx_fb_platform_data mx21ads_fb_data = {
168 .pixclock = 188679, /* in ps */
169 .xres = 240,
170 .yres = 320,
171
172 .bpp = 16,
173 .hsync_len = 2,
174 .left_margin = 6,
175 .right_margin = 16,
176
177 .vsync_len = 1,
178 .upper_margin = 8,
179 .lower_margin = 10,
180 .fixed_screen_cpu = 0,
181
182 .pcr = 0xFB108BC7,
183 .pwmr = 0x00A901ff,
184 .lscr1 = 0x00120300,
185 .dmacr = 0x00020008,
186
187 .init = mx21ads_fb_init,
188 .exit = mx21ads_fb_exit,
189};
190
191static int mx21ads_sdhc_get_ro(struct device *dev)
192{
193 return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
194}
195
196static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
197 void *data)
198{
199 int ret;
200
201 ret = request_irq(IRQ_GPIOD(25), detect_irq,
202 IRQF_TRIGGER_FALLING, "mmc-detect", data);
203 if (ret)
204 goto out;
205 return 0;
206out:
207 return ret;
208}
209
210static void mx21ads_sdhc_exit(struct device *dev, void *data)
211{
212 free_irq(IRQ_GPIOD(25), data);
213}
214
215static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
216 .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
217 .get_ro = mx21ads_sdhc_get_ro,
218 .init = mx21ads_sdhc_init,
219 .exit = mx21ads_sdhc_exit,
220};
221
222static struct mxc_nand_platform_data mx21ads_nand_board_info = {
223 .width = 1,
224 .hw_ecc = 1,
225};
226
227static struct map_desc mx21ads_io_desc[] __initdata = {
228 /*
229 * Memory-mapped I/O on MX21ADS Base board:
230 * - CS8900A Ethernet controller
231 * - ST16C2552CJ UART
232 * - CPU and Base board version
233 * - Base board I/O register
234 */
235 {
236 .virtual = MX21ADS_MMIO_BASE_ADDR,
237 .pfn = __phys_to_pfn(CS1_BASE_ADDR),
238 .length = MX21ADS_MMIO_SIZE,
239 .type = MT_DEVICE,
240 },
241};
242
243static void __init mx21ads_map_io(void)
244{
245 mx21_map_io();
246 iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
247}
248
249static struct platform_device *platform_devices[] __initdata = {
250 &mx21ads_nor_mtd_device,
251};
252
253static void __init mx21ads_board_init(void)
254{
255 mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
256 "mx21ads");
257
258 mxc_register_device(&mxc_uart_device0, &uart_pdata);
259 mxc_register_device(&mxc_uart_device2, &uart_norts_pdata);
260 mxc_register_device(&mxc_uart_device3, &uart_pdata);
261 mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
262 mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
263 mxc_register_device(&mxc_nand_device, &mx21ads_nand_board_info);
264
265 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
266}
267
268static void __init mx21ads_timer_init(void)
269{
270 mx21_clocks_init(32768, 26000000);
271}
272
273static struct sys_timer mx21ads_timer = {
274 .init = mx21ads_timer_init,
275};
276
277MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
278 /* maintainer: Freescale Semiconductor, Inc. */
279 .phys_io = AIPI_BASE_ADDR,
280 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
281 .boot_params = PHYS_OFFSET + 0x100,
282 .map_io = mx21ads_map_io,
283 .init_irq = mxc_init_irq,
284 .init_machine = mx21ads_board_init,
285 .timer = &mx21ads_timer,
286MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
index 4a3b097adc12..02daddac6995 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -23,6 +23,8 @@
23#include <linux/mtd/map.h> 23#include <linux/mtd/map.h>
24#include <linux/mtd/partitions.h> 24#include <linux/mtd/partitions.h>
25#include <linux/mtd/physmap.h> 25#include <linux/mtd/physmap.h>
26#include <linux/i2c.h>
27#include <linux/irq.h>
26#include <mach/common.h> 28#include <mach/common.h>
27#include <mach/hardware.h> 29#include <mach/hardware.h>
28#include <asm/mach-types.h> 30#include <asm/mach-types.h>
@@ -33,9 +35,117 @@
33#include <mach/imx-uart.h> 35#include <mach/imx-uart.h>
34#include <mach/iomux.h> 36#include <mach/iomux.h>
35#include <mach/board-mx27ads.h> 37#include <mach/board-mx27ads.h>
38#include <mach/mxc_nand.h>
39#include <mach/i2c.h>
40#include <mach/imxfb.h>
41#include <mach/mmc.h>
36 42
37#include "devices.h" 43#include "devices.h"
38 44
45static unsigned int mx27ads_pins[] = {
46 /* UART0 */
47 PE12_PF_UART1_TXD,
48 PE13_PF_UART1_RXD,
49 PE14_PF_UART1_CTS,
50 PE15_PF_UART1_RTS,
51 /* UART1 */
52 PE3_PF_UART2_CTS,
53 PE4_PF_UART2_RTS,
54 PE6_PF_UART2_TXD,
55 PE7_PF_UART2_RXD,
56 /* UART2 */
57 PE8_PF_UART3_TXD,
58 PE9_PF_UART3_RXD,
59 PE10_PF_UART3_CTS,
60 PE11_PF_UART3_RTS,
61 /* UART3 */
62 PB26_AF_UART4_RTS,
63 PB28_AF_UART4_TXD,
64 PB29_AF_UART4_CTS,
65 PB31_AF_UART4_RXD,
66 /* UART4 */
67 PB18_AF_UART5_TXD,
68 PB19_AF_UART5_RXD,
69 PB20_AF_UART5_CTS,
70 PB21_AF_UART5_RTS,
71 /* UART5 */
72 PB10_AF_UART6_TXD,
73 PB12_AF_UART6_CTS,
74 PB11_AF_UART6_RXD,
75 PB13_AF_UART6_RTS,
76 /* FEC */
77 PD0_AIN_FEC_TXD0,
78 PD1_AIN_FEC_TXD1,
79 PD2_AIN_FEC_TXD2,
80 PD3_AIN_FEC_TXD3,
81 PD4_AOUT_FEC_RX_ER,
82 PD5_AOUT_FEC_RXD1,
83 PD6_AOUT_FEC_RXD2,
84 PD7_AOUT_FEC_RXD3,
85 PD8_AF_FEC_MDIO,
86 PD9_AIN_FEC_MDC,
87 PD10_AOUT_FEC_CRS,
88 PD11_AOUT_FEC_TX_CLK,
89 PD12_AOUT_FEC_RXD0,
90 PD13_AOUT_FEC_RX_DV,
91 PD14_AOUT_FEC_RX_CLK,
92 PD15_AOUT_FEC_COL,
93 PD16_AIN_FEC_TX_ER,
94 PF23_AIN_FEC_TX_EN,
95 /* I2C2 */
96 PC5_PF_I2C2_SDA,
97 PC6_PF_I2C2_SCL,
98 /* FB */
99 PA5_PF_LSCLK,
100 PA6_PF_LD0,
101 PA7_PF_LD1,
102 PA8_PF_LD2,
103 PA9_PF_LD3,
104 PA10_PF_LD4,
105 PA11_PF_LD5,
106 PA12_PF_LD6,
107 PA13_PF_LD7,
108 PA14_PF_LD8,
109 PA15_PF_LD9,
110 PA16_PF_LD10,
111 PA17_PF_LD11,
112 PA18_PF_LD12,
113 PA19_PF_LD13,
114 PA20_PF_LD14,
115 PA21_PF_LD15,
116 PA22_PF_LD16,
117 PA23_PF_LD17,
118 PA24_PF_REV,
119 PA25_PF_CLS,
120 PA26_PF_PS,
121 PA27_PF_SPL_SPR,
122 PA28_PF_HSYNC,
123 PA29_PF_VSYNC,
124 PA30_PF_CONTRAST,
125 PA31_PF_OE_ACD,
126 /* OWIRE */
127 PE16_AF_OWIRE,
128 /* SDHC1*/
129 PE18_PF_SD1_D0,
130 PE19_PF_SD1_D1,
131 PE20_PF_SD1_D2,
132 PE21_PF_SD1_D3,
133 PE22_PF_SD1_CMD,
134 PE23_PF_SD1_CLK,
135 /* SDHC2*/
136 PB4_PF_SD2_D0,
137 PB5_PF_SD2_D1,
138 PB6_PF_SD2_D2,
139 PB7_PF_SD2_D3,
140 PB8_PF_SD2_CMD,
141 PB9_PF_SD2_CLK,
142};
143
144static struct mxc_nand_platform_data mx27ads_nand_board_info = {
145 .width = 1,
146 .hw_ecc = 1,
147};
148
39/* ADS's NOR flash */ 149/* ADS's NOR flash */
40static struct physmap_flash_data mx27ads_flash_data = { 150static struct physmap_flash_data mx27ads_flash_data = {
41 .width = 2, 151 .width = 2,
@@ -58,189 +168,113 @@ static struct platform_device mx27ads_nor_mtd_device = {
58 .resource = &mx27ads_flash_resource, 168 .resource = &mx27ads_flash_resource,
59}; 169};
60 170
61static int mxc_uart0_pins[] = { 171static struct imxi2c_platform_data mx27ads_i2c_data = {
62 PE12_PF_UART1_TXD, 172 .bitrate = 100000,
63 PE13_PF_UART1_RXD,
64 PE14_PF_UART1_CTS,
65 PE15_PF_UART1_RTS
66}; 173};
67 174
68static int uart_mxc_port0_init(struct platform_device *pdev) 175static struct i2c_board_info mx27ads_i2c_devices[] = {
69{
70 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
71 ARRAY_SIZE(mxc_uart0_pins), "UART0");
72}
73
74static int uart_mxc_port0_exit(struct platform_device *pdev)
75{
76 mxc_gpio_release_multiple_pins(mxc_uart0_pins,
77 ARRAY_SIZE(mxc_uart0_pins));
78 return 0;
79}
80
81static int mxc_uart1_pins[] = {
82 PE3_PF_UART2_CTS,
83 PE4_PF_UART2_RTS,
84 PE6_PF_UART2_TXD,
85 PE7_PF_UART2_RXD
86}; 176};
87 177
88static int uart_mxc_port1_init(struct platform_device *pdev) 178void lcd_power(int on)
89{ 179{
90 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, 180 if (on)
91 ARRAY_SIZE(mxc_uart1_pins), "UART1"); 181 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
182 else
183 __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
92} 184}
93 185
94static int uart_mxc_port1_exit(struct platform_device *pdev) 186static struct imx_fb_platform_data mx27ads_fb_data = {
95{ 187 .pixclock = 188679,
96 mxc_gpio_release_multiple_pins(mxc_uart1_pins, 188 .xres = 240,
97 ARRAY_SIZE(mxc_uart1_pins)); 189 .yres = 320,
98 return 0; 190
99} 191 .bpp = 16,
100 192 .hsync_len = 1,
101static int mxc_uart2_pins[] = { 193 .left_margin = 9,
102 PE8_PF_UART3_TXD, 194 .right_margin = 16,
103 PE9_PF_UART3_RXD, 195
104 PE10_PF_UART3_CTS, 196 .vsync_len = 1,
105 PE11_PF_UART3_RTS 197 .upper_margin = 7,
198 .lower_margin = 9,
199 .fixed_screen_cpu = 0,
200
201 /*
202 * - HSYNC active high
203 * - VSYNC active high
204 * - clk notenabled while idle
205 * - clock inverted
206 * - data not inverted
207 * - data enable low active
208 * - enable sharp mode
209 */
210 .pcr = 0xFB008BC0,
211 .pwmr = 0x00A903FF,
212 .lscr1 = 0x00120300,
213 .dmacr = 0x00020010,
214
215 .lcd_power = lcd_power,
106}; 216};
107 217
108static int uart_mxc_port2_init(struct platform_device *pdev) 218static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
219 void *data)
109{ 220{
110 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, 221 return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
111 ARRAY_SIZE(mxc_uart2_pins), "UART2"); 222 "sdhc1-card-detect", data);
112} 223}
113 224
114static int uart_mxc_port2_exit(struct platform_device *pdev) 225static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
226 void *data)
115{ 227{
116 mxc_gpio_release_multiple_pins(mxc_uart2_pins, 228 return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
117 ARRAY_SIZE(mxc_uart2_pins)); 229 "sdhc2-card-detect", data);
118 return 0;
119} 230}
120 231
121static int mxc_uart3_pins[] = { 232static void mx27ads_sdhc1_exit(struct device *dev, void *data)
122 PB26_AF_UART4_RTS,
123 PB28_AF_UART4_TXD,
124 PB29_AF_UART4_CTS,
125 PB31_AF_UART4_RXD
126};
127
128static int uart_mxc_port3_init(struct platform_device *pdev)
129{ 233{
130 return mxc_gpio_setup_multiple_pins(mxc_uart3_pins, 234 free_irq(IRQ_GPIOE(21), data);
131 ARRAY_SIZE(mxc_uart3_pins), "UART3");
132} 235}
133 236
134static int uart_mxc_port3_exit(struct platform_device *pdev) 237static void mx27ads_sdhc2_exit(struct device *dev, void *data)
135{ 238{
136 mxc_gpio_release_multiple_pins(mxc_uart3_pins, 239 free_irq(IRQ_GPIOB(7), data);
137 ARRAY_SIZE(mxc_uart3_pins));
138 return 0;
139} 240}
140 241
141static int mxc_uart4_pins[] = { 242static struct imxmmc_platform_data sdhc1_pdata = {
142 PB18_AF_UART5_TXD, 243 .init = mx27ads_sdhc1_init,
143 PB19_AF_UART5_RXD, 244 .exit = mx27ads_sdhc1_exit,
144 PB20_AF_UART5_CTS,
145 PB21_AF_UART5_RTS
146}; 245};
147 246
148static int uart_mxc_port4_init(struct platform_device *pdev) 247static struct imxmmc_platform_data sdhc2_pdata = {
149{ 248 .init = mx27ads_sdhc2_init,
150 return mxc_gpio_setup_multiple_pins(mxc_uart4_pins, 249 .exit = mx27ads_sdhc2_exit,
151 ARRAY_SIZE(mxc_uart4_pins), "UART4");
152}
153
154static int uart_mxc_port4_exit(struct platform_device *pdev)
155{
156 mxc_gpio_release_multiple_pins(mxc_uart4_pins,
157 ARRAY_SIZE(mxc_uart4_pins));
158 return 0;
159}
160
161static int mxc_uart5_pins[] = {
162 PB10_AF_UART6_TXD,
163 PB12_AF_UART6_CTS,
164 PB11_AF_UART6_RXD,
165 PB13_AF_UART6_RTS
166}; 250};
167 251
168static int uart_mxc_port5_init(struct platform_device *pdev)
169{
170 return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
171 ARRAY_SIZE(mxc_uart5_pins), "UART5");
172}
173
174static int uart_mxc_port5_exit(struct platform_device *pdev)
175{
176 mxc_gpio_release_multiple_pins(mxc_uart5_pins,
177 ARRAY_SIZE(mxc_uart5_pins));
178 return 0;
179}
180
181static struct platform_device *platform_devices[] __initdata = { 252static struct platform_device *platform_devices[] __initdata = {
182 &mx27ads_nor_mtd_device, 253 &mx27ads_nor_mtd_device,
183 &mxc_fec_device, 254 &mxc_fec_device,
255 &mxc_w1_master_device,
184}; 256};
185 257
186static int mxc_fec_pins[] = {
187 PD0_AIN_FEC_TXD0,
188 PD1_AIN_FEC_TXD1,
189 PD2_AIN_FEC_TXD2,
190 PD3_AIN_FEC_TXD3,
191 PD4_AOUT_FEC_RX_ER,
192 PD5_AOUT_FEC_RXD1,
193 PD6_AOUT_FEC_RXD2,
194 PD7_AOUT_FEC_RXD3,
195 PD8_AF_FEC_MDIO,
196 PD9_AIN_FEC_MDC,
197 PD10_AOUT_FEC_CRS,
198 PD11_AOUT_FEC_TX_CLK,
199 PD12_AOUT_FEC_RXD0,
200 PD13_AOUT_FEC_RX_DV,
201 PD14_AOUT_FEC_RX_CLK,
202 PD15_AOUT_FEC_COL,
203 PD16_AIN_FEC_TX_ER,
204 PF23_AIN_FEC_TX_EN
205};
206
207static void gpio_fec_active(void)
208{
209 mxc_gpio_setup_multiple_pins(mxc_fec_pins,
210 ARRAY_SIZE(mxc_fec_pins), "FEC");
211}
212
213static struct imxuart_platform_data uart_pdata[] = { 258static struct imxuart_platform_data uart_pdata[] = {
214 { 259 {
215 .init = uart_mxc_port0_init,
216 .exit = uart_mxc_port0_exit,
217 .flags = IMXUART_HAVE_RTSCTS, 260 .flags = IMXUART_HAVE_RTSCTS,
218 }, { 261 }, {
219 .init = uart_mxc_port1_init,
220 .exit = uart_mxc_port1_exit,
221 .flags = IMXUART_HAVE_RTSCTS, 262 .flags = IMXUART_HAVE_RTSCTS,
222 }, { 263 }, {
223 .init = uart_mxc_port2_init,
224 .exit = uart_mxc_port2_exit,
225 .flags = IMXUART_HAVE_RTSCTS, 264 .flags = IMXUART_HAVE_RTSCTS,
226 }, { 265 }, {
227 .init = uart_mxc_port3_init,
228 .exit = uart_mxc_port3_exit,
229 .flags = IMXUART_HAVE_RTSCTS, 266 .flags = IMXUART_HAVE_RTSCTS,
230 }, { 267 }, {
231 .init = uart_mxc_port4_init,
232 .exit = uart_mxc_port4_exit,
233 .flags = IMXUART_HAVE_RTSCTS, 268 .flags = IMXUART_HAVE_RTSCTS,
234 }, { 269 }, {
235 .init = uart_mxc_port5_init,
236 .exit = uart_mxc_port5_exit,
237 .flags = IMXUART_HAVE_RTSCTS, 270 .flags = IMXUART_HAVE_RTSCTS,
238 }, 271 },
239}; 272};
240 273
241static void __init mx27ads_board_init(void) 274static void __init mx27ads_board_init(void)
242{ 275{
243 gpio_fec_active(); 276 mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
277 "mx27ads");
244 278
245 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); 279 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
246 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); 280 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
@@ -248,6 +282,15 @@ static void __init mx27ads_board_init(void)
248 mxc_register_device(&mxc_uart_device3, &uart_pdata[3]); 282 mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
249 mxc_register_device(&mxc_uart_device4, &uart_pdata[4]); 283 mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
250 mxc_register_device(&mxc_uart_device5, &uart_pdata[5]); 284 mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
285 mxc_register_device(&mxc_nand_device, &mx27ads_nand_board_info);
286
287 /* only the i2c master 1 is used on this CPU card */
288 i2c_register_board_info(1, mx27ads_i2c_devices,
289 ARRAY_SIZE(mx27ads_i2c_devices));
290 mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data);
291 mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
292 mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
293 mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
251 294
252 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 295 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
253} 296}
@@ -277,7 +320,7 @@ static struct map_desc mx27ads_io_desc[] __initdata = {
277 320
278static void __init mx27ads_map_io(void) 321static void __init mx27ads_map_io(void)
279{ 322{
280 mxc_map_io(); 323 mx27_map_io();
281 iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); 324 iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
282} 325}
283 326
diff --git a/arch/arm/mach-mx2/mx27lite.c b/arch/arm/mach-mx2/mx27lite.c
new file mode 100644
index 000000000000..3ae11cb8c04b
--- /dev/null
+++ b/arch/arm/mach-mx2/mx27lite.c
@@ -0,0 +1,95 @@
1/*
2 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 * Copyright 2009 Daniel Schaeffer (daniel.schaeffer@timesys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/platform_device.h>
22#include <linux/gpio.h>
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25#include <asm/mach/time.h>
26#include <asm/mach/map.h>
27#include <mach/hardware.h>
28#include <mach/common.h>
29#include <mach/imx-uart.h>
30#include <mach/iomux.h>
31#include <mach/board-mx27lite.h>
32
33#include "devices.h"
34
35static unsigned int mx27lite_pins[] = {
36 /* UART1 */
37 PE12_PF_UART1_TXD,
38 PE13_PF_UART1_RXD,
39 PE14_PF_UART1_CTS,
40 PE15_PF_UART1_RTS,
41 /* FEC */
42 PD0_AIN_FEC_TXD0,
43 PD1_AIN_FEC_TXD1,
44 PD2_AIN_FEC_TXD2,
45 PD3_AIN_FEC_TXD3,
46 PD4_AOUT_FEC_RX_ER,
47 PD5_AOUT_FEC_RXD1,
48 PD6_AOUT_FEC_RXD2,
49 PD7_AOUT_FEC_RXD3,
50 PD8_AF_FEC_MDIO,
51 PD9_AIN_FEC_MDC,
52 PD10_AOUT_FEC_CRS,
53 PD11_AOUT_FEC_TX_CLK,
54 PD12_AOUT_FEC_RXD0,
55 PD13_AOUT_FEC_RX_DV,
56 PD14_AOUT_FEC_RX_CLK,
57 PD15_AOUT_FEC_COL,
58 PD16_AIN_FEC_TX_ER,
59 PF23_AIN_FEC_TX_EN,
60};
61
62static struct imxuart_platform_data uart_pdata = {
63 .flags = IMXUART_HAVE_RTSCTS,
64};
65
66static struct platform_device *platform_devices[] __initdata = {
67 &mxc_fec_device,
68};
69
70static void __init mx27lite_init(void)
71{
72 mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
73 "imx27lite");
74 mxc_register_device(&mxc_uart_device0, &uart_pdata);
75 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
76}
77
78static void __init mx27lite_timer_init(void)
79{
80 mx27_clocks_init(26000000);
81}
82
83static struct sys_timer mx27lite_timer = {
84 .init = mx27lite_timer_init,
85};
86
87MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
88 .phys_io = AIPI_BASE_ADDR,
89 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
90 .boot_params = PHYS_OFFSET + 0x100,
91 .map_io = mx27_map_io,
92 .init_irq = mxc_init_irq,
93 .init_machine = mx27lite_init,
94 .timer = &mx27lite_timer,
95MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27pdk.c b/arch/arm/mach-mx2/mx27pdk.c
new file mode 100644
index 000000000000..1d9238c7a6c3
--- /dev/null
+++ b/arch/arm/mach-mx2/mx27pdk.c
@@ -0,0 +1,95 @@
1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/platform_device.h>
22#include <linux/gpio.h>
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25#include <asm/mach/time.h>
26#include <mach/hardware.h>
27#include <mach/common.h>
28#include <mach/imx-uart.h>
29#include <mach/iomux.h>
30#include <mach/board-mx27pdk.h>
31
32#include "devices.h"
33
34static unsigned int mx27pdk_pins[] = {
35 /* UART1 */
36 PE12_PF_UART1_TXD,
37 PE13_PF_UART1_RXD,
38 PE14_PF_UART1_CTS,
39 PE15_PF_UART1_RTS,
40 /* FEC */
41 PD0_AIN_FEC_TXD0,
42 PD1_AIN_FEC_TXD1,
43 PD2_AIN_FEC_TXD2,
44 PD3_AIN_FEC_TXD3,
45 PD4_AOUT_FEC_RX_ER,
46 PD5_AOUT_FEC_RXD1,
47 PD6_AOUT_FEC_RXD2,
48 PD7_AOUT_FEC_RXD3,
49 PD8_AF_FEC_MDIO,
50 PD9_AIN_FEC_MDC,
51 PD10_AOUT_FEC_CRS,
52 PD11_AOUT_FEC_TX_CLK,
53 PD12_AOUT_FEC_RXD0,
54 PD13_AOUT_FEC_RX_DV,
55 PD14_AOUT_FEC_RX_CLK,
56 PD15_AOUT_FEC_COL,
57 PD16_AIN_FEC_TX_ER,
58 PF23_AIN_FEC_TX_EN,
59};
60
61static struct imxuart_platform_data uart_pdata = {
62 .flags = IMXUART_HAVE_RTSCTS,
63};
64
65static struct platform_device *platform_devices[] __initdata = {
66 &mxc_fec_device,
67};
68
69static void __init mx27pdk_init(void)
70{
71 mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
72 "mx27pdk");
73 mxc_register_device(&mxc_uart_device0, &uart_pdata);
74 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
75}
76
77static void __init mx27pdk_timer_init(void)
78{
79 mx27_clocks_init(26000000);
80}
81
82static struct sys_timer mx27pdk_timer = {
83 .init = mx27pdk_timer_init,
84};
85
86MACHINE_START(MX27_3DS, "Freescale MX27PDK")
87 /* maintainer: Freescale Semiconductor, Inc. */
88 .phys_io = AIPI_BASE_ADDR,
89 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
90 .boot_params = PHYS_OFFSET + 0x100,
91 .map_io = mx27_map_io,
92 .init_irq = mxc_init_irq,
93 .init_machine = mx27pdk_init,
94 .timer = &mx27pdk_timer,
95MACHINE_END
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
index aa4eaa61d1b5..a4628d004343 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -17,28 +17,84 @@
17 * MA 02110-1301, USA. 17 * MA 02110-1301, USA.
18 */ 18 */
19 19
20#include <linux/platform_device.h>
21#include <linux/mtd/physmap.h>
22#include <linux/mtd/plat-ram.h>
23#include <linux/io.h>
24#include <linux/i2c.h> 20#include <linux/i2c.h>
25#include <linux/i2c/at24.h> 21#include <linux/i2c/at24.h>
22#include <linux/io.h>
23#include <linux/mtd/plat-ram.h>
24#include <linux/mtd/physmap.h>
25#include <linux/platform_device.h>
26 26
27#include <asm/mach/arch.h>
28#include <asm/mach-types.h> 27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/time.h>
30
31#include <mach/board-pcm038.h>
29#include <mach/common.h> 32#include <mach/common.h>
30#include <mach/hardware.h> 33#include <mach/hardware.h>
31#include <mach/iomux.h>
32#ifdef CONFIG_I2C_IMX
33#include <mach/i2c.h> 34#include <mach/i2c.h>
34#endif 35#include <mach/iomux.h>
35#include <asm/mach/time.h>
36#include <mach/imx-uart.h> 36#include <mach/imx-uart.h>
37#include <mach/board-pcm038.h>
38#include <mach/mxc_nand.h> 37#include <mach/mxc_nand.h>
39 38
40#include "devices.h" 39#include "devices.h"
41 40
41static int pcm038_pins[] = {
42 /* UART1 */
43 PE12_PF_UART1_TXD,
44 PE13_PF_UART1_RXD,
45 PE14_PF_UART1_CTS,
46 PE15_PF_UART1_RTS,
47 /* UART2 */
48 PE3_PF_UART2_CTS,
49 PE4_PF_UART2_RTS,
50 PE6_PF_UART2_TXD,
51 PE7_PF_UART2_RXD,
52 /* UART3 */
53 PE8_PF_UART3_TXD,
54 PE9_PF_UART3_RXD,
55 PE10_PF_UART3_CTS,
56 PE11_PF_UART3_RTS,
57 /* FEC */
58 PD0_AIN_FEC_TXD0,
59 PD1_AIN_FEC_TXD1,
60 PD2_AIN_FEC_TXD2,
61 PD3_AIN_FEC_TXD3,
62 PD4_AOUT_FEC_RX_ER,
63 PD5_AOUT_FEC_RXD1,
64 PD6_AOUT_FEC_RXD2,
65 PD7_AOUT_FEC_RXD3,
66 PD8_AF_FEC_MDIO,
67 PD9_AIN_FEC_MDC,
68 PD10_AOUT_FEC_CRS,
69 PD11_AOUT_FEC_TX_CLK,
70 PD12_AOUT_FEC_RXD0,
71 PD13_AOUT_FEC_RX_DV,
72 PD14_AOUT_FEC_RX_CLK,
73 PD15_AOUT_FEC_COL,
74 PD16_AIN_FEC_TX_ER,
75 PF23_AIN_FEC_TX_EN,
76 /* I2C2 */
77 PC5_PF_I2C2_SDA,
78 PC6_PF_I2C2_SCL,
79 /* SPI1 */
80 PD25_PF_CSPI1_RDY,
81 PD27_PF_CSPI1_SS1,
82 PD28_PF_CSPI1_SS0,
83 PD29_PF_CSPI1_SCLK,
84 PD30_PF_CSPI1_MISO,
85 PD31_PF_CSPI1_MOSI,
86 /* SSI1 */
87 PC20_PF_SSI1_FS,
88 PC21_PF_SSI1_RXD,
89 PC22_PF_SSI1_TXD,
90 PC23_PF_SSI1_CLK,
91 /* SSI4 */
92 PC16_PF_SSI4_FS,
93 PC17_PF_SSI4_RXD,
94 PC18_PF_SSI4_TXD,
95 PC19_PF_SSI4_CLK,
96};
97
42/* 98/*
43 * Phytec's PCM038 comes with 2MiB battery buffered SRAM, 99 * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
44 * 16 bit width 100 * 16 bit width
@@ -88,107 +144,16 @@ static struct platform_device pcm038_nor_mtd_device = {
88 .resource = &pcm038_flash_resource, 144 .resource = &pcm038_flash_resource,
89}; 145};
90 146
91static int mxc_uart0_pins[] = {
92 PE12_PF_UART1_TXD,
93 PE13_PF_UART1_RXD,
94 PE14_PF_UART1_CTS,
95 PE15_PF_UART1_RTS
96};
97
98static int uart_mxc_port0_init(struct platform_device *pdev)
99{
100 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
101 ARRAY_SIZE(mxc_uart0_pins), "UART0");
102}
103
104static int uart_mxc_port0_exit(struct platform_device *pdev)
105{
106 mxc_gpio_release_multiple_pins(mxc_uart0_pins,
107 ARRAY_SIZE(mxc_uart0_pins));
108 return 0;
109}
110
111static int mxc_uart1_pins[] = {
112 PE3_PF_UART2_CTS,
113 PE4_PF_UART2_RTS,
114 PE6_PF_UART2_TXD,
115 PE7_PF_UART2_RXD
116};
117
118static int uart_mxc_port1_init(struct platform_device *pdev)
119{
120 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
121 ARRAY_SIZE(mxc_uart1_pins), "UART1");
122}
123
124static int uart_mxc_port1_exit(struct platform_device *pdev)
125{
126 mxc_gpio_release_multiple_pins(mxc_uart1_pins,
127 ARRAY_SIZE(mxc_uart1_pins));
128 return 0;
129}
130
131static int mxc_uart2_pins[] = { PE8_PF_UART3_TXD,
132 PE9_PF_UART3_RXD,
133 PE10_PF_UART3_CTS,
134 PE11_PF_UART3_RTS };
135
136static int uart_mxc_port2_init(struct platform_device *pdev)
137{
138 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
139 ARRAY_SIZE(mxc_uart2_pins), "UART2");
140}
141
142static int uart_mxc_port2_exit(struct platform_device *pdev)
143{
144 mxc_gpio_release_multiple_pins(mxc_uart2_pins,
145 ARRAY_SIZE(mxc_uart2_pins));
146 return 0;
147}
148
149static struct imxuart_platform_data uart_pdata[] = { 147static struct imxuart_platform_data uart_pdata[] = {
150 { 148 {
151 .init = uart_mxc_port0_init,
152 .exit = uart_mxc_port0_exit,
153 .flags = IMXUART_HAVE_RTSCTS, 149 .flags = IMXUART_HAVE_RTSCTS,
154 }, { 150 }, {
155 .init = uart_mxc_port1_init,
156 .exit = uart_mxc_port1_exit,
157 .flags = IMXUART_HAVE_RTSCTS, 151 .flags = IMXUART_HAVE_RTSCTS,
158 }, { 152 }, {
159 .init = uart_mxc_port2_init,
160 .exit = uart_mxc_port2_exit,
161 .flags = IMXUART_HAVE_RTSCTS, 153 .flags = IMXUART_HAVE_RTSCTS,
162 }, 154 },
163}; 155};
164 156
165static int mxc_fec_pins[] = {
166 PD0_AIN_FEC_TXD0,
167 PD1_AIN_FEC_TXD1,
168 PD2_AIN_FEC_TXD2,
169 PD3_AIN_FEC_TXD3,
170 PD4_AOUT_FEC_RX_ER,
171 PD5_AOUT_FEC_RXD1,
172 PD6_AOUT_FEC_RXD2,
173 PD7_AOUT_FEC_RXD3,
174 PD8_AF_FEC_MDIO,
175 PD9_AIN_FEC_MDC,
176 PD10_AOUT_FEC_CRS,
177 PD11_AOUT_FEC_TX_CLK,
178 PD12_AOUT_FEC_RXD0,
179 PD13_AOUT_FEC_RX_DV,
180 PD14_AOUT_FEC_RX_CLK,
181 PD15_AOUT_FEC_COL,
182 PD16_AIN_FEC_TX_ER,
183 PF23_AIN_FEC_TX_EN
184};
185
186static void gpio_fec_active(void)
187{
188 mxc_gpio_setup_multiple_pins(mxc_fec_pins,
189 ARRAY_SIZE(mxc_fec_pins), "FEC");
190}
191
192static struct mxc_nand_platform_data pcm038_nand_board_info = { 157static struct mxc_nand_platform_data pcm038_nand_board_info = {
193 .width = 1, 158 .width = 1,
194 .hw_ecc = 1, 159 .hw_ecc = 1,
@@ -210,27 +175,8 @@ static void __init pcm038_init_sram(void)
210 __raw_writel(0x22220a00, CSCR_A(1)); 175 __raw_writel(0x22220a00, CSCR_A(1));
211} 176}
212 177
213#ifdef CONFIG_I2C_IMX
214static int mxc_i2c1_pins[] = {
215 PC5_PF_I2C2_SDA,
216 PC6_PF_I2C2_SCL
217};
218
219static int pcm038_i2c_1_init(struct device *dev)
220{
221 return mxc_gpio_setup_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins),
222 "I2C1");
223}
224
225static void pcm038_i2c_1_exit(struct device *dev)
226{
227 mxc_gpio_release_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins));
228}
229
230static struct imxi2c_platform_data pcm038_i2c_1_data = { 178static struct imxi2c_platform_data pcm038_i2c_1_data = {
231 .bitrate = 100000, 179 .bitrate = 100000,
232 .init = pcm038_i2c_1_init,
233 .exit = pcm038_i2c_1_exit,
234}; 180};
235 181
236static struct at24_platform_data board_eeprom = { 182static struct at24_platform_data board_eeprom = {
@@ -253,11 +199,12 @@ static struct i2c_board_info pcm038_i2c_devices[] = {
253 .type = "lm75" 199 .type = "lm75"
254 } 200 }
255}; 201};
256#endif
257 202
258static void __init pcm038_init(void) 203static void __init pcm038_init(void)
259{ 204{
260 gpio_fec_active(); 205 mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
206 "PCM038");
207
261 pcm038_init_sram(); 208 pcm038_init_sram();
262 209
263 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); 210 mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
@@ -267,13 +214,11 @@ static void __init pcm038_init(void)
267 mxc_gpio_mode(PE16_AF_OWIRE); 214 mxc_gpio_mode(PE16_AF_OWIRE);
268 mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); 215 mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info);
269 216
270#ifdef CONFIG_I2C_IMX
271 /* only the i2c master 1 is used on this CPU card */ 217 /* only the i2c master 1 is used on this CPU card */
272 i2c_register_board_info(1, pcm038_i2c_devices, 218 i2c_register_board_info(1, pcm038_i2c_devices,
273 ARRAY_SIZE(pcm038_i2c_devices)); 219 ARRAY_SIZE(pcm038_i2c_devices));
274 220
275 mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data); 221 mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
276#endif
277 222
278 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 223 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
279 224
@@ -295,7 +240,7 @@ MACHINE_START(PCM038, "phyCORE-i.MX27")
295 .phys_io = AIPI_BASE_ADDR, 240 .phys_io = AIPI_BASE_ADDR,
296 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, 241 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
297 .boot_params = PHYS_OFFSET + 0x100, 242 .boot_params = PHYS_OFFSET + 0x100,
298 .map_io = mxc_map_io, 243 .map_io = mx27_map_io,
299 .init_irq = mxc_init_irq, 244 .init_irq = mxc_init_irq,
300 .init_machine = pcm038_init, 245 .init_machine = pcm038_init,
301 .timer = &pcm038_timer, 246 .timer = &pcm038_timer,
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
index bf4e520bc1bc..6a3acaf57dd4 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -16,71 +16,107 @@
16 * MA 02110-1301, USA. 16 * MA 02110-1301, USA.
17 */ 17 */
18 18
19#include <linux/platform_device.h>
20#include <linux/gpio.h> 19#include <linux/gpio.h>
21#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/platform_device.h>
22 22
23#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
24 24
25#include <mach/hardware.h>
26#include <mach/common.h> 25#include <mach/common.h>
27#include <mach/mmc.h>
28#include <mach/imxfb.h>
29#include <mach/iomux.h> 26#include <mach/iomux.h>
27#include <mach/imxfb.h>
28#include <mach/hardware.h>
29#include <mach/mmc.h>
30 30
31#include "devices.h" 31#include "devices.h"
32 32
33static int pcm970_sdhc2_get_ro(struct device *dev) 33static int pcm970_pins[] = {
34{ 34 /* SDHC */
35 return gpio_get_value(GPIO_PORTC + 28);
36}
37
38static int pcm970_sdhc2_pins[] = {
39 PB4_PF_SD2_D0, 35 PB4_PF_SD2_D0,
40 PB5_PF_SD2_D1, 36 PB5_PF_SD2_D1,
41 PB6_PF_SD2_D2, 37 PB6_PF_SD2_D2,
42 PB7_PF_SD2_D3, 38 PB7_PF_SD2_D3,
43 PB8_PF_SD2_CMD, 39 PB8_PF_SD2_CMD,
44 PB9_PF_SD2_CLK, 40 PB9_PF_SD2_CLK,
41 GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN, /* card detect */
42 /* display */
43 PA5_PF_LSCLK,
44 PA6_PF_LD0,
45 PA7_PF_LD1,
46 PA8_PF_LD2,
47 PA9_PF_LD3,
48 PA10_PF_LD4,
49 PA11_PF_LD5,
50 PA12_PF_LD6,
51 PA13_PF_LD7,
52 PA14_PF_LD8,
53 PA15_PF_LD9,
54 PA16_PF_LD10,
55 PA17_PF_LD11,
56 PA18_PF_LD12,
57 PA19_PF_LD13,
58 PA20_PF_LD14,
59 PA21_PF_LD15,
60 PA22_PF_LD16,
61 PA23_PF_LD17,
62 PA24_PF_REV,
63 PA25_PF_CLS,
64 PA26_PF_PS,
65 PA27_PF_SPL_SPR,
66 PA28_PF_HSYNC,
67 PA29_PF_VSYNC,
68 PA30_PF_CONTRAST,
69 PA31_PF_OE_ACD,
70 /*
71 * it seems the data line misses a pullup, so we must enable
72 * the internal pullup as a local workaround
73 */
74 PD17_PF_I2C_DATA | GPIO_PUEN,
75 PD18_PF_I2C_CLK,
76 /* Camera */
77 PB10_PF_CSI_D0,
78 PB11_PF_CSI_D1,
79 PB12_PF_CSI_D2,
80 PB13_PF_CSI_D3,
81 PB14_PF_CSI_D4,
82 PB15_PF_CSI_MCLK,
83 PB16_PF_CSI_PIXCLK,
84 PB17_PF_CSI_D5,
85 PB18_PF_CSI_D6,
86 PB19_PF_CSI_D7,
87 PB20_PF_CSI_VSYNC,
88 PB21_PF_CSI_HSYNC,
45}; 89};
46 90
91static int pcm970_sdhc2_get_ro(struct device *dev)
92{
93 return gpio_get_value(GPIO_PORTC + 28);
94}
95
47static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data) 96static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data)
48{ 97{
49 int ret; 98 int ret;
50 99
51 ret = mxc_gpio_setup_multiple_pins(pcm970_sdhc2_pins, 100 ret = request_irq(IRQ_GPIOC(29), detect_irq, IRQF_TRIGGER_FALLING,
52 ARRAY_SIZE(pcm970_sdhc2_pins), "sdhc2");
53 if(ret)
54 return ret;
55
56 ret = request_irq(IRQ_GPIOC(29), detect_irq, 0,
57 "imx-mmc-detect", data); 101 "imx-mmc-detect", data);
58 if (ret) 102 if (ret)
59 goto out_release_gpio; 103 return ret;
60
61 set_irq_type(IRQ_GPIOC(29), IRQF_TRIGGER_FALLING);
62 104
63 ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro"); 105 ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
64 if (ret) 106 if (ret) {
65 goto out_release_gpio; 107 free_irq(IRQ_GPIOC(29), data);
108 return ret;
109 }
66 110
67 mxc_gpio_mode((GPIO_PORTC | 28) | GPIO_GPIO | GPIO_IN);
68 gpio_direction_input(GPIO_PORTC + 28); 111 gpio_direction_input(GPIO_PORTC + 28);
69 112
70 return 0; 113 return 0;
71
72out_release_gpio:
73 mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins,
74 ARRAY_SIZE(pcm970_sdhc2_pins));
75 return ret;
76} 114}
77 115
78static void pcm970_sdhc2_exit(struct device *dev, void *data) 116static void pcm970_sdhc2_exit(struct device *dev, void *data)
79{ 117{
80 free_irq(IRQ_GPIOC(29), data); 118 free_irq(IRQ_GPIOC(29), data);
81 gpio_free(GPIO_PORTC + 28); 119 gpio_free(GPIO_PORTC + 28);
82 mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins,
83 ARRAY_SIZE(pcm970_sdhc2_pins));
84} 120}
85 121
86static struct imxmmc_platform_data sdhc_pdata = { 122static struct imxmmc_platform_data sdhc_pdata = {
@@ -89,29 +125,6 @@ static struct imxmmc_platform_data sdhc_pdata = {
89 .exit = pcm970_sdhc2_exit, 125 .exit = pcm970_sdhc2_exit,
90}; 126};
91 127
92static int mxc_fb_pins[] = {
93 PA5_PF_LSCLK, PA6_PF_LD0, PA7_PF_LD1, PA8_PF_LD2,
94 PA9_PF_LD3, PA10_PF_LD4, PA11_PF_LD5, PA12_PF_LD6,
95 PA13_PF_LD7, PA14_PF_LD8, PA15_PF_LD9, PA16_PF_LD10,
96 PA17_PF_LD11, PA18_PF_LD12, PA19_PF_LD13, PA20_PF_LD14,
97 PA21_PF_LD15, PA22_PF_LD16, PA23_PF_LD17, PA24_PF_REV,
98 PA25_PF_CLS, PA26_PF_PS, PA27_PF_SPL_SPR, PA28_PF_HSYNC,
99 PA29_PF_VSYNC, PA30_PF_CONTRAST, PA31_PF_OE_ACD
100};
101
102static int pcm038_fb_init(struct platform_device *pdev)
103{
104 return mxc_gpio_setup_multiple_pins(mxc_fb_pins,
105 ARRAY_SIZE(mxc_fb_pins), "FB");
106}
107
108static int pcm038_fb_exit(struct platform_device *pdev)
109{
110 mxc_gpio_release_multiple_pins(mxc_fb_pins, ARRAY_SIZE(mxc_fb_pins));
111
112 return 0;
113}
114
115/* 128/*
116 * Connected is a portrait Sharp-QVGA display 129 * Connected is a portrait Sharp-QVGA display
117 * of type: LQ035Q7DH06 130 * of type: LQ035Q7DH06
@@ -144,9 +157,6 @@ static struct imx_fb_platform_data pcm038_fb_data = {
144 .pwmr = 0x00A903FF, 157 .pwmr = 0x00A903FF,
145 .lscr1 = 0x00120300, 158 .lscr1 = 0x00120300,
146 .dmacr = 0x00020010, 159 .dmacr = 0x00020010,
147
148 .init = pcm038_fb_init,
149 .exit = pcm038_fb_exit,
150}; 160};
151 161
152/* 162/*
@@ -157,6 +167,9 @@ static struct imx_fb_platform_data pcm038_fb_data = {
157 */ 167 */
158void __init pcm970_baseboard_init(void) 168void __init pcm970_baseboard_init(void)
159{ 169{
170 mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
171 "PCM970");
172
160 mxc_register_device(&mxc_fb_device, &pcm038_fb_data); 173 mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
161 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); 174 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
162} 175}