Merge tag 'late-mvebu-rebased' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC mvebu platform changes from Olof Johansson:
 "This series contains changes for the Marvell EBU platforms (mvebu,
  orion, kirkwood, dove) that were not part of the first set of pull
  requests because of dependencies on the MMC tree, and being submitted
  a little late.

  Notable changes are:

   - More devices get moved out of board files into device tree
     descriptions.  The remaining devices listed in there have patches
     that will get sent for 3.10, after which we can remove a lot of the
     board files entirely.  We are doing the pinctrl and mmc drivers
     here, ethernet and PCI still remain.

   - SMP support for mvebu is improved with support for the local
     interrupt controller.

   - The Guruplug board file gets replaced with a DT description.

  Unfortunately, the dependency on the MMC tree turned out to be a much
  larger problem than expected, when the MMC maintainer rebased the
  patches in his tree that all of the patches in this branch are based
  on, which caused merge conflicts between the new and old versions of
  those patches.

  To work around the merge conflicts, this branch rebases all patches on
  top of the respective MMC patches that did get merged into 3.9.  The
  patches are all identical to the versions that were part of
  linux-next, but have a new commit date."

* tag 'late-mvebu-rebased' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (90 commits)
  arm: mvebu: enable the SD card slot on Armada 370 Reference Design board
  ARM: kirkwood: topkick: init mvsdio via DT
  ARM: kirkwood: nsa310: convert to pinctrl
  ARM: Kirkwood: topkick: Enable i2c bus.
  ARM: kirkwood: topkick: convert to pinctrl
  ARM: dove: convert serial DT nodes to clocks property
  arm: mvebu: Add SPI flash on Armada 370 DB board
  arm: mvebu: Add SPI flash on Armada XP-DB board
  arm: mvebu: Add SPI flash on Armada XP-GP board
  arm: mvebu: Add support for SPI controller in Armada 370/XP
  clocksource: update and move armada-370-xp-timer documentation to timer directory
  arm: mvebu: update DT to support local timers
  ARM: Dove: convert usb host controller to DT
  arm: mvebu: Enable USB controllers on Armada 370/XP boards
  arm: mvebu: Add support for USB host controllers in Armada 370/XP
  arm: mvebu: add button for OpenBlocks AX3-4
  ARM: Kirkwood: Convert NS2 to gpio-poweroff.
  ARM: Kirkwood: Convert NSA310 I2C to device tree
  ARM: Kirkwood: Convert NSA310 to use gpio-poweroff driver
  ARM: Kirkwood: Convert NSA310 to DT based regulators.
  ...

1 files changed, 83 insertions, 4 deletions

diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
index 8e3fb082c3c6..274ff58271de 100644
--- a/arch/arm/mach-mvebu/irq-armada-370-xp.c
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -34,6 +34,7 @@
 #define ARMADA_370_XP_INT_CONTROL               (0x00)
 #define ARMADA_370_XP_INT_SET_ENABLE_OFFS       (0x30)
 #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS     (0x34)
+#define ARMADA_370_XP_INT_SOURCE_CTL(irq)       (0x100 + irq*4)
 
 #define ARMADA_370_XP_CPU_INTACK_OFFS           (0x44)
 
@@ -41,28 +42,90 @@
 #define ARMADA_370_XP_IN_DRBEL_MSK_OFFS          (0xc)
 #define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS        (0x8)
 
+#define ARMADA_370_XP_MAX_PER_CPU_IRQS          (28)
+
 #define ACTIVE_DOORBELLS                        (8)
 
+static DEFINE_RAW_SPINLOCK(irq_controller_lock);
+
 static void __iomem *per_cpu_int_base;
 static void __iomem *main_int_base;
 static struct irq_domain *armada_370_xp_mpic_domain;
 
+/*
+ * In SMP mode:
+ * For shared global interrupts, mask/unmask global enable bit
+ * For CPU interrtups, mask/unmask the calling CPU's bit
+ */
 static void armada_370_xp_irq_mask(struct irq_data *d)
 {
+#ifdef CONFIG_SMP
+        irq_hw_number_t hwirq = irqd_to_hwirq(d);
+
+        if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
+                writel(hwirq, main_int_base +
+                                ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
+        else
+                writel(hwirq, per_cpu_int_base +
+                                ARMADA_370_XP_INT_SET_MASK_OFFS);
+#else
         writel(irqd_to_hwirq(d),
                per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
+#endif
 }
 
 static void armada_370_xp_irq_unmask(struct irq_data *d)
 {
+#ifdef CONFIG_SMP
+        irq_hw_number_t hwirq = irqd_to_hwirq(d);
+
+        if (hwirq > ARMADA_370_XP_MAX_PER_CPU_IRQS)
+                writel(hwirq, main_int_base +
+                                ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+        else
+                writel(hwirq, per_cpu_int_base +
+                                ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+#else
         writel(irqd_to_hwirq(d),
                per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+#endif
 }
 
 #ifdef CONFIG_SMP
 static int armada_xp_set_affinity(struct irq_data *d,
                                   const struct cpumask *mask_val, bool force)
 {
+        unsigned long reg;
+        unsigned long new_mask = 0;
+        unsigned long online_mask = 0;
+        unsigned long count = 0;
+        irq_hw_number_t hwirq = irqd_to_hwirq(d);
+        int cpu;
+
+        for_each_cpu(cpu, mask_val) {
+                new_mask |= 1 << cpu_logical_map(cpu);
+                count++;
+        }
+
+        /*
+         * Forbid mutlicore interrupt affinity
+         * This is required since the MPIC HW doesn't limit
+         * several CPUs from acknowledging the same interrupt.
+         */
+        if (count > 1)
+                return -EINVAL;
+
+        for_each_cpu(cpu, cpu_online_mask)
+                online_mask |= 1 << cpu_logical_map(cpu);
+
+        raw_spin_lock(&irq_controller_lock);
+
+        reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
+        reg = (reg & (~online_mask)) | new_mask;
+        writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
+
+        raw_spin_unlock(&irq_controller_lock);
+
         return 0;
 }
 #endif
@@ -82,10 +145,17 @@ static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
 {
         armada_370_xp_irq_mask(irq_get_irq_data(virq));
         writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
-
-        irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
-                                 handle_level_irq);
         irq_set_status_flags(virq, IRQ_LEVEL);
+
+        if (hw < ARMADA_370_XP_MAX_PER_CPU_IRQS) {
+                irq_set_percpu_devid(virq);
+                irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
+                                        handle_percpu_devid_irq);
+
+        } else {
+                irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
+                                        handle_level_irq);
+        }
         set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
 
         return 0;
@@ -155,6 +225,15 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
 
 #ifdef CONFIG_SMP
         armada_xp_mpic_smp_cpu_init();
+
+        /*
+         * Set the default affinity from all CPUs to the boot cpu.
+         * This is required since the MPIC doesn't limit several CPUs
+         * from acknowledging the same interrupt.
+         */
+        cpumask_clear(irq_default_affinity);
+        cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
+
 #endif
 
         return 0;
@@ -173,7 +252,7 @@ asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
                 if (irqnr > 1022)
                         break;
 
-                if (irqnr >= 8) {
+                if (irqnr > 0) {
                         irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
                                         irqnr);
                         handle_IRQ(irqnr, regs);