ARM: Orion: Consolidate the address map setup

Compile tested on Dove, orion5x, mv78xx0. Boot tested on Kirkwood.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Michael Walle <michael@walle.cc>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Nicolas Pitre <nico@fluxnic.net>

1 files changed, 21 insertions, 81 deletions

diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 311d5b0e9bc7..6b14555e5766 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -12,12 +12,12 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
+#include <plat/addr-map.h>
 #include "common.h"
 
 /*
  * Generic Address Decode Windows bit settings
  */
-#define TARGET_DDR              0
 #define TARGET_DEV_BUS          1
 #define TARGET_PCIE0            4
 #define TARGET_PCIE1            8
@@ -32,21 +32,10 @@
 #define ATTR_PCIE_MEM(l)        (0xf8 & ~(0x10 << (l)))
 
 /*
- * Helpers to get DDR bank info
- */
-#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
-#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
-
-/*
  * CPU Address Decode Windows registers
  */
 #define WIN0_OFF(n)             (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
 #define WIN8_OFF(n)             (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
-#define WIN_CTRL_OFF            0x0000
-#define WIN_BASE_OFF            0x0004
-#define WIN_REMAP_LO_OFF        0x0008
-#define WIN_REMAP_HI_OFF        0x000c
-
 
 struct mbus_dram_target_info mv78xx0_mbus_dram_info;
 
@@ -63,94 +52,45 @@ static void __init __iomem *win_cfg_base(int win)
         return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
 }
 
-static int __init cpu_win_can_remap(int win)
-{
-        if (win < 8)
-                return 1;
-
-        return 0;
-}
-
-static void __init setup_cpu_win(int win, u32 base, u32 size,
-                                 u8 target, u8 attr, int remap)
-{
-        void __iomem *addr = win_cfg_base(win);
-        u32 ctrl;
-
-        base &= 0xffff0000;
-        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
-
-        writel(base, addr + WIN_BASE_OFF);
-        writel(ctrl, addr + WIN_CTRL_OFF);
-        if (cpu_win_can_remap(win)) {
-                if (remap < 0)
-                        remap = base;
-
-                writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
-                writel(0, addr + WIN_REMAP_HI_OFF);
-        }
-}
+/*
+ * Description of the windows needed by the platform code
+ */
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 14,
+        .remappable_wins = 8,
+        .win_cfg_base = win_cfg_base,
+};
 
 void __init mv78xx0_setup_cpu_mbus(void)
 {
-        void __iomem *addr;
-        int i;
-        int cs;
-
         /*
-         * First, disable and clear windows.
+         * Disable, clear and configure windows.
          */
-        for (i = 0; i < 14; i++) {
-                addr = win_cfg_base(i);
-
-                writel(0, addr + WIN_BASE_OFF);
-                writel(0, addr + WIN_CTRL_OFF);
-                if (cpu_win_can_remap(i)) {
-                        writel(0, addr + WIN_REMAP_LO_OFF);
-                        writel(0, addr + WIN_REMAP_HI_OFF);
-                }
-        }
+        orion_config_wins(&addr_map_cfg, NULL);
 
         /*
          * Setup MBUS dram target info.
          */
-        mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
-
         if (mv78xx0_core_index() == 0)
-                addr = (void __iomem *)DDR_WINDOW_CPU0_BASE;
+                orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                            &mv78xx0_mbus_dram_info,
+                                            DDR_WINDOW_CPU0_BASE);
         else
-                addr = (void __iomem *)DDR_WINDOW_CPU1_BASE;
-
-        for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
-                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
-
-                /*
-                 * Chip select enabled?
-                 */
-                if (size & 1) {
-                        struct mbus_dram_window *w;
-
-                        w = &mv78xx0_mbus_dram_info.cs[cs++];
-                        w->cs_index = i;
-                        w->mbus_attr = 0xf & ~(1 << i);
-                        w->base = base & 0xffff0000;
-                        w->size = (size | 0x0000ffff) + 1;
-                }
-        }
-        mv78xx0_mbus_dram_info.num_cs = cs;
+                orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                            &mv78xx0_mbus_dram_info,
+                                            DDR_WINDOW_CPU1_BASE);
 }
 
 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
                                       int maj, int min)
 {
-        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
-                      ATTR_PCIE_IO(min), -1);
+        orion_setup_cpu_win(&addr_map_cfg, window, base, size,
+                            TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
 }
 
 void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
                                        int maj, int min)
 {
-        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
-                      ATTR_PCIE_MEM(min), -1);
+        orion_setup_cpu_win(&addr_map_cfg, window, base, size,
+                            TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
 }