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authorStepan Moskovchenko <stepanm@codeaurora.org>2010-08-24 21:31:10 -0400
committerDaniel Walker <dwalker@codeaurora.org>2010-10-08 18:12:50 -0400
commit0720d1f052dc1576396a39b327da6e60082c4efa (patch)
tree43fb8566eda2cab0741df1cee489f2979d685678 /arch/arm/mach-msm
parent69b7f6ff855e32ec353475ce7b7246d293816078 (diff)
msm: Add MSM IOMMU support
Add support for the IOMMUs found on the upcoming Qualcomm MSM8x60 chips. These IOMMUs allow virtualization of the address space used by most of the multimedia cores on these chips. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Diffstat (limited to 'arch/arm/mach-msm')
-rw-r--r--arch/arm/mach-msm/include/mach/iommu.h103
-rw-r--r--arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h1871
-rw-r--r--arch/arm/mach-msm/iommu.c597
3 files changed, 2571 insertions, 0 deletions
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
new file mode 100644
index 000000000000..218ef5732a24
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/iommu.h
@@ -0,0 +1,103 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#ifndef MSM_IOMMU_H
19#define MSM_IOMMU_H
20
21#include <linux/interrupt.h>
22
23/* Maximum number of Machine IDs that we are allowing to be mapped to the same
24 * context bank. The number of MIDs mapped to the same CB does not affect
25 * performance, but there is a practical limit on how many distinct MIDs may
26 * be present. These mappings are typically determined at design time and are
27 * not expected to change at run time.
28 */
29#define MAX_NUM_MIDS 16
30
31/**
32 * struct msm_iommu_dev - a single IOMMU hardware instance
33 * name Human-readable name given to this IOMMU HW instance
34 * clk_rate Rate to set for this IOMMU's clock, if applicable to this
35 * particular IOMMU. 0 means don't set a rate.
36 * -1 means it is an AXI clock with no valid rate
37 *
38 */
39struct msm_iommu_dev {
40 const char *name;
41 int clk_rate;
42};
43
44/**
45 * struct msm_iommu_ctx_dev - an IOMMU context bank instance
46 * name Human-readable name given to this context bank
47 * num Index of this context bank within the hardware
48 * mids List of Machine IDs that are to be mapped into this context
49 * bank, terminated by -1. The MID is a set of signals on the
50 * AXI bus that identifies the function associated with a specific
51 * memory request. (See ARM spec).
52 */
53struct msm_iommu_ctx_dev {
54 const char *name;
55 int num;
56 int mids[MAX_NUM_MIDS];
57};
58
59
60/**
61 * struct msm_iommu_drvdata - A single IOMMU hardware instance
62 * @base: IOMMU config port base address (VA)
63 * @irq: Interrupt number
64 *
65 * A msm_iommu_drvdata holds the global driver data about a single piece
66 * of an IOMMU hardware instance.
67 */
68struct msm_iommu_drvdata {
69 void __iomem *base;
70 int irq;
71};
72
73/**
74 * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
75 * @num: Hardware context number of this context
76 * @pdev: Platform device associated wit this HW instance
77 * @attached_elm: List element for domains to track which devices are
78 * attached to them
79 *
80 * A msm_iommu_ctx_drvdata holds the driver data for a single context bank
81 * within each IOMMU hardware instance
82 */
83struct msm_iommu_ctx_drvdata {
84 int num;
85 struct platform_device *pdev;
86 struct list_head attached_elm;
87};
88
89/*
90 * Look up an IOMMU context device by its context name. NULL if none found.
91 * Useful for testing and drivers that do not yet fully have IOMMU stuff in
92 * their platform devices.
93 */
94struct device *msm_iommu_get_ctx(const char *ctx_name);
95
96/*
97 * Interrupt handler for the IOMMU context fault interrupt. Hooking the
98 * interrupt is not supported in the API yet, but this will print an error
99 * message and dump useful IOMMU registers.
100 */
101irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
102
103#endif
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
new file mode 100644
index 000000000000..f9386d3a2f77
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
@@ -0,0 +1,1871 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#ifndef __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
19#define __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
20
21#define CTX_SHIFT 12
22
23#define GET_GLOBAL_REG(reg, base) (readl((base) + (reg)))
24#define GET_CTX_REG(reg, base, ctx) \
25 (readl((base) + (reg) + ((ctx) << CTX_SHIFT)))
26
27#define SET_GLOBAL_REG(reg, base, val) writel((val), ((base) + (reg)))
28
29#define SET_CTX_REG(reg, base, ctx, val) \
30 writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT)))
31
32/* Wrappers for numbered registers */
33#define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v))
34#define GET_GLOBAL_REG_N(b, n, r) GET_GLOBAL_REG(b, ((r) + (n << 2)))
35
36/* Field wrappers */
37#define GET_GLOBAL_FIELD(b, r, F) GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT)
38#define GET_CONTEXT_FIELD(b, c, r, F) \
39 GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT)
40
41#define SET_GLOBAL_FIELD(b, r, F, v) \
42 SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
43#define SET_CONTEXT_FIELD(b, c, r, F, v) \
44 SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
45
46#define GET_FIELD(addr, mask, shift) ((readl(addr) >> (shift)) & (mask))
47
48#define SET_FIELD(addr, mask, shift, v) \
49do { \
50 int t = readl(addr); \
51 writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
52} while (0)
53
54
55#define NUM_FL_PTE 4096
56#define NUM_SL_PTE 256
57
58/* First-level page table bits */
59#define FL_BASE_MASK 0xFFFFFC00
60#define FL_TYPE_TABLE (1 << 0)
61#define FL_TYPE_SECT (2 << 0)
62#define FL_SUPERSECTION (1 << 18)
63#define FL_AP_WRITE (1 << 10)
64#define FL_AP_READ (1 << 11)
65#define FL_SHARED (1 << 16)
66#define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20)
67
68/* Second-level page table bits */
69#define SL_BASE_MASK_LARGE 0xFFFF0000
70#define SL_BASE_MASK_SMALL 0xFFFFF000
71#define SL_TYPE_LARGE (1 << 0)
72#define SL_TYPE_SMALL (2 << 0)
73#define SL_AP0 (1 << 4)
74#define SL_AP1 (2 << 4)
75#define SL_SHARED (1 << 10)
76#define SL_OFFSET(va) (((va) & 0xFF000) >> 12)
77
78/* Global register setters / getters */
79#define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v))
80#define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v))
81#define SET_TLBRSW(b, v) SET_GLOBAL_REG(TLBRSW, (b), (v))
82#define SET_TLBTR0(b, v) SET_GLOBAL_REG(TLBTR0, (b), (v))
83#define SET_TLBTR1(b, v) SET_GLOBAL_REG(TLBTR1, (b), (v))
84#define SET_TLBTR2(b, v) SET_GLOBAL_REG(TLBTR2, (b), (v))
85#define SET_TESTBUSCR(b, v) SET_GLOBAL_REG(TESTBUSCR, (b), (v))
86#define SET_GLOBAL_TLBIALL(b, v) SET_GLOBAL_REG(GLOBAL_TLBIALL, (b), (v))
87#define SET_TLBIVMID(b, v) SET_GLOBAL_REG(TLBIVMID, (b), (v))
88#define SET_CR(b, v) SET_GLOBAL_REG(CR, (b), (v))
89#define SET_EAR(b, v) SET_GLOBAL_REG(EAR, (b), (v))
90#define SET_ESR(b, v) SET_GLOBAL_REG(ESR, (b), (v))
91#define SET_ESRRESTORE(b, v) SET_GLOBAL_REG(ESRRESTORE, (b), (v))
92#define SET_ESYNR0(b, v) SET_GLOBAL_REG(ESYNR0, (b), (v))
93#define SET_ESYNR1(b, v) SET_GLOBAL_REG(ESYNR1, (b), (v))
94#define SET_RPU_ACR(b, v) SET_GLOBAL_REG(RPU_ACR, (b), (v))
95
96#define GET_M2VCBR_N(b, N) GET_GLOBAL_REG_N(M2VCBR_N, N, (b))
97#define GET_CBACR_N(b, N) GET_GLOBAL_REG_N(CBACR_N, N, (b))
98#define GET_TLBTR0(b) GET_GLOBAL_REG(TLBTR0, (b))
99#define GET_TLBTR1(b) GET_GLOBAL_REG(TLBTR1, (b))
100#define GET_TLBTR2(b) GET_GLOBAL_REG(TLBTR2, (b))
101#define GET_TESTBUSCR(b) GET_GLOBAL_REG(TESTBUSCR, (b))
102#define GET_GLOBAL_TLBIALL(b) GET_GLOBAL_REG(GLOBAL_TLBIALL, (b))
103#define GET_TLBIVMID(b) GET_GLOBAL_REG(TLBIVMID, (b))
104#define GET_CR(b) GET_GLOBAL_REG(CR, (b))
105#define GET_EAR(b) GET_GLOBAL_REG(EAR, (b))
106#define GET_ESR(b) GET_GLOBAL_REG(ESR, (b))
107#define GET_ESRRESTORE(b) GET_GLOBAL_REG(ESRRESTORE, (b))
108#define GET_ESYNR0(b) GET_GLOBAL_REG(ESYNR0, (b))
109#define GET_ESYNR1(b) GET_GLOBAL_REG(ESYNR1, (b))
110#define GET_REV(b) GET_GLOBAL_REG(REV, (b))
111#define GET_IDR(b) GET_GLOBAL_REG(IDR, (b))
112#define GET_RPU_ACR(b) GET_GLOBAL_REG(RPU_ACR, (b))
113
114
115/* Context register setters/getters */
116#define SET_SCTLR(b, c, v) SET_CTX_REG(SCTLR, (b), (c), (v))
117#define SET_ACTLR(b, c, v) SET_CTX_REG(ACTLR, (b), (c), (v))
118#define SET_CONTEXTIDR(b, c, v) SET_CTX_REG(CONTEXTIDR, (b), (c), (v))
119#define SET_TTBR0(b, c, v) SET_CTX_REG(TTBR0, (b), (c), (v))
120#define SET_TTBR1(b, c, v) SET_CTX_REG(TTBR1, (b), (c), (v))
121#define SET_TTBCR(b, c, v) SET_CTX_REG(TTBCR, (b), (c), (v))
122#define SET_PAR(b, c, v) SET_CTX_REG(PAR, (b), (c), (v))
123#define SET_FSR(b, c, v) SET_CTX_REG(FSR, (b), (c), (v))
124#define SET_FSRRESTORE(b, c, v) SET_CTX_REG(FSRRESTORE, (b), (c), (v))
125#define SET_FAR(b, c, v) SET_CTX_REG(FAR, (b), (c), (v))
126#define SET_FSYNR0(b, c, v) SET_CTX_REG(FSYNR0, (b), (c), (v))
127#define SET_FSYNR1(b, c, v) SET_CTX_REG(FSYNR1, (b), (c), (v))
128#define SET_PRRR(b, c, v) SET_CTX_REG(PRRR, (b), (c), (v))
129#define SET_NMRR(b, c, v) SET_CTX_REG(NMRR, (b), (c), (v))
130#define SET_TLBLKCR(b, c, v) SET_CTX_REG(TLBLCKR, (b), (c), (v))
131#define SET_V2PSR(b, c, v) SET_CTX_REG(V2PSR, (b), (c), (v))
132#define SET_TLBFLPTER(b, c, v) SET_CTX_REG(TLBFLPTER, (b), (c), (v))
133#define SET_TLBSLPTER(b, c, v) SET_CTX_REG(TLBSLPTER, (b), (c), (v))
134#define SET_BFBCR(b, c, v) SET_CTX_REG(BFBCR, (b), (c), (v))
135#define SET_CTX_TLBIALL(b, c, v) SET_CTX_REG(CTX_TLBIALL, (b), (c), (v))
136#define SET_TLBIASID(b, c, v) SET_CTX_REG(TLBIASID, (b), (c), (v))
137#define SET_TLBIVA(b, c, v) SET_CTX_REG(TLBIVA, (b), (c), (v))
138#define SET_TLBIVAA(b, c, v) SET_CTX_REG(TLBIVAA, (b), (c), (v))
139#define SET_V2PPR(b, c, v) SET_CTX_REG(V2PPR, (b), (c), (v))
140#define SET_V2PPW(b, c, v) SET_CTX_REG(V2PPW, (b), (c), (v))
141#define SET_V2PUR(b, c, v) SET_CTX_REG(V2PUR, (b), (c), (v))
142#define SET_V2PUW(b, c, v) SET_CTX_REG(V2PUW, (b), (c), (v))
143#define SET_RESUME(b, c, v) SET_CTX_REG(RESUME, (b), (c), (v))
144
145#define GET_SCTLR(b, c) GET_CTX_REG(SCTLR, (b), (c))
146#define GET_ACTLR(b, c) GET_CTX_REG(ACTLR, (b), (c))
147#define GET_CONTEXTIDR(b, c) GET_CTX_REG(CONTEXTIDR, (b), (c))
148#define GET_TTBR0(b, c) GET_CTX_REG(TTBR0, (b), (c))
149#define GET_TTBR1(b, c) GET_CTX_REG(TTBR1, (b), (c))
150#define GET_TTBCR(b, c) GET_CTX_REG(TTBCR, (b), (c))
151#define GET_PAR(b, c) GET_CTX_REG(PAR, (b), (c))
152#define GET_FSR(b, c) GET_CTX_REG(FSR, (b), (c))
153#define GET_FSRRESTORE(b, c) GET_CTX_REG(FSRRESTORE, (b), (c))
154#define GET_FAR(b, c) GET_CTX_REG(FAR, (b), (c))
155#define GET_FSYNR0(b, c) GET_CTX_REG(FSYNR0, (b), (c))
156#define GET_FSYNR1(b, c) GET_CTX_REG(FSYNR1, (b), (c))
157#define GET_PRRR(b, c) GET_CTX_REG(PRRR, (b), (c))
158#define GET_NMRR(b, c) GET_CTX_REG(NMRR, (b), (c))
159#define GET_TLBLCKR(b, c) GET_CTX_REG(TLBLCKR, (b), (c))
160#define GET_V2PSR(b, c) GET_CTX_REG(V2PSR, (b), (c))
161#define GET_TLBFLPTER(b, c) GET_CTX_REG(TLBFLPTER, (b), (c))
162#define GET_TLBSLPTER(b, c) GET_CTX_REG(TLBSLPTER, (b), (c))
163#define GET_BFBCR(b, c) GET_CTX_REG(BFBCR, (b), (c))
164#define GET_CTX_TLBIALL(b, c) GET_CTX_REG(CTX_TLBIALL, (b), (c))
165#define GET_TLBIASID(b, c) GET_CTX_REG(TLBIASID, (b), (c))
166#define GET_TLBIVA(b, c) GET_CTX_REG(TLBIVA, (b), (c))
167#define GET_TLBIVAA(b, c) GET_CTX_REG(TLBIVAA, (b), (c))
168#define GET_V2PPR(b, c) GET_CTX_REG(V2PPR, (b), (c))
169#define GET_V2PPW(b, c) GET_CTX_REG(V2PPW, (b), (c))
170#define GET_V2PUR(b, c) GET_CTX_REG(V2PUR, (b), (c))
171#define GET_V2PUW(b, c) GET_CTX_REG(V2PUW, (b), (c))
172#define GET_RESUME(b, c) GET_CTX_REG(RESUME, (b), (c))
173
174
175/* Global field setters / getters */
176/* Global Field Setters: */
177/* CBACR_N */
178#define SET_RWVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID, v)
179#define SET_RWE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE, v)
180#define SET_RWGE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE, v)
181#define SET_CBVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID, v)
182#define SET_IRPTNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX, v)
183
184
185/* M2VCBR_N */
186#define SET_VMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID, v)
187#define SET_CBNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX, v)
188#define SET_BYPASSD(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD, v)
189#define SET_BPRCOSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH, v)
190#define SET_BPRCISH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH, v)
191#define SET_BPRCNSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH, v)
192#define SET_BPSHCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG, v)
193#define SET_NSCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG, v)
194#define SET_BPMTCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG, v)
195#define SET_BPMEMTYPE(b, n, v) \
196 SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE, v)
197
198
199/* CR */
200#define SET_RPUE(b, v) SET_GLOBAL_FIELD(b, CR, RPUE, v)
201#define SET_RPUERE(b, v) SET_GLOBAL_FIELD(b, CR, RPUERE, v)
202#define SET_RPUEIE(b, v) SET_GLOBAL_FIELD(b, CR, RPUEIE, v)
203#define SET_DCDEE(b, v) SET_GLOBAL_FIELD(b, CR, DCDEE, v)
204#define SET_CLIENTPD(b, v) SET_GLOBAL_FIELD(b, CR, CLIENTPD, v)
205#define SET_STALLD(b, v) SET_GLOBAL_FIELD(b, CR, STALLD, v)
206#define SET_TLBLKCRWE(b, v) SET_GLOBAL_FIELD(b, CR, TLBLKCRWE, v)
207#define SET_CR_TLBIALLCFG(b, v) SET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG, v)
208#define SET_TLBIVMIDCFG(b, v) SET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG, v)
209#define SET_CR_HUME(b, v) SET_GLOBAL_FIELD(b, CR, CR_HUME, v)
210
211
212/* ESR */
213#define SET_CFG(b, v) SET_GLOBAL_FIELD(b, ESR, CFG, v)
214#define SET_BYPASS(b, v) SET_GLOBAL_FIELD(b, ESR, BYPASS, v)
215#define SET_ESR_MULTI(b, v) SET_GLOBAL_FIELD(b, ESR, ESR_MULTI, v)
216
217
218/* ESYNR0 */
219#define SET_ESYNR0_AMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID, v)
220#define SET_ESYNR0_APID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID, v)
221#define SET_ESYNR0_ABID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID, v)
222#define SET_ESYNR0_AVMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID, v)
223#define SET_ESYNR0_ATID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID, v)
224
225
226/* ESYNR1 */
227#define SET_ESYNR1_AMEMTYPE(b, v) \
228 SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE, v)
229#define SET_ESYNR1_ASHARED(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED, v)
230#define SET_ESYNR1_AINNERSHARED(b, v) \
231 SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED, v)
232#define SET_ESYNR1_APRIV(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV, v)
233#define SET_ESYNR1_APROTNS(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS, v)
234#define SET_ESYNR1_AINST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST, v)
235#define SET_ESYNR1_AWRITE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE, v)
236#define SET_ESYNR1_ABURST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST, v)
237#define SET_ESYNR1_ALEN(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN, v)
238#define SET_ESYNR1_ASIZE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE, v)
239#define SET_ESYNR1_ALOCK(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK, v)
240#define SET_ESYNR1_AOOO(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO, v)
241#define SET_ESYNR1_AFULL(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL, v)
242#define SET_ESYNR1_AC(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC, v)
243#define SET_ESYNR1_DCD(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD, v)
244
245
246/* TESTBUSCR */
247#define SET_TBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBE, v)
248#define SET_SPDMBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE, v)
249#define SET_WGSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL, v)
250#define SET_TBLSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL, v)
251#define SET_TBHSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL, v)
252#define SET_SPDM0SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL, v)
253#define SET_SPDM1SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL, v)
254#define SET_SPDM2SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL, v)
255#define SET_SPDM3SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL, v)
256
257
258/* TLBIVMID */
259#define SET_TLBIVMID_VMID(b, v) SET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID, v)
260
261
262/* TLBRSW */
263#define SET_TLBRSW_INDEX(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBRSW_INDEX, v)
264#define SET_TLBBFBS(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBBFBS, v)
265
266
267/* TLBTR0 */
268#define SET_PR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PR, v)
269#define SET_PW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PW, v)
270#define SET_UR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UR, v)
271#define SET_UW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UW, v)
272#define SET_XN(b, v) SET_GLOBAL_FIELD(b, TLBTR0, XN, v)
273#define SET_NSDESC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, NSDESC, v)
274#define SET_ISH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, ISH, v)
275#define SET_SH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, SH, v)
276#define SET_MT(b, v) SET_GLOBAL_FIELD(b, TLBTR0, MT, v)
277#define SET_DPSIZR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZR, v)
278#define SET_DPSIZC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZC, v)
279
280
281/* TLBTR1 */
282#define SET_TLBTR1_VMID(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID, v)
283#define SET_TLBTR1_PA(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA, v)
284
285
286/* TLBTR2 */
287#define SET_TLBTR2_ASID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID, v)
288#define SET_TLBTR2_V(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V, v)
289#define SET_TLBTR2_NSTID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID, v)
290#define SET_TLBTR2_NV(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV, v)
291#define SET_TLBTR2_VA(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA, v)
292
293
294/* Global Field Getters */
295/* CBACR_N */
296#define GET_RWVMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID)
297#define GET_RWE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE)
298#define GET_RWGE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE)
299#define GET_CBVMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID)
300#define GET_IRPTNDX(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX)
301
302
303/* M2VCBR_N */
304#define GET_VMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID)
305#define GET_CBNDX(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX)
306#define GET_BYPASSD(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD)
307#define GET_BPRCOSH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH)
308#define GET_BPRCISH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH)
309#define GET_BPRCNSH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH)
310#define GET_BPSHCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG)
311#define GET_NSCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG)
312#define GET_BPMTCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG)
313#define GET_BPMEMTYPE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE)
314
315
316/* CR */
317#define GET_RPUE(b) GET_GLOBAL_FIELD(b, CR, RPUE)
318#define GET_RPUERE(b) GET_GLOBAL_FIELD(b, CR, RPUERE)
319#define GET_RPUEIE(b) GET_GLOBAL_FIELD(b, CR, RPUEIE)
320#define GET_DCDEE(b) GET_GLOBAL_FIELD(b, CR, DCDEE)
321#define GET_CLIENTPD(b) GET_GLOBAL_FIELD(b, CR, CLIENTPD)
322#define GET_STALLD(b) GET_GLOBAL_FIELD(b, CR, STALLD)
323#define GET_TLBLKCRWE(b) GET_GLOBAL_FIELD(b, CR, TLBLKCRWE)
324#define GET_CR_TLBIALLCFG(b) GET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG)
325#define GET_TLBIVMIDCFG(b) GET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG)
326#define GET_CR_HUME(b) GET_GLOBAL_FIELD(b, CR, CR_HUME)
327
328
329/* ESR */
330#define GET_CFG(b) GET_GLOBAL_FIELD(b, ESR, CFG)
331#define GET_BYPASS(b) GET_GLOBAL_FIELD(b, ESR, BYPASS)
332#define GET_ESR_MULTI(b) GET_GLOBAL_FIELD(b, ESR, ESR_MULTI)
333
334
335/* ESYNR0 */
336#define GET_ESYNR0_AMID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID)
337#define GET_ESYNR0_APID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID)
338#define GET_ESYNR0_ABID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID)
339#define GET_ESYNR0_AVMID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID)
340#define GET_ESYNR0_ATID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID)
341
342
343/* ESYNR1 */
344#define GET_ESYNR1_AMEMTYPE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE)
345#define GET_ESYNR1_ASHARED(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED)
346#define GET_ESYNR1_AINNERSHARED(b) \
347 GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED)
348#define GET_ESYNR1_APRIV(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV)
349#define GET_ESYNR1_APROTNS(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS)
350#define GET_ESYNR1_AINST(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST)
351#define GET_ESYNR1_AWRITE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE)
352#define GET_ESYNR1_ABURST(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST)
353#define GET_ESYNR1_ALEN(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN)
354#define GET_ESYNR1_ASIZE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE)
355#define GET_ESYNR1_ALOCK(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK)
356#define GET_ESYNR1_AOOO(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO)
357#define GET_ESYNR1_AFULL(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL)
358#define GET_ESYNR1_AC(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC)
359#define GET_ESYNR1_DCD(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD)
360
361
362/* IDR */
363#define GET_NM2VCBMT(b) GET_GLOBAL_FIELD(b, IDR, NM2VCBMT)
364#define GET_HTW(b) GET_GLOBAL_FIELD(b, IDR, HTW)
365#define GET_HUM(b) GET_GLOBAL_FIELD(b, IDR, HUM)
366#define GET_TLBSIZE(b) GET_GLOBAL_FIELD(b, IDR, TLBSIZE)
367#define GET_NCB(b) GET_GLOBAL_FIELD(b, IDR, NCB)
368#define GET_NIRPT(b) GET_GLOBAL_FIELD(b, IDR, NIRPT)
369
370
371/* REV */
372#define GET_MAJOR(b) GET_GLOBAL_FIELD(b, REV, MAJOR)
373#define GET_MINOR(b) GET_GLOBAL_FIELD(b, REV, MINOR)
374
375
376/* TESTBUSCR */
377#define GET_TBE(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBE)
378#define GET_SPDMBE(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE)
379#define GET_WGSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL)
380#define GET_TBLSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL)
381#define GET_TBHSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL)
382#define GET_SPDM0SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL)
383#define GET_SPDM1SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL)
384#define GET_SPDM2SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL)
385#define GET_SPDM3SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL)
386
387
388/* TLBIVMID */
389#define GET_TLBIVMID_VMID(b) GET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID)
390
391
392/* TLBTR0 */
393#define GET_PR(b) GET_GLOBAL_FIELD(b, TLBTR0, PR)
394#define GET_PW(b) GET_GLOBAL_FIELD(b, TLBTR0, PW)
395#define GET_UR(b) GET_GLOBAL_FIELD(b, TLBTR0, UR)
396#define GET_UW(b) GET_GLOBAL_FIELD(b, TLBTR0, UW)
397#define GET_XN(b) GET_GLOBAL_FIELD(b, TLBTR0, XN)
398#define GET_NSDESC(b) GET_GLOBAL_FIELD(b, TLBTR0, NSDESC)
399#define GET_ISH(b) GET_GLOBAL_FIELD(b, TLBTR0, ISH)
400#define GET_SH(b) GET_GLOBAL_FIELD(b, TLBTR0, SH)
401#define GET_MT(b) GET_GLOBAL_FIELD(b, TLBTR0, MT)
402#define GET_DPSIZR(b) GET_GLOBAL_FIELD(b, TLBTR0, DPSIZR)
403#define GET_DPSIZC(b) GET_GLOBAL_FIELD(b, TLBTR0, DPSIZC)
404
405
406/* TLBTR1 */
407#define GET_TLBTR1_VMID(b) GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID)
408#define GET_TLBTR1_PA(b) GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA)
409
410
411/* TLBTR2 */
412#define GET_TLBTR2_ASID(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID)
413#define GET_TLBTR2_V(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V)
414#define GET_TLBTR2_NSTID(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID)
415#define GET_TLBTR2_NV(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV)
416#define GET_TLBTR2_VA(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA)
417
418
419/* Context Register setters / getters */
420/* Context Register setters */
421/* ACTLR */
422#define SET_CFERE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFERE, v)
423#define SET_CFEIE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFEIE, v)
424#define SET_PTSHCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG, v)
425#define SET_RCOSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCOSH, v)
426#define SET_RCISH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCISH, v)
427#define SET_RCNSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCNSH, v)
428#define SET_PRIVCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG, v)
429#define SET_DNA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNA, v)
430#define SET_DNLV2PA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA, v)
431#define SET_TLBMCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG, v)
432#define SET_CFCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFCFG, v)
433#define SET_TIPCF(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TIPCF, v)
434#define SET_V2PCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG, v)
435#define SET_HUME(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, HUME, v)
436#define SET_PTMTCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG, v)
437#define SET_PTMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE, v)
438
439
440/* BFBCR */
441#define SET_BFBDFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE, v)
442#define SET_BFBSFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE, v)
443#define SET_SFVS(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SFVS, v)
444#define SET_FLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, FLVIC, v)
445#define SET_SLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SLVIC, v)
446
447
448/* CONTEXTIDR */
449#define SET_CONTEXTIDR_ASID(b, c, v) \
450 SET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID, v)
451#define SET_CONTEXTIDR_PROCID(b, c, v) \
452 SET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID, v)
453
454
455/* FSR */
456#define SET_TF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TF, v)
457#define SET_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, AFF, v)
458#define SET_APF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, APF, v)
459#define SET_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TLBMF, v)
460#define SET_HTWDEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWDEEF, v)
461#define SET_HTWSEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWSEEF, v)
462#define SET_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MHF, v)
463#define SET_SL(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SL, v)
464#define SET_SS(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SS, v)
465#define SET_MULTI(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MULTI, v)
466
467
468/* FSYNR0 */
469#define SET_AMID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, AMID, v)
470#define SET_APID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, APID, v)
471#define SET_ABID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ABID, v)
472#define SET_ATID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ATID, v)
473
474
475/* FSYNR1 */
476#define SET_AMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE, v)
477#define SET_ASHARED(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED, v)
478#define SET_AINNERSHARED(b, c, v) \
479 SET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED, v)
480#define SET_APRIV(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APRIV, v)
481#define SET_APROTNS(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS, v)
482#define SET_AINST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AINST, v)
483#define SET_AWRITE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE, v)
484#define SET_ABURST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ABURST, v)
485#define SET_ALEN(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALEN, v)
486#define SET_FSYNR1_ASIZE(b, c, v) \
487 SET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE, v)
488#define SET_ALOCK(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK, v)
489#define SET_AFULL(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AFULL, v)
490
491
492/* NMRR */
493#define SET_ICPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC0, v)
494#define SET_ICPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC1, v)
495#define SET_ICPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC2, v)
496#define SET_ICPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC3, v)
497#define SET_ICPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC4, v)
498#define SET_ICPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC5, v)
499#define SET_ICPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC6, v)
500#define SET_ICPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC7, v)
501#define SET_OCPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC0, v)
502#define SET_OCPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC1, v)
503#define SET_OCPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC2, v)
504#define SET_OCPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC3, v)
505#define SET_OCPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC4, v)
506#define SET_OCPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC5, v)
507#define SET_OCPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC6, v)
508#define SET_OCPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC7, v)
509
510
511/* PAR */
512#define SET_FAULT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT, v)
513
514#define SET_FAULT_TF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TF, v)
515#define SET_FAULT_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF, v)
516#define SET_FAULT_APF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_APF, v)
517#define SET_FAULT_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF, v)
518#define SET_FAULT_HTWDEEF(b, c, v) \
519 SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF, v)
520#define SET_FAULT_HTWSEEF(b, c, v) \
521 SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF, v)
522#define SET_FAULT_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF, v)
523#define SET_FAULT_SL(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SL, v)
524#define SET_FAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SS, v)
525
526#define SET_NOFAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SS, v)
527#define SET_NOFAULT_MT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_MT, v)
528#define SET_NOFAULT_SH(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SH, v)
529#define SET_NOFAULT_NS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NS, v)
530#define SET_NOFAULT_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NOS, v)
531#define SET_NPFAULT_PA(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NPFAULT_PA, v)
532
533
534/* PRRR */
535#define SET_MTC0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC0, v)
536#define SET_MTC1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC1, v)
537#define SET_MTC2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC2, v)
538#define SET_MTC3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC3, v)
539#define SET_MTC4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC4, v)
540#define SET_MTC5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC5, v)
541#define SET_MTC6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC6, v)
542#define SET_MTC7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC7, v)
543#define SET_SHDSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH0, v)
544#define SET_SHDSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH1, v)
545#define SET_SHNMSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0, v)
546#define SET_SHNMSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1, v)
547#define SET_NOS0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS0, v)
548#define SET_NOS1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS1, v)
549#define SET_NOS2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS2, v)
550#define SET_NOS3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS3, v)
551#define SET_NOS4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS4, v)
552#define SET_NOS5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS5, v)
553#define SET_NOS6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS6, v)
554#define SET_NOS7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS7, v)
555
556
557/* RESUME */
558#define SET_TNR(b, c, v) SET_CONTEXT_FIELD(b, c, RESUME, TNR, v)
559
560
561/* SCTLR */
562#define SET_M(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, M, v)
563#define SET_TRE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, TRE, v)
564#define SET_AFE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFE, v)
565#define SET_HAF(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, HAF, v)
566#define SET_BE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, BE, v)
567#define SET_AFFD(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFFD, v)
568
569
570/* TLBLKCR */
571#define SET_LKE(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, LKE, v)
572#define SET_TLBLKCR_TLBIALLCFG(b, c, v) \
573 SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG, v)
574#define SET_TLBIASIDCFG(b, c, v) \
575 SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG, v)
576#define SET_TLBIVAACFG(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG, v)
577#define SET_FLOOR(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR, v)
578#define SET_VICTIM(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM, v)
579
580
581/* TTBCR */
582#define SET_N(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, N, v)
583#define SET_PD0(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD0, v)
584#define SET_PD1(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD1, v)
585
586
587/* TTBR0 */
588#define SET_TTBR0_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH, v)
589#define SET_TTBR0_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH, v)
590#define SET_TTBR0_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN, v)
591#define SET_TTBR0_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS, v)
592#define SET_TTBR0_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL, v)
593#define SET_TTBR0_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA, v)
594
595
596/* TTBR1 */
597#define SET_TTBR1_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH, v)
598#define SET_TTBR1_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH, v)
599#define SET_TTBR1_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN, v)
600#define SET_TTBR1_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS, v)
601#define SET_TTBR1_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL, v)
602#define SET_TTBR1_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA, v)
603
604
605/* V2PSR */
606#define SET_HIT(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, HIT, v)
607#define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v)
608
609
610/* V2Pxx UW UR PW PR */
611#define SET_V2PUW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX, v)
612#define SET_V2PUW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA, v)
613
614#define SET_V2PUR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX, v)
615#define SET_V2PUR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA, v)
616
617#define SET_V2PPW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX, v)
618#define SET_V2PPW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA, v)
619
620#define SET_V2PPR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX, v)
621#define SET_V2PPR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA, v)
622
623
624/* Context Register getters */
625/* ACTLR */
626#define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE)
627#define GET_CFEIE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFEIE)
628#define GET_PTSHCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG)
629#define GET_RCOSH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCOSH)
630#define GET_RCISH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCISH)
631#define GET_RCNSH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCNSH)
632#define GET_PRIVCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG)
633#define GET_DNA(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, DNA)
634#define GET_DNLV2PA(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA)
635#define GET_TLBMCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG)
636#define GET_CFCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFCFG)
637#define GET_TIPCF(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, TIPCF)
638#define GET_V2PCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG)
639#define GET_HUME(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, HUME)
640#define GET_PTMTCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG)
641#define GET_PTMEMTYPE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE)
642
643/* BFBCR */
644#define GET_BFBDFE(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE)
645#define GET_BFBSFE(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE)
646#define GET_SFVS(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, SFVS)
647#define GET_FLVIC(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, FLVIC)
648#define GET_SLVIC(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, SLVIC)
649
650
651/* CONTEXTIDR */
652#define GET_CONTEXTIDR_ASID(b, c) \
653 GET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID)
654#define GET_CONTEXTIDR_PROCID(b, c) GET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID)
655
656
657/* FSR */
658#define GET_TF(b, c) GET_CONTEXT_FIELD(b, c, FSR, TF)
659#define GET_AFF(b, c) GET_CONTEXT_FIELD(b, c, FSR, AFF)
660#define GET_APF(b, c) GET_CONTEXT_FIELD(b, c, FSR, APF)
661#define GET_TLBMF(b, c) GET_CONTEXT_FIELD(b, c, FSR, TLBMF)
662#define GET_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, FSR, HTWDEEF)
663#define GET_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, FSR, HTWSEEF)
664#define GET_MHF(b, c) GET_CONTEXT_FIELD(b, c, FSR, MHF)
665#define GET_SL(b, c) GET_CONTEXT_FIELD(b, c, FSR, SL)
666#define GET_SS(b, c) GET_CONTEXT_FIELD(b, c, FSR, SS)
667#define GET_MULTI(b, c) GET_CONTEXT_FIELD(b, c, FSR, MULTI)
668
669
670/* FSYNR0 */
671#define GET_AMID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, AMID)
672#define GET_APID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, APID)
673#define GET_ABID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, ABID)
674#define GET_ATID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, ATID)
675
676
677/* FSYNR1 */
678#define GET_AMEMTYPE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE)
679#define GET_ASHARED(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED)
680#define GET_AINNERSHARED(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED)
681#define GET_APRIV(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, APRIV)
682#define GET_APROTNS(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS)
683#define GET_AINST(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AINST)
684#define GET_AWRITE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE)
685#define GET_ABURST(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ABURST)
686#define GET_ALEN(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ALEN)
687#define GET_FSYNR1_ASIZE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE)
688#define GET_ALOCK(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK)
689#define GET_AFULL(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AFULL)
690
691
692/* NMRR */
693#define GET_ICPC0(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC0)
694#define GET_ICPC1(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC1)
695#define GET_ICPC2(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC2)
696#define GET_ICPC3(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC3)
697#define GET_ICPC4(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC4)
698#define GET_ICPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC5)
699#define GET_ICPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC6)
700#define GET_ICPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC7)
701#define GET_OCPC0(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC0)
702#define GET_OCPC1(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC1)
703#define GET_OCPC2(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC2)
704#define GET_OCPC3(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC3)
705#define GET_OCPC4(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC4)
706#define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5)
707#define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6)
708#define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7)
709
710
711/* PAR */
712#define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT)
713
714#define GET_FAULT_TF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_TF)
715#define GET_FAULT_AFF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF)
716#define GET_FAULT_APF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_APF)
717#define GET_FAULT_TLBMF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF)
718#define GET_FAULT_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF)
719#define GET_FAULT_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF)
720#define GET_FAULT_MHF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF)
721#define GET_FAULT_SL(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_SL)
722#define GET_FAULT_SS(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_SS)
723
724#define GET_NOFAULT_SS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SS)
725#define GET_NOFAULT_MT(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_MT)
726#define GET_NOFAULT_SH(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SH)
727#define GET_NOFAULT_NS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NS)
728#define GET_NOFAULT_NOS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NOS)
729#define GET_NPFAULT_PA(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NPFAULT_PA)
730
731
732/* PRRR */
733#define GET_MTC0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC0)
734#define GET_MTC1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC1)
735#define GET_MTC2(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC2)
736#define GET_MTC3(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC3)
737#define GET_MTC4(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC4)
738#define GET_MTC5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC5)
739#define GET_MTC6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC6)
740#define GET_MTC7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC7)
741#define GET_SHDSH0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHDSH0)
742#define GET_SHDSH1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHDSH1)
743#define GET_SHNMSH0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0)
744#define GET_SHNMSH1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1)
745#define GET_NOS0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS0)
746#define GET_NOS1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS1)
747#define GET_NOS2(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS2)
748#define GET_NOS3(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS3)
749#define GET_NOS4(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS4)
750#define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5)
751#define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6)
752#define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7)
753
754
755/* RESUME */
756#define GET_TNR(b, c) GET_CONTEXT_FIELD(b, c, RESUME, TNR)
757
758
759/* SCTLR */
760#define GET_M(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, M)
761#define GET_TRE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, TRE)
762#define GET_AFE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, AFE)
763#define GET_HAF(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, HAF)
764#define GET_BE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, BE)
765#define GET_AFFD(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, AFFD)
766
767
768/* TLBLKCR */
769#define GET_LKE(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, LKE)
770#define GET_TLBLCKR_TLBIALLCFG(b, c) \
771 GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG)
772#define GET_TLBIASIDCFG(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG)
773#define GET_TLBIVAACFG(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG)
774#define GET_FLOOR(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR)
775#define GET_VICTIM(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM)
776
777
778/* TTBCR */
779#define GET_N(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, N)
780#define GET_PD0(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD0)
781#define GET_PD1(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD1)
782
783
784/* TTBR0 */
785#define GET_TTBR0_IRGNH(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH)
786#define GET_TTBR0_SH(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH)
787#define GET_TTBR0_ORGN(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN)
788#define GET_TTBR0_NOS(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS)
789#define GET_TTBR0_IRGNL(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL)
790#define GET_TTBR0_PA(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA)
791
792
793/* TTBR1 */
794#define GET_TTBR1_IRGNH(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH)
795#define GET_TTBR1_SH(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH)
796#define GET_TTBR1_ORGN(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN)
797#define GET_TTBR1_NOS(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS)
798#define GET_TTBR1_IRGNL(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL)
799#define GET_TTBR1_PA(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA)
800
801
802/* V2PSR */
803#define GET_HIT(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, HIT)
804#define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX)
805
806
807/* V2Pxx UW UR PW PR */
808#define GET_V2PUW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX)
809#define GET_V2PUW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA)
810
811#define GET_V2PUR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX)
812#define GET_V2PUR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA)
813
814#define GET_V2PPW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX)
815#define GET_V2PPW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA)
816
817#define GET_V2PPR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX)
818#define GET_V2PPR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA)
819
820
821/* Global Registers */
822#define M2VCBR_N (0xFF000)
823#define CBACR_N (0xFF800)
824#define TLBRSW (0xFFE00)
825#define TLBTR0 (0xFFE80)
826#define TLBTR1 (0xFFE84)
827#define TLBTR2 (0xFFE88)
828#define TESTBUSCR (0xFFE8C)
829#define GLOBAL_TLBIALL (0xFFF00)
830#define TLBIVMID (0xFFF04)
831#define CR (0xFFF80)
832#define EAR (0xFFF84)
833#define ESR (0xFFF88)
834#define ESRRESTORE (0xFFF8C)
835#define ESYNR0 (0xFFF90)
836#define ESYNR1 (0xFFF94)
837#define REV (0xFFFF4)
838#define IDR (0xFFFF8)
839#define RPU_ACR (0xFFFFC)
840
841
842/* Context Bank Registers */
843#define SCTLR (0x000)
844#define ACTLR (0x004)
845#define CONTEXTIDR (0x008)
846#define TTBR0 (0x010)
847#define TTBR1 (0x014)
848#define TTBCR (0x018)
849#define PAR (0x01C)
850#define FSR (0x020)
851#define FSRRESTORE (0x024)
852#define FAR (0x028)
853#define FSYNR0 (0x02C)
854#define FSYNR1 (0x030)
855#define PRRR (0x034)
856#define NMRR (0x038)
857#define TLBLCKR (0x03C)
858#define V2PSR (0x040)
859#define TLBFLPTER (0x044)
860#define TLBSLPTER (0x048)
861#define BFBCR (0x04C)
862#define CTX_TLBIALL (0x800)
863#define TLBIASID (0x804)
864#define TLBIVA (0x808)
865#define TLBIVAA (0x80C)
866#define V2PPR (0x810)
867#define V2PPW (0x814)
868#define V2PUR (0x818)
869#define V2PUW (0x81C)
870#define RESUME (0x820)
871
872
873/* Global Register Fields */
874/* CBACRn */
875#define RWVMID (RWVMID_MASK << RWVMID_SHIFT)
876#define RWE (RWE_MASK << RWE_SHIFT)
877#define RWGE (RWGE_MASK << RWGE_SHIFT)
878#define CBVMID (CBVMID_MASK << CBVMID_SHIFT)
879#define IRPTNDX (IRPTNDX_MASK << IRPTNDX_SHIFT)
880
881
882/* CR */
883#define RPUE (RPUE_MASK << RPUE_SHIFT)
884#define RPUERE (RPUERE_MASK << RPUERE_SHIFT)
885#define RPUEIE (RPUEIE_MASK << RPUEIE_SHIFT)
886#define DCDEE (DCDEE_MASK << DCDEE_SHIFT)
887#define CLIENTPD (CLIENTPD_MASK << CLIENTPD_SHIFT)
888#define STALLD (STALLD_MASK << STALLD_SHIFT)
889#define TLBLKCRWE (TLBLKCRWE_MASK << TLBLKCRWE_SHIFT)
890#define CR_TLBIALLCFG (CR_TLBIALLCFG_MASK << CR_TLBIALLCFG_SHIFT)
891#define TLBIVMIDCFG (TLBIVMIDCFG_MASK << TLBIVMIDCFG_SHIFT)
892#define CR_HUME (CR_HUME_MASK << CR_HUME_SHIFT)
893
894
895/* ESR */
896#define CFG (CFG_MASK << CFG_SHIFT)
897#define BYPASS (BYPASS_MASK << BYPASS_SHIFT)
898#define ESR_MULTI (ESR_MULTI_MASK << ESR_MULTI_SHIFT)
899
900
901/* ESYNR0 */
902#define ESYNR0_AMID (ESYNR0_AMID_MASK << ESYNR0_AMID_SHIFT)
903#define ESYNR0_APID (ESYNR0_APID_MASK << ESYNR0_APID_SHIFT)
904#define ESYNR0_ABID (ESYNR0_ABID_MASK << ESYNR0_ABID_SHIFT)
905#define ESYNR0_AVMID (ESYNR0_AVMID_MASK << ESYNR0_AVMID_SHIFT)
906#define ESYNR0_ATID (ESYNR0_ATID_MASK << ESYNR0_ATID_SHIFT)
907
908
909/* ESYNR1 */
910#define ESYNR1_AMEMTYPE (ESYNR1_AMEMTYPE_MASK << ESYNR1_AMEMTYPE_SHIFT)
911#define ESYNR1_ASHARED (ESYNR1_ASHARED_MASK << ESYNR1_ASHARED_SHIFT)
912#define ESYNR1_AINNERSHARED (ESYNR1_AINNERSHARED_MASK<< \
913 ESYNR1_AINNERSHARED_SHIFT)
914#define ESYNR1_APRIV (ESYNR1_APRIV_MASK << ESYNR1_APRIV_SHIFT)
915#define ESYNR1_APROTNS (ESYNR1_APROTNS_MASK << ESYNR1_APROTNS_SHIFT)
916#define ESYNR1_AINST (ESYNR1_AINST_MASK << ESYNR1_AINST_SHIFT)
917#define ESYNR1_AWRITE (ESYNR1_AWRITE_MASK << ESYNR1_AWRITE_SHIFT)
918#define ESYNR1_ABURST (ESYNR1_ABURST_MASK << ESYNR1_ABURST_SHIFT)
919#define ESYNR1_ALEN (ESYNR1_ALEN_MASK << ESYNR1_ALEN_SHIFT)
920#define ESYNR1_ASIZE (ESYNR1_ASIZE_MASK << ESYNR1_ASIZE_SHIFT)
921#define ESYNR1_ALOCK (ESYNR1_ALOCK_MASK << ESYNR1_ALOCK_SHIFT)
922#define ESYNR1_AOOO (ESYNR1_AOOO_MASK << ESYNR1_AOOO_SHIFT)
923#define ESYNR1_AFULL (ESYNR1_AFULL_MASK << ESYNR1_AFULL_SHIFT)
924#define ESYNR1_AC (ESYNR1_AC_MASK << ESYNR1_AC_SHIFT)
925#define ESYNR1_DCD (ESYNR1_DCD_MASK << ESYNR1_DCD_SHIFT)
926
927
928/* IDR */
929#define NM2VCBMT (NM2VCBMT_MASK << NM2VCBMT_SHIFT)
930#define HTW (HTW_MASK << HTW_SHIFT)
931#define HUM (HUM_MASK << HUM_SHIFT)
932#define TLBSIZE (TLBSIZE_MASK << TLBSIZE_SHIFT)
933#define NCB (NCB_MASK << NCB_SHIFT)
934#define NIRPT (NIRPT_MASK << NIRPT_SHIFT)
935
936
937/* M2VCBRn */
938#define VMID (VMID_MASK << VMID_SHIFT)
939#define CBNDX (CBNDX_MASK << CBNDX_SHIFT)
940#define BYPASSD (BYPASSD_MASK << BYPASSD_SHIFT)
941#define BPRCOSH (BPRCOSH_MASK << BPRCOSH_SHIFT)
942#define BPRCISH (BPRCISH_MASK << BPRCISH_SHIFT)
943#define BPRCNSH (BPRCNSH_MASK << BPRCNSH_SHIFT)
944#define BPSHCFG (BPSHCFG_MASK << BPSHCFG_SHIFT)
945#define NSCFG (NSCFG_MASK << NSCFG_SHIFT)
946#define BPMTCFG (BPMTCFG_MASK << BPMTCFG_SHIFT)
947#define BPMEMTYPE (BPMEMTYPE_MASK << BPMEMTYPE_SHIFT)
948
949
950/* REV */
951#define IDR_MINOR (MINOR_MASK << MINOR_SHIFT)
952#define IDR_MAJOR (MAJOR_MASK << MAJOR_SHIFT)
953
954
955/* TESTBUSCR */
956#define TBE (TBE_MASK << TBE_SHIFT)
957#define SPDMBE (SPDMBE_MASK << SPDMBE_SHIFT)
958#define WGSEL (WGSEL_MASK << WGSEL_SHIFT)
959#define TBLSEL (TBLSEL_MASK << TBLSEL_SHIFT)
960#define TBHSEL (TBHSEL_MASK << TBHSEL_SHIFT)
961#define SPDM0SEL (SPDM0SEL_MASK << SPDM0SEL_SHIFT)
962#define SPDM1SEL (SPDM1SEL_MASK << SPDM1SEL_SHIFT)
963#define SPDM2SEL (SPDM2SEL_MASK << SPDM2SEL_SHIFT)
964#define SPDM3SEL (SPDM3SEL_MASK << SPDM3SEL_SHIFT)
965
966
967/* TLBIVMID */
968#define TLBIVMID_VMID (TLBIVMID_VMID_MASK << TLBIVMID_VMID_SHIFT)
969
970
971/* TLBRSW */
972#define TLBRSW_INDEX (TLBRSW_INDEX_MASK << TLBRSW_INDEX_SHIFT)
973#define TLBBFBS (TLBBFBS_MASK << TLBBFBS_SHIFT)
974
975
976/* TLBTR0 */
977#define PR (PR_MASK << PR_SHIFT)
978#define PW (PW_MASK << PW_SHIFT)
979#define UR (UR_MASK << UR_SHIFT)
980#define UW (UW_MASK << UW_SHIFT)
981#define XN (XN_MASK << XN_SHIFT)
982#define NSDESC (NSDESC_MASK << NSDESC_SHIFT)
983#define ISH (ISH_MASK << ISH_SHIFT)
984#define SH (SH_MASK << SH_SHIFT)
985#define MT (MT_MASK << MT_SHIFT)
986#define DPSIZR (DPSIZR_MASK << DPSIZR_SHIFT)
987#define DPSIZC (DPSIZC_MASK << DPSIZC_SHIFT)
988
989
990/* TLBTR1 */
991#define TLBTR1_VMID (TLBTR1_VMID_MASK << TLBTR1_VMID_SHIFT)
992#define TLBTR1_PA (TLBTR1_PA_MASK << TLBTR1_PA_SHIFT)
993
994
995/* TLBTR2 */
996#define TLBTR2_ASID (TLBTR2_ASID_MASK << TLBTR2_ASID_SHIFT)
997#define TLBTR2_V (TLBTR2_V_MASK << TLBTR2_V_SHIFT)
998#define TLBTR2_NSTID (TLBTR2_NSTID_MASK << TLBTR2_NSTID_SHIFT)
999#define TLBTR2_NV (TLBTR2_NV_MASK << TLBTR2_NV_SHIFT)
1000#define TLBTR2_VA (TLBTR2_VA_MASK << TLBTR2_VA_SHIFT)
1001
1002
1003/* Context Register Fields */
1004/* ACTLR */
1005#define CFERE (CFERE_MASK << CFERE_SHIFT)
1006#define CFEIE (CFEIE_MASK << CFEIE_SHIFT)
1007#define PTSHCFG (PTSHCFG_MASK << PTSHCFG_SHIFT)
1008#define RCOSH (RCOSH_MASK << RCOSH_SHIFT)
1009#define RCISH (RCISH_MASK << RCISH_SHIFT)
1010#define RCNSH (RCNSH_MASK << RCNSH_SHIFT)
1011#define PRIVCFG (PRIVCFG_MASK << PRIVCFG_SHIFT)
1012#define DNA (DNA_MASK << DNA_SHIFT)
1013#define DNLV2PA (DNLV2PA_MASK << DNLV2PA_SHIFT)
1014#define TLBMCFG (TLBMCFG_MASK << TLBMCFG_SHIFT)
1015#define CFCFG (CFCFG_MASK << CFCFG_SHIFT)
1016#define TIPCF (TIPCF_MASK << TIPCF_SHIFT)
1017#define V2PCFG (V2PCFG_MASK << V2PCFG_SHIFT)
1018#define HUME (HUME_MASK << HUME_SHIFT)
1019#define PTMTCFG (PTMTCFG_MASK << PTMTCFG_SHIFT)
1020#define PTMEMTYPE (PTMEMTYPE_MASK << PTMEMTYPE_SHIFT)
1021
1022
1023/* BFBCR */
1024#define BFBDFE (BFBDFE_MASK << BFBDFE_SHIFT)
1025#define BFBSFE (BFBSFE_MASK << BFBSFE_SHIFT)
1026#define SFVS (SFVS_MASK << SFVS_SHIFT)
1027#define FLVIC (FLVIC_MASK << FLVIC_SHIFT)
1028#define SLVIC (SLVIC_MASK << SLVIC_SHIFT)
1029
1030
1031/* CONTEXTIDR */
1032#define CONTEXTIDR_ASID (CONTEXTIDR_ASID_MASK << CONTEXTIDR_ASID_SHIFT)
1033#define PROCID (PROCID_MASK << PROCID_SHIFT)
1034
1035
1036/* FSR */
1037#define TF (TF_MASK << TF_SHIFT)
1038#define AFF (AFF_MASK << AFF_SHIFT)
1039#define APF (APF_MASK << APF_SHIFT)
1040#define TLBMF (TLBMF_MASK << TLBMF_SHIFT)
1041#define HTWDEEF (HTWDEEF_MASK << HTWDEEF_SHIFT)
1042#define HTWSEEF (HTWSEEF_MASK << HTWSEEF_SHIFT)
1043#define MHF (MHF_MASK << MHF_SHIFT)
1044#define SL (SL_MASK << SL_SHIFT)
1045#define SS (SS_MASK << SS_SHIFT)
1046#define MULTI (MULTI_MASK << MULTI_SHIFT)
1047
1048
1049/* FSYNR0 */
1050#define AMID (AMID_MASK << AMID_SHIFT)
1051#define APID (APID_MASK << APID_SHIFT)
1052#define ABID (ABID_MASK << ABID_SHIFT)
1053#define ATID (ATID_MASK << ATID_SHIFT)
1054
1055
1056/* FSYNR1 */
1057#define AMEMTYPE (AMEMTYPE_MASK << AMEMTYPE_SHIFT)
1058#define ASHARED (ASHARED_MASK << ASHARED_SHIFT)
1059#define AINNERSHARED (AINNERSHARED_MASK << AINNERSHARED_SHIFT)
1060#define APRIV (APRIV_MASK << APRIV_SHIFT)
1061#define APROTNS (APROTNS_MASK << APROTNS_SHIFT)
1062#define AINST (AINST_MASK << AINST_SHIFT)
1063#define AWRITE (AWRITE_MASK << AWRITE_SHIFT)
1064#define ABURST (ABURST_MASK << ABURST_SHIFT)
1065#define ALEN (ALEN_MASK << ALEN_SHIFT)
1066#define FSYNR1_ASIZE (FSYNR1_ASIZE_MASK << FSYNR1_ASIZE_SHIFT)
1067#define ALOCK (ALOCK_MASK << ALOCK_SHIFT)
1068#define AFULL (AFULL_MASK << AFULL_SHIFT)
1069
1070
1071/* NMRR */
1072#define ICPC0 (ICPC0_MASK << ICPC0_SHIFT)
1073#define ICPC1 (ICPC1_MASK << ICPC1_SHIFT)
1074#define ICPC2 (ICPC2_MASK << ICPC2_SHIFT)
1075#define ICPC3 (ICPC3_MASK << ICPC3_SHIFT)
1076#define ICPC4 (ICPC4_MASK << ICPC4_SHIFT)
1077#define ICPC5 (ICPC5_MASK << ICPC5_SHIFT)
1078#define ICPC6 (ICPC6_MASK << ICPC6_SHIFT)
1079#define ICPC7 (ICPC7_MASK << ICPC7_SHIFT)
1080#define OCPC0 (OCPC0_MASK << OCPC0_SHIFT)
1081#define OCPC1 (OCPC1_MASK << OCPC1_SHIFT)
1082#define OCPC2 (OCPC2_MASK << OCPC2_SHIFT)
1083#define OCPC3 (OCPC3_MASK << OCPC3_SHIFT)
1084#define OCPC4 (OCPC4_MASK << OCPC4_SHIFT)
1085#define OCPC5 (OCPC5_MASK << OCPC5_SHIFT)
1086#define OCPC6 (OCPC6_MASK << OCPC6_SHIFT)
1087#define OCPC7 (OCPC7_MASK << OCPC7_SHIFT)
1088
1089
1090/* PAR */
1091#define FAULT (FAULT_MASK << FAULT_SHIFT)
1092/* If a fault is present, these are the
1093same as the fault fields in the FAR */
1094#define FAULT_TF (FAULT_TF_MASK << FAULT_TF_SHIFT)
1095#define FAULT_AFF (FAULT_AFF_MASK << FAULT_AFF_SHIFT)
1096#define FAULT_APF (FAULT_APF_MASK << FAULT_APF_SHIFT)
1097#define FAULT_TLBMF (FAULT_TLBMF_MASK << FAULT_TLBMF_SHIFT)
1098#define FAULT_HTWDEEF (FAULT_HTWDEEF_MASK << FAULT_HTWDEEF_SHIFT)
1099#define FAULT_HTWSEEF (FAULT_HTWSEEF_MASK << FAULT_HTWSEEF_SHIFT)
1100#define FAULT_MHF (FAULT_MHF_MASK << FAULT_MHF_SHIFT)
1101#define FAULT_SL (FAULT_SL_MASK << FAULT_SL_SHIFT)
1102#define FAULT_SS (FAULT_SS_MASK << FAULT_SS_SHIFT)
1103
1104/* If NO fault is present, the following fields are in effect */
1105/* (FAULT remains as before) */
1106#define PAR_NOFAULT_SS (PAR_NOFAULT_SS_MASK << PAR_NOFAULT_SS_SHIFT)
1107#define PAR_NOFAULT_MT (PAR_NOFAULT_MT_MASK << PAR_NOFAULT_MT_SHIFT)
1108#define PAR_NOFAULT_SH (PAR_NOFAULT_SH_MASK << PAR_NOFAULT_SH_SHIFT)
1109#define PAR_NOFAULT_NS (PAR_NOFAULT_NS_MASK << PAR_NOFAULT_NS_SHIFT)
1110#define PAR_NOFAULT_NOS (PAR_NOFAULT_NOS_MASK << PAR_NOFAULT_NOS_SHIFT)
1111#define PAR_NPFAULT_PA (PAR_NPFAULT_PA_MASK << PAR_NPFAULT_PA_SHIFT)
1112
1113
1114/* PRRR */
1115#define MTC0 (MTC0_MASK << MTC0_SHIFT)
1116#define MTC1 (MTC1_MASK << MTC1_SHIFT)
1117#define MTC2 (MTC2_MASK << MTC2_SHIFT)
1118#define MTC3 (MTC3_MASK << MTC3_SHIFT)
1119#define MTC4 (MTC4_MASK << MTC4_SHIFT)
1120#define MTC5 (MTC5_MASK << MTC5_SHIFT)
1121#define MTC6 (MTC6_MASK << MTC6_SHIFT)
1122#define MTC7 (MTC7_MASK << MTC7_SHIFT)
1123#define SHDSH0 (SHDSH0_MASK << SHDSH0_SHIFT)
1124#define SHDSH1 (SHDSH1_MASK << SHDSH1_SHIFT)
1125#define SHNMSH0 (SHNMSH0_MASK << SHNMSH0_SHIFT)
1126#define SHNMSH1 (SHNMSH1_MASK << SHNMSH1_SHIFT)
1127#define NOS0 (NOS0_MASK << NOS0_SHIFT)
1128#define NOS1 (NOS1_MASK << NOS1_SHIFT)
1129#define NOS2 (NOS2_MASK << NOS2_SHIFT)
1130#define NOS3 (NOS3_MASK << NOS3_SHIFT)
1131#define NOS4 (NOS4_MASK << NOS4_SHIFT)
1132#define NOS5 (NOS5_MASK << NOS5_SHIFT)
1133#define NOS6 (NOS6_MASK << NOS6_SHIFT)
1134#define NOS7 (NOS7_MASK << NOS7_SHIFT)
1135
1136
1137/* RESUME */
1138#define TNR (TNR_MASK << TNR_SHIFT)
1139
1140
1141/* SCTLR */
1142#define M (M_MASK << M_SHIFT)
1143#define TRE (TRE_MASK << TRE_SHIFT)
1144#define AFE (AFE_MASK << AFE_SHIFT)
1145#define HAF (HAF_MASK << HAF_SHIFT)
1146#define BE (BE_MASK << BE_SHIFT)
1147#define AFFD (AFFD_MASK << AFFD_SHIFT)
1148
1149
1150/* TLBIASID */
1151#define TLBIASID_ASID (TLBIASID_ASID_MASK << TLBIASID_ASID_SHIFT)
1152
1153
1154/* TLBIVA */
1155#define TLBIVA_ASID (TLBIVA_ASID_MASK << TLBIVA_ASID_SHIFT)
1156#define TLBIVA_VA (TLBIVA_VA_MASK << TLBIVA_VA_SHIFT)
1157
1158
1159/* TLBIVAA */
1160#define TLBIVAA_VA (TLBIVAA_VA_MASK << TLBIVAA_VA_SHIFT)
1161
1162
1163/* TLBLCKR */
1164#define LKE (LKE_MASK << LKE_SHIFT)
1165#define TLBLCKR_TLBIALLCFG (TLBLCKR_TLBIALLCFG_MASK<<TLBLCKR_TLBIALLCFG_SHIFT)
1166#define TLBIASIDCFG (TLBIASIDCFG_MASK << TLBIASIDCFG_SHIFT)
1167#define TLBIVAACFG (TLBIVAACFG_MASK << TLBIVAACFG_SHIFT)
1168#define FLOOR (FLOOR_MASK << FLOOR_SHIFT)
1169#define VICTIM (VICTIM_MASK << VICTIM_SHIFT)
1170
1171
1172/* TTBCR */
1173#define N (N_MASK << N_SHIFT)
1174#define PD0 (PD0_MASK << PD0_SHIFT)
1175#define PD1 (PD1_MASK << PD1_SHIFT)
1176
1177
1178/* TTBR0 */
1179#define TTBR0_IRGNH (TTBR0_IRGNH_MASK << TTBR0_IRGNH_SHIFT)
1180#define TTBR0_SH (TTBR0_SH_MASK << TTBR0_SH_SHIFT)
1181#define TTBR0_ORGN (TTBR0_ORGN_MASK << TTBR0_ORGN_SHIFT)
1182#define TTBR0_NOS (TTBR0_NOS_MASK << TTBR0_NOS_SHIFT)
1183#define TTBR0_IRGNL (TTBR0_IRGNL_MASK << TTBR0_IRGNL_SHIFT)
1184#define TTBR0_PA (TTBR0_PA_MASK << TTBR0_PA_SHIFT)
1185
1186
1187/* TTBR1 */
1188#define TTBR1_IRGNH (TTBR1_IRGNH_MASK << TTBR1_IRGNH_SHIFT)
1189#define TTBR1_SH (TTBR1_SH_MASK << TTBR1_SH_SHIFT)
1190#define TTBR1_ORGN (TTBR1_ORGN_MASK << TTBR1_ORGN_SHIFT)
1191#define TTBR1_NOS (TTBR1_NOS_MASK << TTBR1_NOS_SHIFT)
1192#define TTBR1_IRGNL (TTBR1_IRGNL_MASK << TTBR1_IRGNL_SHIFT)
1193#define TTBR1_PA (TTBR1_PA_MASK << TTBR1_PA_SHIFT)
1194
1195
1196/* V2PSR */
1197#define HIT (HIT_MASK << HIT_SHIFT)
1198#define INDEX (INDEX_MASK << INDEX_SHIFT)
1199
1200
1201/* V2Pxx */
1202#define V2Pxx_INDEX (V2Pxx_INDEX_MASK << V2Pxx_INDEX_SHIFT)
1203#define V2Pxx_VA (V2Pxx_VA_MASK << V2Pxx_VA_SHIFT)
1204
1205
1206/* Global Register Masks */
1207/* CBACRn */
1208#define RWVMID_MASK 0x1F
1209#define RWE_MASK 0x01
1210#define RWGE_MASK 0x01
1211#define CBVMID_MASK 0x1F
1212#define IRPTNDX_MASK 0xFF
1213
1214
1215/* CR */
1216#define RPUE_MASK 0x01
1217#define RPUERE_MASK 0x01
1218#define RPUEIE_MASK 0x01
1219#define DCDEE_MASK 0x01
1220#define CLIENTPD_MASK 0x01
1221#define STALLD_MASK 0x01
1222#define TLBLKCRWE_MASK 0x01
1223#define CR_TLBIALLCFG_MASK 0x01
1224#define TLBIVMIDCFG_MASK 0x01
1225#define CR_HUME_MASK 0x01
1226
1227
1228/* ESR */
1229#define CFG_MASK 0x01
1230#define BYPASS_MASK 0x01
1231#define ESR_MULTI_MASK 0x01
1232
1233
1234/* ESYNR0 */
1235#define ESYNR0_AMID_MASK 0xFF
1236#define ESYNR0_APID_MASK 0x1F
1237#define ESYNR0_ABID_MASK 0x07
1238#define ESYNR0_AVMID_MASK 0x1F
1239#define ESYNR0_ATID_MASK 0xFF
1240
1241
1242/* ESYNR1 */
1243#define ESYNR1_AMEMTYPE_MASK 0x07
1244#define ESYNR1_ASHARED_MASK 0x01
1245#define ESYNR1_AINNERSHARED_MASK 0x01
1246#define ESYNR1_APRIV_MASK 0x01
1247#define ESYNR1_APROTNS_MASK 0x01
1248#define ESYNR1_AINST_MASK 0x01
1249#define ESYNR1_AWRITE_MASK 0x01
1250#define ESYNR1_ABURST_MASK 0x01
1251#define ESYNR1_ALEN_MASK 0x0F
1252#define ESYNR1_ASIZE_MASK 0x01
1253#define ESYNR1_ALOCK_MASK 0x03
1254#define ESYNR1_AOOO_MASK 0x01
1255#define ESYNR1_AFULL_MASK 0x01
1256#define ESYNR1_AC_MASK 0x01
1257#define ESYNR1_DCD_MASK 0x01
1258
1259
1260/* IDR */
1261#define NM2VCBMT_MASK 0x1FF
1262#define HTW_MASK 0x01
1263#define HUM_MASK 0x01
1264#define TLBSIZE_MASK 0x0F
1265#define NCB_MASK 0xFF
1266#define NIRPT_MASK 0xFF
1267
1268
1269/* M2VCBRn */
1270#define VMID_MASK 0x1F
1271#define CBNDX_MASK 0xFF
1272#define BYPASSD_MASK 0x01
1273#define BPRCOSH_MASK 0x01
1274#define BPRCISH_MASK 0x01
1275#define BPRCNSH_MASK 0x01
1276#define BPSHCFG_MASK 0x03
1277#define NSCFG_MASK 0x03
1278#define BPMTCFG_MASK 0x01
1279#define BPMEMTYPE_MASK 0x07
1280
1281
1282/* REV */
1283#define MINOR_MASK 0x0F
1284#define MAJOR_MASK 0x0F
1285
1286
1287/* TESTBUSCR */
1288#define TBE_MASK 0x01
1289#define SPDMBE_MASK 0x01
1290#define WGSEL_MASK 0x03
1291#define TBLSEL_MASK 0x03
1292#define TBHSEL_MASK 0x03
1293#define SPDM0SEL_MASK 0x0F
1294#define SPDM1SEL_MASK 0x0F
1295#define SPDM2SEL_MASK 0x0F
1296#define SPDM3SEL_MASK 0x0F
1297
1298
1299/* TLBIMID */
1300#define TLBIVMID_VMID_MASK 0x1F
1301
1302
1303/* TLBRSW */
1304#define TLBRSW_INDEX_MASK 0xFF
1305#define TLBBFBS_MASK 0x03
1306
1307
1308/* TLBTR0 */
1309#define PR_MASK 0x01
1310#define PW_MASK 0x01
1311#define UR_MASK 0x01
1312#define UW_MASK 0x01
1313#define XN_MASK 0x01
1314#define NSDESC_MASK 0x01
1315#define ISH_MASK 0x01
1316#define SH_MASK 0x01
1317#define MT_MASK 0x07
1318#define DPSIZR_MASK 0x07
1319#define DPSIZC_MASK 0x07
1320
1321
1322/* TLBTR1 */
1323#define TLBTR1_VMID_MASK 0x1F
1324#define TLBTR1_PA_MASK 0x000FFFFF
1325
1326
1327/* TLBTR2 */
1328#define TLBTR2_ASID_MASK 0xFF
1329#define TLBTR2_V_MASK 0x01
1330#define TLBTR2_NSTID_MASK 0x01
1331#define TLBTR2_NV_MASK 0x01
1332#define TLBTR2_VA_MASK 0x000FFFFF
1333
1334
1335/* Global Register Shifts */
1336/* CBACRn */
1337#define RWVMID_SHIFT 0
1338#define RWE_SHIFT 8
1339#define RWGE_SHIFT 9
1340#define CBVMID_SHIFT 16
1341#define IRPTNDX_SHIFT 24
1342
1343
1344/* CR */
1345#define RPUE_SHIFT 0
1346#define RPUERE_SHIFT 1
1347#define RPUEIE_SHIFT 2
1348#define DCDEE_SHIFT 3
1349#define CLIENTPD_SHIFT 4
1350#define STALLD_SHIFT 5
1351#define TLBLKCRWE_SHIFT 6
1352#define CR_TLBIALLCFG_SHIFT 7
1353#define TLBIVMIDCFG_SHIFT 8
1354#define CR_HUME_SHIFT 9
1355
1356
1357/* ESR */
1358#define CFG_SHIFT 0
1359#define BYPASS_SHIFT 1
1360#define ESR_MULTI_SHIFT 31
1361
1362
1363/* ESYNR0 */
1364#define ESYNR0_AMID_SHIFT 0
1365#define ESYNR0_APID_SHIFT 8
1366#define ESYNR0_ABID_SHIFT 13
1367#define ESYNR0_AVMID_SHIFT 16
1368#define ESYNR0_ATID_SHIFT 24
1369
1370
1371/* ESYNR1 */
1372#define ESYNR1_AMEMTYPE_SHIFT 0
1373#define ESYNR1_ASHARED_SHIFT 3
1374#define ESYNR1_AINNERSHARED_SHIFT 4
1375#define ESYNR1_APRIV_SHIFT 5
1376#define ESYNR1_APROTNS_SHIFT 6
1377#define ESYNR1_AINST_SHIFT 7
1378#define ESYNR1_AWRITE_SHIFT 8
1379#define ESYNR1_ABURST_SHIFT 10
1380#define ESYNR1_ALEN_SHIFT 12
1381#define ESYNR1_ASIZE_SHIFT 16
1382#define ESYNR1_ALOCK_SHIFT 20
1383#define ESYNR1_AOOO_SHIFT 22
1384#define ESYNR1_AFULL_SHIFT 24
1385#define ESYNR1_AC_SHIFT 30
1386#define ESYNR1_DCD_SHIFT 31
1387
1388
1389/* IDR */
1390#define NM2VCBMT_SHIFT 0
1391#define HTW_SHIFT 9
1392#define HUM_SHIFT 10
1393#define TLBSIZE_SHIFT 12
1394#define NCB_SHIFT 16
1395#define NIRPT_SHIFT 24
1396
1397
1398/* M2VCBRn */
1399#define VMID_SHIFT 0
1400#define CBNDX_SHIFT 8
1401#define BYPASSD_SHIFT 16
1402#define BPRCOSH_SHIFT 17
1403#define BPRCISH_SHIFT 18
1404#define BPRCNSH_SHIFT 19
1405#define BPSHCFG_SHIFT 20
1406#define NSCFG_SHIFT 22
1407#define BPMTCFG_SHIFT 24
1408#define BPMEMTYPE_SHIFT 25
1409
1410
1411/* REV */
1412#define MINOR_SHIFT 0
1413#define MAJOR_SHIFT 4
1414
1415
1416/* TESTBUSCR */
1417#define TBE_SHIFT 0
1418#define SPDMBE_SHIFT 1
1419#define WGSEL_SHIFT 8
1420#define TBLSEL_SHIFT 12
1421#define TBHSEL_SHIFT 14
1422#define SPDM0SEL_SHIFT 16
1423#define SPDM1SEL_SHIFT 20
1424#define SPDM2SEL_SHIFT 24
1425#define SPDM3SEL_SHIFT 28
1426
1427
1428/* TLBIMID */
1429#define TLBIVMID_VMID_SHIFT 0
1430
1431
1432/* TLBRSW */
1433#define TLBRSW_INDEX_SHIFT 0
1434#define TLBBFBS_SHIFT 8
1435
1436
1437/* TLBTR0 */
1438#define PR_SHIFT 0
1439#define PW_SHIFT 1
1440#define UR_SHIFT 2
1441#define UW_SHIFT 3
1442#define XN_SHIFT 4
1443#define NSDESC_SHIFT 6
1444#define ISH_SHIFT 7
1445#define SH_SHIFT 8
1446#define MT_SHIFT 9
1447#define DPSIZR_SHIFT 16
1448#define DPSIZC_SHIFT 20
1449
1450
1451/* TLBTR1 */
1452#define TLBTR1_VMID_SHIFT 0
1453#define TLBTR1_PA_SHIFT 12
1454
1455
1456/* TLBTR2 */
1457#define TLBTR2_ASID_SHIFT 0
1458#define TLBTR2_V_SHIFT 8
1459#define TLBTR2_NSTID_SHIFT 9
1460#define TLBTR2_NV_SHIFT 10
1461#define TLBTR2_VA_SHIFT 12
1462
1463
1464/* Context Register Masks */
1465/* ACTLR */
1466#define CFERE_MASK 0x01
1467#define CFEIE_MASK 0x01
1468#define PTSHCFG_MASK 0x03
1469#define RCOSH_MASK 0x01
1470#define RCISH_MASK 0x01
1471#define RCNSH_MASK 0x01
1472#define PRIVCFG_MASK 0x03
1473#define DNA_MASK 0x01
1474#define DNLV2PA_MASK 0x01
1475#define TLBMCFG_MASK 0x03
1476#define CFCFG_MASK 0x01
1477#define TIPCF_MASK 0x01
1478#define V2PCFG_MASK 0x03
1479#define HUME_MASK 0x01
1480#define PTMTCFG_MASK 0x01
1481#define PTMEMTYPE_MASK 0x07
1482
1483
1484/* BFBCR */
1485#define BFBDFE_MASK 0x01
1486#define BFBSFE_MASK 0x01
1487#define SFVS_MASK 0x01
1488#define FLVIC_MASK 0x0F
1489#define SLVIC_MASK 0x0F
1490
1491
1492/* CONTEXTIDR */
1493#define CONTEXTIDR_ASID_MASK 0xFF
1494#define PROCID_MASK 0x00FFFFFF
1495
1496
1497/* FSR */
1498#define TF_MASK 0x01
1499#define AFF_MASK 0x01
1500#define APF_MASK 0x01
1501#define TLBMF_MASK 0x01
1502#define HTWDEEF_MASK 0x01
1503#define HTWSEEF_MASK 0x01
1504#define MHF_MASK 0x01
1505#define SL_MASK 0x01
1506#define SS_MASK 0x01
1507#define MULTI_MASK 0x01
1508
1509
1510/* FSYNR0 */
1511#define AMID_MASK 0xFF
1512#define APID_MASK 0x1F
1513#define ABID_MASK 0x07
1514#define ATID_MASK 0xFF
1515
1516
1517/* FSYNR1 */
1518#define AMEMTYPE_MASK 0x07
1519#define ASHARED_MASK 0x01
1520#define AINNERSHARED_MASK 0x01
1521#define APRIV_MASK 0x01
1522#define APROTNS_MASK 0x01
1523#define AINST_MASK 0x01
1524#define AWRITE_MASK 0x01
1525#define ABURST_MASK 0x01
1526#define ALEN_MASK 0x0F
1527#define FSYNR1_ASIZE_MASK 0x07
1528#define ALOCK_MASK 0x03
1529#define AFULL_MASK 0x01
1530
1531
1532/* NMRR */
1533#define ICPC0_MASK 0x03
1534#define ICPC1_MASK 0x03
1535#define ICPC2_MASK 0x03
1536#define ICPC3_MASK 0x03
1537#define ICPC4_MASK 0x03
1538#define ICPC5_MASK 0x03
1539#define ICPC6_MASK 0x03
1540#define ICPC7_MASK 0x03
1541#define OCPC0_MASK 0x03
1542#define OCPC1_MASK 0x03
1543#define OCPC2_MASK 0x03
1544#define OCPC3_MASK 0x03
1545#define OCPC4_MASK 0x03
1546#define OCPC5_MASK 0x03
1547#define OCPC6_MASK 0x03
1548#define OCPC7_MASK 0x03
1549
1550
1551/* PAR */
1552#define FAULT_MASK 0x01
1553/* If a fault is present, these are the
1554same as the fault fields in the FAR */
1555#define FAULT_TF_MASK 0x01
1556#define FAULT_AFF_MASK 0x01
1557#define FAULT_APF_MASK 0x01
1558#define FAULT_TLBMF_MASK 0x01
1559#define FAULT_HTWDEEF_MASK 0x01
1560#define FAULT_HTWSEEF_MASK 0x01
1561#define FAULT_MHF_MASK 0x01
1562#define FAULT_SL_MASK 0x01
1563#define FAULT_SS_MASK 0x01
1564
1565/* If NO fault is present, the following
1566 * fields are in effect
1567 * (FAULT remains as before) */
1568#define PAR_NOFAULT_SS_MASK 0x01
1569#define PAR_NOFAULT_MT_MASK 0x07
1570#define PAR_NOFAULT_SH_MASK 0x01
1571#define PAR_NOFAULT_NS_MASK 0x01
1572#define PAR_NOFAULT_NOS_MASK 0x01
1573#define PAR_NPFAULT_PA_MASK 0x000FFFFF
1574
1575
1576/* PRRR */
1577#define MTC0_MASK 0x03
1578#define MTC1_MASK 0x03
1579#define MTC2_MASK 0x03
1580#define MTC3_MASK 0x03
1581#define MTC4_MASK 0x03
1582#define MTC5_MASK 0x03
1583#define MTC6_MASK 0x03
1584#define MTC7_MASK 0x03
1585#define SHDSH0_MASK 0x01
1586#define SHDSH1_MASK 0x01
1587#define SHNMSH0_MASK 0x01
1588#define SHNMSH1_MASK 0x01
1589#define NOS0_MASK 0x01
1590#define NOS1_MASK 0x01
1591#define NOS2_MASK 0x01
1592#define NOS3_MASK 0x01
1593#define NOS4_MASK 0x01
1594#define NOS5_MASK 0x01
1595#define NOS6_MASK 0x01
1596#define NOS7_MASK 0x01
1597
1598
1599/* RESUME */
1600#define TNR_MASK 0x01
1601
1602
1603/* SCTLR */
1604#define M_MASK 0x01
1605#define TRE_MASK 0x01
1606#define AFE_MASK 0x01
1607#define HAF_MASK 0x01
1608#define BE_MASK 0x01
1609#define AFFD_MASK 0x01
1610
1611
1612/* TLBIASID */
1613#define TLBIASID_ASID_MASK 0xFF
1614
1615
1616/* TLBIVA */
1617#define TLBIVA_ASID_MASK 0xFF
1618#define TLBIVA_VA_MASK 0x000FFFFF
1619
1620
1621/* TLBIVAA */
1622#define TLBIVAA_VA_MASK 0x000FFFFF
1623
1624
1625/* TLBLCKR */
1626#define LKE_MASK 0x01
1627#define TLBLCKR_TLBIALLCFG_MASK 0x01
1628#define TLBIASIDCFG_MASK 0x01
1629#define TLBIVAACFG_MASK 0x01
1630#define FLOOR_MASK 0xFF
1631#define VICTIM_MASK 0xFF
1632
1633
1634/* TTBCR */
1635#define N_MASK 0x07
1636#define PD0_MASK 0x01
1637#define PD1_MASK 0x01
1638
1639
1640/* TTBR0 */
1641#define TTBR0_IRGNH_MASK 0x01
1642#define TTBR0_SH_MASK 0x01
1643#define TTBR0_ORGN_MASK 0x03
1644#define TTBR0_NOS_MASK 0x01
1645#define TTBR0_IRGNL_MASK 0x01
1646#define TTBR0_PA_MASK 0x0003FFFF
1647
1648
1649/* TTBR1 */
1650#define TTBR1_IRGNH_MASK 0x01
1651#define TTBR1_SH_MASK 0x01
1652#define TTBR1_ORGN_MASK 0x03
1653#define TTBR1_NOS_MASK 0x01
1654#define TTBR1_IRGNL_MASK 0x01
1655#define TTBR1_PA_MASK 0x0003FFFF
1656
1657
1658/* V2PSR */
1659#define HIT_MASK 0x01
1660#define INDEX_MASK 0xFF
1661
1662
1663/* V2Pxx */
1664#define V2Pxx_INDEX_MASK 0xFF
1665#define V2Pxx_VA_MASK 0x000FFFFF
1666
1667
1668/* Context Register Shifts */
1669/* ACTLR */
1670#define CFERE_SHIFT 0
1671#define CFEIE_SHIFT 1
1672#define PTSHCFG_SHIFT 2
1673#define RCOSH_SHIFT 4
1674#define RCISH_SHIFT 5
1675#define RCNSH_SHIFT 6
1676#define PRIVCFG_SHIFT 8
1677#define DNA_SHIFT 10
1678#define DNLV2PA_SHIFT 11
1679#define TLBMCFG_SHIFT 12
1680#define CFCFG_SHIFT 14
1681#define TIPCF_SHIFT 15
1682#define V2PCFG_SHIFT 16
1683#define HUME_SHIFT 18
1684#define PTMTCFG_SHIFT 20
1685#define PTMEMTYPE_SHIFT 21
1686
1687
1688/* BFBCR */
1689#define BFBDFE_SHIFT 0
1690#define BFBSFE_SHIFT 1
1691#define SFVS_SHIFT 2
1692#define FLVIC_SHIFT 4
1693#define SLVIC_SHIFT 8
1694
1695
1696/* CONTEXTIDR */
1697#define CONTEXTIDR_ASID_SHIFT 0
1698#define PROCID_SHIFT 8
1699
1700
1701/* FSR */
1702#define TF_SHIFT 1
1703#define AFF_SHIFT 2
1704#define APF_SHIFT 3
1705#define TLBMF_SHIFT 4
1706#define HTWDEEF_SHIFT 5
1707#define HTWSEEF_SHIFT 6
1708#define MHF_SHIFT 7
1709#define SL_SHIFT 16
1710#define SS_SHIFT 30
1711#define MULTI_SHIFT 31
1712
1713
1714/* FSYNR0 */
1715#define AMID_SHIFT 0
1716#define APID_SHIFT 8
1717#define ABID_SHIFT 13
1718#define ATID_SHIFT 24
1719
1720
1721/* FSYNR1 */
1722#define AMEMTYPE_SHIFT 0
1723#define ASHARED_SHIFT 3
1724#define AINNERSHARED_SHIFT 4
1725#define APRIV_SHIFT 5
1726#define APROTNS_SHIFT 6
1727#define AINST_SHIFT 7
1728#define AWRITE_SHIFT 8
1729#define ABURST_SHIFT 10
1730#define ALEN_SHIFT 12
1731#define FSYNR1_ASIZE_SHIFT 16
1732#define ALOCK_SHIFT 20
1733#define AFULL_SHIFT 24
1734
1735
1736/* NMRR */
1737#define ICPC0_SHIFT 0
1738#define ICPC1_SHIFT 2
1739#define ICPC2_SHIFT 4
1740#define ICPC3_SHIFT 6
1741#define ICPC4_SHIFT 8
1742#define ICPC5_SHIFT 10
1743#define ICPC6_SHIFT 12
1744#define ICPC7_SHIFT 14
1745#define OCPC0_SHIFT 16
1746#define OCPC1_SHIFT 18
1747#define OCPC2_SHIFT 20
1748#define OCPC3_SHIFT 22
1749#define OCPC4_SHIFT 24
1750#define OCPC5_SHIFT 26
1751#define OCPC6_SHIFT 28
1752#define OCPC7_SHIFT 30
1753
1754
1755/* PAR */
1756#define FAULT_SHIFT 0
1757/* If a fault is present, these are the
1758same as the fault fields in the FAR */
1759#define FAULT_TF_SHIFT 1
1760#define FAULT_AFF_SHIFT 2
1761#define FAULT_APF_SHIFT 3
1762#define FAULT_TLBMF_SHIFT 4
1763#define FAULT_HTWDEEF_SHIFT 5
1764#define FAULT_HTWSEEF_SHIFT 6
1765#define FAULT_MHF_SHIFT 7
1766#define FAULT_SL_SHIFT 16
1767#define FAULT_SS_SHIFT 30
1768
1769/* If NO fault is present, the following
1770 * fields are in effect
1771 * (FAULT remains as before) */
1772#define PAR_NOFAULT_SS_SHIFT 1
1773#define PAR_NOFAULT_MT_SHIFT 4
1774#define PAR_NOFAULT_SH_SHIFT 7
1775#define PAR_NOFAULT_NS_SHIFT 9
1776#define PAR_NOFAULT_NOS_SHIFT 10
1777#define PAR_NPFAULT_PA_SHIFT 12
1778
1779
1780/* PRRR */
1781#define MTC0_SHIFT 0
1782#define MTC1_SHIFT 2
1783#define MTC2_SHIFT 4
1784#define MTC3_SHIFT 6
1785#define MTC4_SHIFT 8
1786#define MTC5_SHIFT 10
1787#define MTC6_SHIFT 12
1788#define MTC7_SHIFT 14
1789#define SHDSH0_SHIFT 16
1790#define SHDSH1_SHIFT 17
1791#define SHNMSH0_SHIFT 18
1792#define SHNMSH1_SHIFT 19
1793#define NOS0_SHIFT 24
1794#define NOS1_SHIFT 25
1795#define NOS2_SHIFT 26
1796#define NOS3_SHIFT 27
1797#define NOS4_SHIFT 28
1798#define NOS5_SHIFT 29
1799#define NOS6_SHIFT 30
1800#define NOS7_SHIFT 31
1801
1802
1803/* RESUME */
1804#define TNR_SHIFT 0
1805
1806
1807/* SCTLR */
1808#define M_SHIFT 0
1809#define TRE_SHIFT 1
1810#define AFE_SHIFT 2
1811#define HAF_SHIFT 3
1812#define BE_SHIFT 4
1813#define AFFD_SHIFT 5
1814
1815
1816/* TLBIASID */
1817#define TLBIASID_ASID_SHIFT 0
1818
1819
1820/* TLBIVA */
1821#define TLBIVA_ASID_SHIFT 0
1822#define TLBIVA_VA_SHIFT 12
1823
1824
1825/* TLBIVAA */
1826#define TLBIVAA_VA_SHIFT 12
1827
1828
1829/* TLBLCKR */
1830#define LKE_SHIFT 0
1831#define TLBLCKR_TLBIALLCFG_SHIFT 1
1832#define TLBIASIDCFG_SHIFT 2
1833#define TLBIVAACFG_SHIFT 3
1834#define FLOOR_SHIFT 8
1835#define VICTIM_SHIFT 8
1836
1837
1838/* TTBCR */
1839#define N_SHIFT 3
1840#define PD0_SHIFT 4
1841#define PD1_SHIFT 5
1842
1843
1844/* TTBR0 */
1845#define TTBR0_IRGNH_SHIFT 0
1846#define TTBR0_SH_SHIFT 1
1847#define TTBR0_ORGN_SHIFT 3
1848#define TTBR0_NOS_SHIFT 5
1849#define TTBR0_IRGNL_SHIFT 6
1850#define TTBR0_PA_SHIFT 14
1851
1852
1853/* TTBR1 */
1854#define TTBR1_IRGNH_SHIFT 0
1855#define TTBR1_SH_SHIFT 1
1856#define TTBR1_ORGN_SHIFT 3
1857#define TTBR1_NOS_SHIFT 5
1858#define TTBR1_IRGNL_SHIFT 6
1859#define TTBR1_PA_SHIFT 14
1860
1861
1862/* V2PSR */
1863#define HIT_SHIFT 0
1864#define INDEX_SHIFT 8
1865
1866
1867/* V2Pxx */
1868#define V2Pxx_INDEX_SHIFT 0
1869#define V2Pxx_VA_SHIFT 12
1870
1871#endif
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
new file mode 100644
index 000000000000..f71747db3bee
--- /dev/null
+++ b/arch/arm/mach-msm/iommu.c
@@ -0,0 +1,597 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/errno.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/list.h>
26#include <linux/spinlock.h>
27#include <linux/slab.h>
28#include <linux/iommu.h>
29
30#include <asm/cacheflush.h>
31#include <asm/sizes.h>
32
33#include <mach/iommu_hw-8xxx.h>
34#include <mach/iommu.h>
35
36DEFINE_SPINLOCK(msm_iommu_lock);
37
38struct msm_priv {
39 unsigned long *pgtable;
40 struct list_head list_attached;
41};
42
43static void __flush_iotlb(struct iommu_domain *domain)
44{
45 struct msm_priv *priv = domain->priv;
46 struct msm_iommu_drvdata *iommu_drvdata;
47 struct msm_iommu_ctx_drvdata *ctx_drvdata;
48
49#ifndef CONFIG_IOMMU_PGTABLES_L2
50 unsigned long *fl_table = priv->pgtable;
51 int i;
52
53 dmac_flush_range(fl_table, fl_table + SZ_16K);
54
55 for (i = 0; i < NUM_FL_PTE; i++)
56 if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
57 void *sl_table = __va(fl_table[i] & FL_BASE_MASK);
58 dmac_flush_range(sl_table, sl_table + SZ_4K);
59 }
60#endif
61
62 list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
63 if (!ctx_drvdata->pdev || !ctx_drvdata->pdev->dev.parent)
64 BUG();
65
66 iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
67 SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0);
68 }
69}
70
71static void __reset_context(void __iomem *base, int ctx)
72{
73 SET_BPRCOSH(base, ctx, 0);
74 SET_BPRCISH(base, ctx, 0);
75 SET_BPRCNSH(base, ctx, 0);
76 SET_BPSHCFG(base, ctx, 0);
77 SET_BPMTCFG(base, ctx, 0);
78 SET_ACTLR(base, ctx, 0);
79 SET_SCTLR(base, ctx, 0);
80 SET_FSRRESTORE(base, ctx, 0);
81 SET_TTBR0(base, ctx, 0);
82 SET_TTBR1(base, ctx, 0);
83 SET_TTBCR(base, ctx, 0);
84 SET_BFBCR(base, ctx, 0);
85 SET_PAR(base, ctx, 0);
86 SET_FAR(base, ctx, 0);
87 SET_CTX_TLBIALL(base, ctx, 0);
88 SET_TLBFLPTER(base, ctx, 0);
89 SET_TLBSLPTER(base, ctx, 0);
90 SET_TLBLKCR(base, ctx, 0);
91 SET_PRRR(base, ctx, 0);
92 SET_NMRR(base, ctx, 0);
93 SET_CONTEXTIDR(base, ctx, 0);
94}
95
96static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
97{
98 __reset_context(base, ctx);
99
100 /* Set up HTW mode */
101 /* TLB miss configuration: perform HTW on miss */
102 SET_TLBMCFG(base, ctx, 0x3);
103
104 /* V2P configuration: HTW for access */
105 SET_V2PCFG(base, ctx, 0x3);
106
107 SET_TTBCR(base, ctx, 0);
108 SET_TTBR0_PA(base, ctx, (pgtable >> 14));
109
110 /* Invalidate the TLB for this context */
111 SET_CTX_TLBIALL(base, ctx, 0);
112
113 /* Set interrupt number to "secure" interrupt */
114 SET_IRPTNDX(base, ctx, 0);
115
116 /* Enable context fault interrupt */
117 SET_CFEIE(base, ctx, 1);
118
119 /* Stall access on a context fault and let the handler deal with it */
120 SET_CFCFG(base, ctx, 1);
121
122 /* Redirect all cacheable requests to L2 slave port. */
123 SET_RCISH(base, ctx, 1);
124 SET_RCOSH(base, ctx, 1);
125 SET_RCNSH(base, ctx, 1);
126
127 /* Turn on TEX Remap */
128 SET_TRE(base, ctx, 1);
129
130 /* Do not configure PRRR / NMRR on the IOMMU for now. We will assume
131 * TEX class 0 for everything until attributes are properly worked out
132 */
133 SET_PRRR(base, ctx, 0);
134 SET_NMRR(base, ctx, 0);
135
136 /* Turn on BFB prefetch */
137 SET_BFBDFE(base, ctx, 1);
138
139#ifdef CONFIG_IOMMU_PGTABLES_L2
140 /* Configure page tables as inner-cacheable and shareable to reduce
141 * the TLB miss penalty.
142 */
143 SET_TTBR0_SH(base, ctx, 1);
144 SET_TTBR1_SH(base, ctx, 1);
145
146 SET_TTBR0_NOS(base, ctx, 1);
147 SET_TTBR1_NOS(base, ctx, 1);
148
149 SET_TTBR0_IRGNH(base, ctx, 0); /* WB, WA */
150 SET_TTBR0_IRGNL(base, ctx, 1);
151
152 SET_TTBR1_IRGNH(base, ctx, 0); /* WB, WA */
153 SET_TTBR1_IRGNL(base, ctx, 1);
154
155 SET_TTBR0_ORGN(base, ctx, 1); /* WB, WA */
156 SET_TTBR1_ORGN(base, ctx, 1); /* WB, WA */
157#endif
158
159 /* Enable the MMU */
160 SET_M(base, ctx, 1);
161}
162
163static int msm_iommu_domain_init(struct iommu_domain *domain)
164{
165 struct msm_priv *priv = kzalloc(sizeof(*priv), GFP_KERNEL);
166
167 if (!priv)
168 goto fail_nomem;
169
170 INIT_LIST_HEAD(&priv->list_attached);
171 priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL,
172 get_order(SZ_16K));
173
174 if (!priv->pgtable)
175 goto fail_nomem;
176
177 memset(priv->pgtable, 0, SZ_16K);
178 domain->priv = priv;
179 return 0;
180
181fail_nomem:
182 kfree(priv);
183 return -ENOMEM;
184}
185
186static void msm_iommu_domain_destroy(struct iommu_domain *domain)
187{
188 struct msm_priv *priv;
189 unsigned long flags;
190 unsigned long *fl_table;
191 int i;
192
193 spin_lock_irqsave(&msm_iommu_lock, flags);
194 priv = domain->priv;
195 domain->priv = NULL;
196
197 if (priv) {
198 fl_table = priv->pgtable;
199
200 for (i = 0; i < NUM_FL_PTE; i++)
201 if ((fl_table[i] & 0x03) == FL_TYPE_TABLE)
202 free_page((unsigned long) __va(((fl_table[i]) &
203 FL_BASE_MASK)));
204
205 free_pages((unsigned long)priv->pgtable, get_order(SZ_16K));
206 priv->pgtable = NULL;
207 }
208
209 kfree(priv);
210 spin_unlock_irqrestore(&msm_iommu_lock, flags);
211}
212
213static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
214{
215 struct msm_priv *priv;
216 struct msm_iommu_ctx_dev *ctx_dev;
217 struct msm_iommu_drvdata *iommu_drvdata;
218 struct msm_iommu_ctx_drvdata *ctx_drvdata;
219 struct msm_iommu_ctx_drvdata *tmp_drvdata;
220 int ret = 0;
221 unsigned long flags;
222
223 spin_lock_irqsave(&msm_iommu_lock, flags);
224
225 priv = domain->priv;
226
227 if (!priv || !dev) {
228 ret = -EINVAL;
229 goto fail;
230 }
231
232 iommu_drvdata = dev_get_drvdata(dev->parent);
233 ctx_drvdata = dev_get_drvdata(dev);
234 ctx_dev = dev->platform_data;
235
236 if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) {
237 ret = -EINVAL;
238 goto fail;
239 }
240
241 list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm)
242 if (tmp_drvdata == ctx_drvdata) {
243 ret = -EBUSY;
244 goto fail;
245 }
246
247 __program_context(iommu_drvdata->base, ctx_dev->num,
248 __pa(priv->pgtable));
249
250 list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
251 __flush_iotlb(domain);
252
253fail:
254 spin_unlock_irqrestore(&msm_iommu_lock, flags);
255 return ret;
256}
257
258static void msm_iommu_detach_dev(struct iommu_domain *domain,
259 struct device *dev)
260{
261 struct msm_priv *priv;
262 struct msm_iommu_ctx_dev *ctx_dev;
263 struct msm_iommu_drvdata *iommu_drvdata;
264 struct msm_iommu_ctx_drvdata *ctx_drvdata;
265 unsigned long flags;
266
267 spin_lock_irqsave(&msm_iommu_lock, flags);
268 priv = domain->priv;
269
270 if (!priv || !dev)
271 goto fail;
272
273 iommu_drvdata = dev_get_drvdata(dev->parent);
274 ctx_drvdata = dev_get_drvdata(dev);
275 ctx_dev = dev->platform_data;
276
277 if (!iommu_drvdata || !ctx_drvdata || !ctx_dev)
278 goto fail;
279
280 __flush_iotlb(domain);
281 __reset_context(iommu_drvdata->base, ctx_dev->num);
282 list_del_init(&ctx_drvdata->attached_elm);
283
284fail:
285 spin_unlock_irqrestore(&msm_iommu_lock, flags);
286}
287
288static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
289 phys_addr_t pa, int order, int prot)
290{
291 struct msm_priv *priv;
292 unsigned long flags;
293 unsigned long *fl_table;
294 unsigned long *fl_pte;
295 unsigned long fl_offset;
296 unsigned long *sl_table;
297 unsigned long *sl_pte;
298 unsigned long sl_offset;
299 size_t len = 0x1000UL << order;
300 int ret = 0;
301
302 spin_lock_irqsave(&msm_iommu_lock, flags);
303 priv = domain->priv;
304
305 if (!priv) {
306 ret = -EINVAL;
307 goto fail;
308 }
309
310 fl_table = priv->pgtable;
311
312 if (len != SZ_16M && len != SZ_1M &&
313 len != SZ_64K && len != SZ_4K) {
314 pr_debug("Bad size: %d\n", len);
315 ret = -EINVAL;
316 goto fail;
317 }
318
319 if (!fl_table) {
320 pr_debug("Null page table\n");
321 ret = -EINVAL;
322 goto fail;
323 }
324
325 fl_offset = FL_OFFSET(va); /* Upper 12 bits */
326 fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
327
328 if (len == SZ_16M) {
329 int i = 0;
330 for (i = 0; i < 16; i++)
331 *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION |
332 FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
333 FL_SHARED;
334 }
335
336 if (len == SZ_1M)
337 *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE |
338 FL_TYPE_SECT | FL_SHARED;
339
340 /* Need a 2nd level table */
341 if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) {
342 unsigned long *sl;
343 sl = (unsigned long *) __get_free_pages(GFP_KERNEL,
344 get_order(SZ_4K));
345
346 if (!sl) {
347 pr_debug("Could not allocate second level table\n");
348 ret = -ENOMEM;
349 goto fail;
350 }
351
352 memset(sl, 0, SZ_4K);
353 *fl_pte = ((((int)__pa(sl)) & FL_BASE_MASK) | FL_TYPE_TABLE);
354 }
355
356 sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
357 sl_offset = SL_OFFSET(va);
358 sl_pte = sl_table + sl_offset;
359
360
361 if (len == SZ_4K)
362 *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 |
363 SL_SHARED | SL_TYPE_SMALL;
364
365 if (len == SZ_64K) {
366 int i;
367
368 for (i = 0; i < 16; i++)
369 *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 |
370 SL_AP1 | SL_SHARED | SL_TYPE_LARGE;
371 }
372
373 __flush_iotlb(domain);
374fail:
375 spin_unlock_irqrestore(&msm_iommu_lock, flags);
376 return ret;
377}
378
379static int msm_iommu_unmap(struct iommu_domain *domain, unsigned long va,
380 int order)
381{
382 struct msm_priv *priv;
383 unsigned long flags;
384 unsigned long *fl_table;
385 unsigned long *fl_pte;
386 unsigned long fl_offset;
387 unsigned long *sl_table;
388 unsigned long *sl_pte;
389 unsigned long sl_offset;
390 size_t len = 0x1000UL << order;
391 int i, ret = 0;
392
393 spin_lock_irqsave(&msm_iommu_lock, flags);
394
395 priv = domain->priv;
396
397 if (!priv) {
398 ret = -ENODEV;
399 goto fail;
400 }
401
402 fl_table = priv->pgtable;
403
404 if (len != SZ_16M && len != SZ_1M &&
405 len != SZ_64K && len != SZ_4K) {
406 pr_debug("Bad length: %d\n", len);
407 ret = -EINVAL;
408 goto fail;
409 }
410
411 if (!fl_table) {
412 pr_debug("Null page table\n");
413 ret = -EINVAL;
414 goto fail;
415 }
416
417 fl_offset = FL_OFFSET(va); /* Upper 12 bits */
418 fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
419
420 if (*fl_pte == 0) {
421 pr_debug("First level PTE is 0\n");
422 ret = -ENODEV;
423 goto fail;
424 }
425
426 /* Unmap supersection */
427 if (len == SZ_16M)
428 for (i = 0; i < 16; i++)
429 *(fl_pte+i) = 0;
430
431 if (len == SZ_1M)
432 *fl_pte = 0;
433
434 sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
435 sl_offset = SL_OFFSET(va);
436 sl_pte = sl_table + sl_offset;
437
438 if (len == SZ_64K) {
439 for (i = 0; i < 16; i++)
440 *(sl_pte+i) = 0;
441 }
442
443 if (len == SZ_4K)
444 *sl_pte = 0;
445
446 if (len == SZ_4K || len == SZ_64K) {
447 int used = 0;
448
449 for (i = 0; i < NUM_SL_PTE; i++)
450 if (sl_table[i])
451 used = 1;
452 if (!used) {
453 free_page((unsigned long)sl_table);
454 *fl_pte = 0;
455 }
456 }
457
458 __flush_iotlb(domain);
459fail:
460 spin_unlock_irqrestore(&msm_iommu_lock, flags);
461 return ret;
462}
463
464static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
465 unsigned long va)
466{
467 struct msm_priv *priv;
468 struct msm_iommu_drvdata *iommu_drvdata;
469 struct msm_iommu_ctx_drvdata *ctx_drvdata;
470 unsigned int par;
471 unsigned long flags;
472 void __iomem *base;
473 phys_addr_t ret = 0;
474 int ctx;
475
476 spin_lock_irqsave(&msm_iommu_lock, flags);
477
478 priv = domain->priv;
479 if (list_empty(&priv->list_attached))
480 goto fail;
481
482 ctx_drvdata = list_entry(priv->list_attached.next,
483 struct msm_iommu_ctx_drvdata, attached_elm);
484 iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
485
486 base = iommu_drvdata->base;
487 ctx = ctx_drvdata->num;
488
489 /* Invalidate context TLB */
490 SET_CTX_TLBIALL(base, ctx, 0);
491 SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT);
492
493 if (GET_FAULT(base, ctx))
494 goto fail;
495
496 par = GET_PAR(base, ctx);
497
498 /* We are dealing with a supersection */
499 if (GET_NOFAULT_SS(base, ctx))
500 ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
501 else /* Upper 20 bits from PAR, lower 12 from VA */
502 ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
503
504fail:
505 spin_unlock_irqrestore(&msm_iommu_lock, flags);
506 return ret;
507}
508
509static int msm_iommu_domain_has_cap(struct iommu_domain *domain,
510 unsigned long cap)
511{
512 return 0;
513}
514
515static void print_ctx_regs(void __iomem *base, int ctx)
516{
517 unsigned int fsr = GET_FSR(base, ctx);
518 pr_err("FAR = %08x PAR = %08x\n",
519 GET_FAR(base, ctx), GET_PAR(base, ctx));
520 pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
521 (fsr & 0x02) ? "TF " : "",
522 (fsr & 0x04) ? "AFF " : "",
523 (fsr & 0x08) ? "APF " : "",
524 (fsr & 0x10) ? "TLBMF " : "",
525 (fsr & 0x20) ? "HTWDEEF " : "",
526 (fsr & 0x40) ? "HTWSEEF " : "",
527 (fsr & 0x80) ? "MHF " : "",
528 (fsr & 0x10000) ? "SL " : "",
529 (fsr & 0x40000000) ? "SS " : "",
530 (fsr & 0x80000000) ? "MULTI " : "");
531
532 pr_err("FSYNR0 = %08x FSYNR1 = %08x\n",
533 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
534 pr_err("TTBR0 = %08x TTBR1 = %08x\n",
535 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
536 pr_err("SCTLR = %08x ACTLR = %08x\n",
537 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
538 pr_err("PRRR = %08x NMRR = %08x\n",
539 GET_PRRR(base, ctx), GET_NMRR(base, ctx));
540}
541
542irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
543{
544 struct msm_iommu_drvdata *drvdata = dev_id;
545 void __iomem *base;
546 unsigned int fsr = 0;
547 int ncb = 0, i = 0;
548
549 spin_lock(&msm_iommu_lock);
550
551 if (!drvdata) {
552 pr_err("Invalid device ID in context interrupt handler\n");
553 goto fail;
554 }
555
556 base = drvdata->base;
557
558 pr_err("===== WOAH! =====\n");
559 pr_err("Unexpected IOMMU page fault!\n");
560 pr_err("base = %08x\n", (unsigned int) base);
561
562 ncb = GET_NCB(base)+1;
563 for (i = 0; i < ncb; i++) {
564 fsr = GET_FSR(base, i);
565 if (fsr) {
566 pr_err("Fault occurred in context %d.\n", i);
567 pr_err("Interesting registers:\n");
568 print_ctx_regs(base, i);
569 SET_FSR(base, i, 0x4000000F);
570 }
571 }
572fail:
573 spin_unlock(&msm_iommu_lock);
574 return 0;
575}
576
577static struct iommu_ops msm_iommu_ops = {
578 .domain_init = msm_iommu_domain_init,
579 .domain_destroy = msm_iommu_domain_destroy,
580 .attach_dev = msm_iommu_attach_dev,
581 .detach_dev = msm_iommu_detach_dev,
582 .map = msm_iommu_map,
583 .unmap = msm_iommu_unmap,
584 .iova_to_phys = msm_iommu_iova_to_phys,
585 .domain_has_cap = msm_iommu_domain_has_cap
586};
587
588static int msm_iommu_init(void)
589{
590 register_iommu(&msm_iommu_ops);
591 return 0;
592}
593
594subsys_initcall(msm_iommu_init);
595
596MODULE_LICENSE("GPL v2");
597MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 19:10:24 -0500