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authorGrant Likely <grant.likely@secretlab.ca>2010-05-25 02:38:26 -0400
committerGrant Likely <grant.likely@secretlab.ca>2010-05-25 02:38:26 -0400
commitb1e50ebcf24668e57f058deb48b0704b5391ed0f (patch)
tree17e1b69b249d0738317b732186340c9dd053f1a1 /arch/arm/mach-msm/include
parent0c2a2ae32793e3500a15a449612485f5d17dd431 (diff)
parent7e125f7b9cbfce4101191b8076d606c517a73066 (diff)
Merge remote branch 'origin' into secretlab/next-spi
Diffstat (limited to 'arch/arm/mach-msm/include')
-rw-r--r--arch/arm/mach-msm/include/mach/board.h14
-rw-r--r--arch/arm/mach-msm/include/mach/clk.h57
-rw-r--r--arch/arm/mach-msm/include/mach/dma.h34
-rw-r--r--arch/arm/mach-msm/include/mach/gpio.h142
-rw-r--r--arch/arm/mach-msm/include/mach/io.h5
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-7x00.h75
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-7x30.h170
-rw-r--r--arch/arm/mach-msm/include/mach/irqs-8x50.h105
-rw-r--r--arch/arm/mach-msm/include/mach/irqs.h81
-rw-r--r--arch/arm/mach-msm/include/mach/memory.h8
-rw-r--r--arch/arm/mach-msm/include/mach/msm_fb.h147
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x00.h139
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-7x30.h122
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x50.h147
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap.h95
-rw-r--r--arch/arm/mach-msm/include/mach/msm_smd.h109
-rw-r--r--arch/arm/mach-msm/include/mach/sirc.h115
-rw-r--r--arch/arm/mach-msm/include/mach/system.h5
-rw-r--r--arch/arm/mach-msm/include/mach/vreg.h2
19 files changed, 1398 insertions, 174 deletions
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 264d62e519f3..e302fbdc439b 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -21,18 +21,24 @@
21 21
22/* platform device data structures */ 22/* platform device data structures */
23 23
24struct msm_mddi_platform_data 24struct msm_acpu_clock_platform_data
25{ 25{
26 void (*panel_power)(int on); 26 uint32_t acpu_switch_time_us;
27 unsigned has_vsync_irq:1; 27 uint32_t max_speed_delta_khz;
28 uint32_t vdd_switch_time_us;
29 unsigned long power_collapse_khz;
30 unsigned long wait_for_irq_khz;
28}; 31};
29 32
33struct clk;
34
30/* common init routines for use by arch/arm/mach-msm/board-*.c */ 35/* common init routines for use by arch/arm/mach-msm/board-*.c */
31 36
32void __init msm_add_devices(void); 37void __init msm_add_devices(void);
33void __init msm_map_common_io(void); 38void __init msm_map_common_io(void);
34void __init msm_init_irq(void); 39void __init msm_init_irq(void);
35void __init msm_init_gpio(void); 40void __init msm_init_gpio(void);
36void __init msm_clock_init(void); 41void __init msm_clock_init(struct clk *clock_tbl, unsigned num_clocks);
42void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *);
37 43
38#endif 44#endif
diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h
new file mode 100644
index 000000000000..c05ca40478c7
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/clk.h
@@ -0,0 +1,57 @@
1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29#ifndef __MACH_CLK_H
30#define __MACH_CLK_H
31
32/* Magic rate value for use with PM QOS to request the board's maximum
33 * supported AXI rate. PM QOS will only pass positive s32 rate values
34 * through to the clock driver, so INT_MAX is used.
35 */
36#define MSM_AXI_MAX_FREQ LONG_MAX
37
38enum clk_reset_action {
39 CLK_RESET_DEASSERT = 0,
40 CLK_RESET_ASSERT = 1
41};
42
43struct clk;
44
45/* Rate is minimum clock rate in Hz */
46int clk_set_min_rate(struct clk *clk, unsigned long rate);
47
48/* Rate is maximum clock rate in Hz */
49int clk_set_max_rate(struct clk *clk, unsigned long rate);
50
51/* Assert/Deassert reset to a hardware block associated with a clock */
52int clk_reset(struct clk *clk, enum clk_reset_action action);
53
54/* Set clock-specific configuration parameters */
55int clk_set_flags(struct clk *clk, unsigned long flags);
56
57#endif
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 5ab5bdffab07..00f9bbfadbe6 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -28,6 +28,8 @@ struct msm_dmov_cmd {
28 void (*complete_func)(struct msm_dmov_cmd *cmd, 28 void (*complete_func)(struct msm_dmov_cmd *cmd,
29 unsigned int result, 29 unsigned int result,
30 struct msm_dmov_errdata *err); 30 struct msm_dmov_errdata *err);
31 void (*execute_func)(struct msm_dmov_cmd *cmd);
32 void *data;
31}; 33};
32 34
33void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd); 35void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
@@ -41,40 +43,42 @@ int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
41#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2)) 43#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
42#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2)) 44#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
43 45
44/* only security domain 3 is available to the ARM11 46#if defined(CONFIG_ARCH_MSM7X30)
45 * SD0 -> mARM trusted, SD1 -> mARM nontrusted, SD2 -> aDSP, SD3 -> aARM 47#define DMOV_SD_AARM DMOV_SD2
46 */ 48#else
49#define DMOV_SD_AARM DMOV_SD3
50#endif
47 51
48#define DMOV_CMD_PTR(ch) DMOV_SD3(0x000, ch) 52#define DMOV_CMD_PTR(ch) DMOV_SD_AARM(0x000, ch)
49#define DMOV_CMD_LIST (0 << 29) /* does not work */ 53#define DMOV_CMD_LIST (0 << 29) /* does not work */
50#define DMOV_CMD_PTR_LIST (1 << 29) /* works */ 54#define DMOV_CMD_PTR_LIST (1 << 29) /* works */
51#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */ 55#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */
52#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */ 56#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */
53#define DMOV_CMD_ADDR(addr) ((addr) >> 3) 57#define DMOV_CMD_ADDR(addr) ((addr) >> 3)
54 58
55#define DMOV_RSLT(ch) DMOV_SD3(0x040, ch) 59#define DMOV_RSLT(ch) DMOV_SD_AARM(0x040, ch)
56#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */ 60#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */
57#define DMOV_RSLT_ERROR (1 << 3) 61#define DMOV_RSLT_ERROR (1 << 3)
58#define DMOV_RSLT_FLUSH (1 << 2) 62#define DMOV_RSLT_FLUSH (1 << 2)
59#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */ 63#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */
60#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */ 64#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */
61 65
62#define DMOV_FLUSH0(ch) DMOV_SD3(0x080, ch) 66#define DMOV_FLUSH0(ch) DMOV_SD_AARM(0x080, ch)
63#define DMOV_FLUSH1(ch) DMOV_SD3(0x0C0, ch) 67#define DMOV_FLUSH1(ch) DMOV_SD_AARM(0x0C0, ch)
64#define DMOV_FLUSH2(ch) DMOV_SD3(0x100, ch) 68#define DMOV_FLUSH2(ch) DMOV_SD_AARM(0x100, ch)
65#define DMOV_FLUSH3(ch) DMOV_SD3(0x140, ch) 69#define DMOV_FLUSH3(ch) DMOV_SD_AARM(0x140, ch)
66#define DMOV_FLUSH4(ch) DMOV_SD3(0x180, ch) 70#define DMOV_FLUSH4(ch) DMOV_SD_AARM(0x180, ch)
67#define DMOV_FLUSH5(ch) DMOV_SD3(0x1C0, ch) 71#define DMOV_FLUSH5(ch) DMOV_SD_AARM(0x1C0, ch)
68 72
69#define DMOV_STATUS(ch) DMOV_SD3(0x200, ch) 73#define DMOV_STATUS(ch) DMOV_SD_AARM(0x200, ch)
70#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29)) 74#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29))
71#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3) 75#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3)
72#define DMOV_STATUS_RSLT_VALID (1 << 1) 76#define DMOV_STATUS_RSLT_VALID (1 << 1)
73#define DMOV_STATUS_CMD_PTR_RDY (1 << 0) 77#define DMOV_STATUS_CMD_PTR_RDY (1 << 0)
74 78
75#define DMOV_ISR DMOV_SD3(0x380, 0) 79#define DMOV_ISR DMOV_SD_AARM(0x380, 0)
76 80
77#define DMOV_CONFIG(ch) DMOV_SD3(0x300, ch) 81#define DMOV_CONFIG(ch) DMOV_SD_AARM(0x300, ch)
78#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2) 82#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
79#define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1) 83#define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1)
80#define DMOV_CONFIG_IRQ_EN (1 << 0) 84#define DMOV_CONFIG_IRQ_EN (1 << 0)
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
new file mode 100644
index 000000000000..262b441b4374
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/gpio.h
@@ -0,0 +1,142 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
4 * Author: Mike Lockwood <lockwood@android.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16#ifndef __ASM_ARCH_MSM_GPIO_H
17#define __ASM_ARCH_MSM_GPIO_H
18
19/**
20 * struct msm_gpio - GPIO pin description
21 * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()
22 * @label - textual label
23 *
24 * Usually, GPIO's are operated by sets.
25 * This struct accumulate all GPIO information in single source
26 * and facilitete group operations provided by msm_gpios_xxx()
27 */
28struct msm_gpio {
29 u32 gpio_cfg;
30 const char *label;
31};
32
33/**
34 * msm_gpios_request_enable() - request and enable set of GPIOs
35 *
36 * Request and configure set of GPIO's
37 * In case of error, all operations rolled back.
38 * Return error code.
39 *
40 * @table: GPIO table
41 * @size: number of entries in @table
42 */
43int msm_gpios_request_enable(const struct msm_gpio *table, int size);
44
45/**
46 * msm_gpios_disable_free() - disable and free set of GPIOs
47 *
48 * @table: GPIO table
49 * @size: number of entries in @table
50 */
51void msm_gpios_disable_free(const struct msm_gpio *table, int size);
52
53/**
54 * msm_gpios_request() - request set of GPIOs
55 * In case of error, all operations rolled back.
56 * Return error code.
57 *
58 * @table: GPIO table
59 * @size: number of entries in @table
60 */
61int msm_gpios_request(const struct msm_gpio *table, int size);
62
63/**
64 * msm_gpios_free() - free set of GPIOs
65 *
66 * @table: GPIO table
67 * @size: number of entries in @table
68 */
69void msm_gpios_free(const struct msm_gpio *table, int size);
70
71/**
72 * msm_gpios_enable() - enable set of GPIOs
73 * In case of error, all operations rolled back.
74 * Return error code.
75 *
76 * @table: GPIO table
77 * @size: number of entries in @table
78 */
79int msm_gpios_enable(const struct msm_gpio *table, int size);
80
81/**
82 * msm_gpios_disable() - disable set of GPIOs
83 *
84 * @table: GPIO table
85 * @size: number of entries in @table
86 */
87void msm_gpios_disable(const struct msm_gpio *table, int size);
88
89/* GPIO TLMM (Top Level Multiplexing) Definitions */
90
91/* GPIO TLMM: Function -- GPIO specific */
92
93/* GPIO TLMM: Direction */
94enum {
95 GPIO_INPUT,
96 GPIO_OUTPUT,
97};
98
99/* GPIO TLMM: Pullup/Pulldown */
100enum {
101 GPIO_NO_PULL,
102 GPIO_PULL_DOWN,
103 GPIO_KEEPER,
104 GPIO_PULL_UP,
105};
106
107/* GPIO TLMM: Drive Strength */
108enum {
109 GPIO_2MA,
110 GPIO_4MA,
111 GPIO_6MA,
112 GPIO_8MA,
113 GPIO_10MA,
114 GPIO_12MA,
115 GPIO_14MA,
116 GPIO_16MA,
117};
118
119enum {
120 GPIO_ENABLE,
121 GPIO_DISABLE,
122};
123
124#define GPIO_CFG(gpio, func, dir, pull, drvstr) \
125 ((((gpio) & 0x3FF) << 4) | \
126 ((func) & 0xf) | \
127 (((dir) & 0x1) << 14) | \
128 (((pull) & 0x3) << 15) | \
129 (((drvstr) & 0xF) << 17))
130
131/**
132 * extract GPIO pin from bit-field used for gpio_tlmm_config
133 */
134#define GPIO_PIN(gpio_cfg) (((gpio_cfg) >> 4) & 0x3ff)
135#define GPIO_FUNC(gpio_cfg) (((gpio_cfg) >> 0) & 0xf)
136#define GPIO_DIR(gpio_cfg) (((gpio_cfg) >> 14) & 0x1)
137#define GPIO_PULL(gpio_cfg) (((gpio_cfg) >> 15) & 0x3)
138#define GPIO_DRVSTR(gpio_cfg) (((gpio_cfg) >> 17) & 0xf)
139
140int gpio_tlmm_config(unsigned config, unsigned disable);
141
142#endif /* __ASM_ARCH_MSM_GPIO_H */
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index aab964591db4..c35b29f9ac0f 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -26,4 +26,9 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
26#define __io(a) __typesafe_io(a) 26#define __io(a) __typesafe_io(a)
27#define __mem_pci(a) (a) 27#define __mem_pci(a) (a)
28 28
29void msm_map_qsd8x50_io(void);
30void msm_map_msm7x30_io(void);
31
32extern unsigned int msm_shared_ram_phys;
33
29#endif 34#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-7x00.h b/arch/arm/mach-msm/include/mach/irqs-7x00.h
new file mode 100644
index 000000000000..f1fe70612fe9
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-7x00.h
@@ -0,0 +1,75 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 */
6
7#ifndef __ASM_ARCH_MSM_IRQS_7X00_H
8#define __ASM_ARCH_MSM_IRQS_7X00_H
9
10/* MSM ARM11 Interrupt Numbers */
11/* See 80-VE113-1 A, pp219-221 */
12
13#define INT_A9_M2A_0 0
14#define INT_A9_M2A_1 1
15#define INT_A9_M2A_2 2
16#define INT_A9_M2A_3 3
17#define INT_A9_M2A_4 4
18#define INT_A9_M2A_5 5
19#define INT_A9_M2A_6 6
20#define INT_GP_TIMER_EXP 7
21#define INT_DEBUG_TIMER_EXP 8
22#define INT_UART1 9
23#define INT_UART2 10
24#define INT_UART3 11
25#define INT_UART1_RX 12
26#define INT_UART2_RX 13
27#define INT_UART3_RX 14
28#define INT_USB_OTG 15
29#define INT_MDDI_PRI 16
30#define INT_MDDI_EXT 17
31#define INT_MDDI_CLIENT 18
32#define INT_MDP 19
33#define INT_GRAPHICS 20
34#define INT_ADM_AARM 21
35#define INT_ADSP_A11 22
36#define INT_ADSP_A9_A11 23
37#define INT_SDC1_0 24
38#define INT_SDC1_1 25
39#define INT_SDC2_0 26
40#define INT_SDC2_1 27
41#define INT_KEYSENSE 28
42#define INT_TCHSCRN_SSBI 29
43#define INT_TCHSCRN1 30
44#define INT_TCHSCRN2 31
45
46#define INT_GPIO_GROUP1 (32 + 0)
47#define INT_GPIO_GROUP2 (32 + 1)
48#define INT_PWB_I2C (32 + 2)
49#define INT_SOFTRESET (32 + 3)
50#define INT_NAND_WR_ER_DONE (32 + 4)
51#define INT_NAND_OP_DONE (32 + 5)
52#define INT_PBUS_ARM11 (32 + 6)
53#define INT_AXI_MPU_SMI (32 + 7)
54#define INT_AXI_MPU_EBI1 (32 + 8)
55#define INT_AD_HSSD (32 + 9)
56#define INT_ARM11_PMU (32 + 10)
57#define INT_ARM11_DMA (32 + 11)
58#define INT_TSIF_IRQ (32 + 12)
59#define INT_UART1DM_IRQ (32 + 13)
60#define INT_UART1DM_RX (32 + 14)
61#define INT_USB_HS (32 + 15)
62#define INT_SDC3_0 (32 + 16)
63#define INT_SDC3_1 (32 + 17)
64#define INT_SDC4_0 (32 + 18)
65#define INT_SDC4_1 (32 + 19)
66#define INT_UART2DM_RX (32 + 20)
67#define INT_UART2DM_IRQ (32 + 21)
68
69/* 22-31 are reserved */
70
71#define NR_MSM_IRQS 64
72#define NR_GPIO_IRQS 122
73#define NR_BOARD_IRQS 64
74
75#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-7x30.h b/arch/arm/mach-msm/include/mach/irqs-7x30.h
new file mode 100644
index 000000000000..67c5396514fe
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-7x30.h
@@ -0,0 +1,170 @@
1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30#ifndef __ASM_ARCH_MSM_IRQS_7X30_H
31#define __ASM_ARCH_MSM_IRQS_7X30_H
32
33/* MSM ACPU Interrupt Numbers */
34
35#define INT_DEBUG_TIMER_EXP 0
36#define INT_GPT0_TIMER_EXP 1
37#define INT_GPT1_TIMER_EXP 2
38#define INT_WDT0_ACCSCSSBARK 3
39#define INT_WDT1_ACCSCSSBARK 4
40#define INT_AVS_SVIC 5
41#define INT_AVS_SVIC_SW_DONE 6
42#define INT_SC_DBG_RX_FULL 7
43#define INT_SC_DBG_TX_EMPTY 8
44#define INT_ARM11_PM 9
45#define INT_AVS_REQ_DOWN 10
46#define INT_AVS_REQ_UP 11
47#define INT_SC_ACG 12
48/* SCSS_VICFIQSTS0[13:15] are RESERVED */
49#define INT_L2_SVICCPUIRPTREQ 16
50#define INT_L2_SVICDMANSIRPTREQ 17
51#define INT_L2_SVICDMASIRPTREQ 18
52#define INT_L2_SVICSLVIRPTREQ 19
53#define INT_AD5A_MPROC_APPS_0 20
54#define INT_AD5A_MPROC_APPS_1 21
55#define INT_A9_M2A_0 22
56#define INT_A9_M2A_1 23
57#define INT_A9_M2A_2 24
58#define INT_A9_M2A_3 25
59#define INT_A9_M2A_4 26
60#define INT_A9_M2A_5 27
61#define INT_A9_M2A_6 28
62#define INT_A9_M2A_7 29
63#define INT_A9_M2A_8 30
64#define INT_A9_M2A_9 31
65
66#define INT_AXI_EBI1_SC (32 + 0)
67#define INT_IMEM_ERR (32 + 1)
68#define INT_AXI_EBI0_SC (32 + 2)
69#define INT_PBUS_SC_IRQC (32 + 3)
70#define INT_PERPH_BUS_BPM (32 + 4)
71#define INT_CC_TEMP_SENSE (32 + 5)
72#define INT_UXMC_EBI0 (32 + 6)
73#define INT_UXMC_EBI1 (32 + 7)
74#define INT_EBI2_OP_DONE (32 + 8)
75#define INT_EBI2_WR_ER_DONE (32 + 9)
76#define INT_TCSR_SPSS_CE (32 + 10)
77#define INT_EMDH (32 + 11)
78#define INT_PMDH (32 + 12)
79#define INT_MDC (32 + 13)
80#define INT_MIDI_TO_SUPSS (32 + 14)
81#define INT_LPA_2 (32 + 15)
82#define INT_GPIO_GROUP1_SECURE (32 + 16)
83#define INT_GPIO_GROUP2_SECURE (32 + 17)
84#define INT_GPIO_GROUP1 (32 + 18)
85#define INT_GPIO_GROUP2 (32 + 19)
86#define INT_MPRPH_SOFTRESET (32 + 20)
87#define INT_PWB_I2C (32 + 21)
88#define INT_PWB_I2C_2 (32 + 22)
89#define INT_TSSC_SAMPLE (32 + 23)
90#define INT_TSSC_PENUP (32 + 24)
91#define INT_TCHSCRN_SSBI (32 + 25)
92#define INT_FM_RDS (32 + 26)
93#define INT_KEYSENSE (32 + 27)
94#define INT_USB_OTG_HS (32 + 28)
95#define INT_USB_OTG_HS2 (32 + 29)
96#define INT_USB_OTG_HS3 (32 + 30)
97#define INT_CSI (32 + 31)
98
99#define INT_SPI_OUTPUT (64 + 0)
100#define INT_SPI_INPUT (64 + 1)
101#define INT_SPI_ERROR (64 + 2)
102#define INT_UART1 (64 + 3)
103#define INT_UART1_RX (64 + 4)
104#define INT_UART2 (64 + 5)
105#define INT_UART2_RX (64 + 6)
106#define INT_UART3 (64 + 7)
107#define INT_UART3_RX (64 + 8)
108#define INT_UART1DM_IRQ (64 + 9)
109#define INT_UART1DM_RX (64 + 10)
110#define INT_UART2DM_IRQ (64 + 11)
111#define INT_UART2DM_RX (64 + 12)
112#define INT_TSIF (64 + 13)
113#define INT_ADM_SC1 (64 + 14)
114#define INT_ADM_SC2 (64 + 15)
115#define INT_MDP (64 + 16)
116#define INT_VPE (64 + 17)
117#define INT_GRP_2D (64 + 18)
118#define INT_GRP_3D (64 + 19)
119#define INT_ROTATOR (64 + 20)
120#define INT_MFC720 (64 + 21)
121#define INT_JPEG (64 + 22)
122#define INT_VFE (64 + 23)
123#define INT_TV_ENC (64 + 24)
124#define INT_PMIC_SSBI (64 + 25)
125#define INT_MPM_1 (64 + 26)
126#define INT_TCSR_SPSS_SAMPLE (64 + 27)
127#define INT_TCSR_SPSS_PENUP (64 + 28)
128#define INT_MPM_2 (64 + 29)
129#define INT_SDC1_0 (64 + 30)
130#define INT_SDC1_1 (64 + 31)
131
132#define INT_SDC3_0 (96 + 0)
133#define INT_SDC3_1 (96 + 1)
134#define INT_SDC2_0 (96 + 2)
135#define INT_SDC2_1 (96 + 3)
136#define INT_SDC4_0 (96 + 4)
137#define INT_SDC4_1 (96 + 5)
138#define INT_PWB_QUP_IN (96 + 6)
139#define INT_PWB_QUP_OUT (96 + 7)
140#define INT_PWB_QUP_ERR (96 + 8)
141#define INT_SCSS_WDT0_BITE (96 + 9)
142/* SCSS_VICFIQSTS3[10:31] are RESERVED */
143
144/* Retrofit universal macro names */
145#define INT_ADM_AARM INT_ADM_SC2
146#define INT_USB_HS INT_USB_OTG_HS
147#define INT_USB_OTG INT_USB_OTG_HS
148#define INT_TCHSCRN1 INT_TSSC_SAMPLE
149#define INT_TCHSCRN2 INT_TSSC_PENUP
150#define INT_GP_TIMER_EXP INT_GPT0_TIMER_EXP
151#define INT_ADSP_A11 INT_AD5A_MPROC_APPS_0
152#define INT_ADSP_A9_A11 INT_AD5A_MPROC_APPS_1
153#define INT_MDDI_EXT INT_EMDH
154#define INT_MDDI_PRI INT_PMDH
155#define INT_MDDI_CLIENT INT_MDC
156#define INT_NAND_WR_ER_DONE INT_EBI2_WR_ER_DONE
157#define INT_NAND_OP_DONE INT_EBI2_OP_DONE
158
159#define NR_MSM_IRQS 128
160#define NR_GPIO_IRQS 182
161#define PMIC8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
162#define NR_PMIC8058_GPIO_IRQS 40
163#define NR_PMIC8058_MPP_IRQS 12
164#define NR_PMIC8058_MISC_IRQS 8
165#define NR_PMIC8058_IRQS (NR_PMIC8058_GPIO_IRQS +\
166 NR_PMIC8058_MPP_IRQS +\
167 NR_PMIC8058_MISC_IRQS)
168#define NR_BOARD_IRQS NR_PMIC8058_IRQS
169
170#endif /* __ASM_ARCH_MSM_IRQS_7X30_H */
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x50.h b/arch/arm/mach-msm/include/mach/irqs-8x50.h
new file mode 100644
index 000000000000..de3d8fe24e4e
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8x50.h
@@ -0,0 +1,105 @@
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30#ifndef __ASM_ARCH_MSM_IRQS_8XXX_H
31#define __ASM_ARCH_MSM_IRQS_8XXX_H
32
33/* MSM ACPU Interrupt Numbers */
34
35#define INT_A9_M2A_0 0
36#define INT_A9_M2A_1 1
37#define INT_A9_M2A_2 2
38#define INT_A9_M2A_3 3
39#define INT_A9_M2A_4 4
40#define INT_A9_M2A_5 5
41#define INT_A9_M2A_6 6
42#define INT_GP_TIMER_EXP 7
43#define INT_DEBUG_TIMER_EXP 8
44#define INT_SIRC_0 9
45#define INT_SDC3_0 10
46#define INT_SDC3_1 11
47#define INT_SDC4_0 12
48#define INT_SDC4_1 13
49#define INT_AD6_EXT_VFR 14
50#define INT_USB_OTG 15
51#define INT_MDDI_PRI 16
52#define INT_MDDI_EXT 17
53#define INT_MDDI_CLIENT 18
54#define INT_MDP 19
55#define INT_GRAPHICS 20
56#define INT_ADM_AARM 21
57#define INT_ADSP_A11 22
58#define INT_ADSP_A9_A11 23
59#define INT_SDC1_0 24
60#define INT_SDC1_1 25
61#define INT_SDC2_0 26
62#define INT_SDC2_1 27
63#define INT_KEYSENSE 28
64#define INT_TCHSCRN_SSBI 29
65#define INT_TCHSCRN1 30
66#define INT_TCHSCRN2 31
67
68#define INT_TCSR_MPRPH_SC1 (32 + 0)
69#define INT_USB_FS2 (32 + 1)
70#define INT_PWB_I2C (32 + 2)
71#define INT_SOFTRESET (32 + 3)
72#define INT_NAND_WR_ER_DONE (32 + 4)
73#define INT_NAND_OP_DONE (32 + 5)
74#define INT_TCSR_MPRPH_SC2 (32 + 6)
75#define INT_OP_PEN (32 + 7)
76#define INT_AD_HSSD (32 + 8)
77#define INT_ARM11_PM (32 + 9)
78#define INT_SDMA_NON_SECURE (32 + 10)
79#define INT_TSIF_IRQ (32 + 11)
80#define INT_UART1DM_IRQ (32 + 12)
81#define INT_UART1DM_RX (32 + 13)
82#define INT_SDMA_SECURE (32 + 14)
83#define INT_SI2S_SLAVE (32 + 15)
84#define INT_SC_I2CPU (32 + 16)
85#define INT_SC_DBG_RDTRFULL (32 + 17)
86#define INT_SC_DBG_WDTRFULL (32 + 18)
87#define INT_SCPLL_CTL_DONE (32 + 19)
88#define INT_UART2DM_IRQ (32 + 20)
89#define INT_UART2DM_RX (32 + 21)
90#define INT_VDC_MEC (32 + 22)
91#define INT_VDC_DB (32 + 23)
92#define INT_VDC_AXI (32 + 24)
93#define INT_VFE (32 + 25)
94#define INT_USB_HS (32 + 26)
95#define INT_AUDIO_OUT0 (32 + 27)
96#define INT_AUDIO_OUT1 (32 + 28)
97#define INT_CRYPTO (32 + 29)
98#define INT_AD6M_IDLE (32 + 30)
99#define INT_SIRC_1 (32 + 31)
100
101#define NR_GPIO_IRQS 165
102#define NR_MSM_IRQS 64
103#define NR_BOARD_IRQS 64
104
105#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 9dd4cf8a2693..164d355c96ea 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -1,6 +1,6 @@
1/* arch/arm/mach-msm/include/mach/irqs.h 1/*
2 *
3 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 4 * Author: Brian Swetland <swetland@google.com>
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
@@ -17,74 +17,21 @@
17#ifndef __ASM_ARCH_MSM_IRQS_H 17#ifndef __ASM_ARCH_MSM_IRQS_H
18#define __ASM_ARCH_MSM_IRQS_H 18#define __ASM_ARCH_MSM_IRQS_H
19 19
20/* MSM ARM11 Interrupt Numbers */
21/* See 80-VE113-1 A, pp219-221 */
22
23#define INT_A9_M2A_0 0
24#define INT_A9_M2A_1 1
25#define INT_A9_M2A_2 2
26#define INT_A9_M2A_3 3
27#define INT_A9_M2A_4 4
28#define INT_A9_M2A_5 5
29#define INT_A9_M2A_6 6
30#define INT_GP_TIMER_EXP 7
31#define INT_DEBUG_TIMER_EXP 8
32#define INT_UART1 9
33#define INT_UART2 10
34#define INT_UART3 11
35#define INT_UART1_RX 12
36#define INT_UART2_RX 13
37#define INT_UART3_RX 14
38#define INT_USB_OTG 15
39#define INT_MDDI_PRI 16
40#define INT_MDDI_EXT 17
41#define INT_MDDI_CLIENT 18
42#define INT_MDP 19
43#define INT_GRAPHICS 20
44#define INT_ADM_AARM 21
45#define INT_ADSP_A11 22
46#define INT_ADSP_A9_A11 23
47#define INT_SDC1_0 24
48#define INT_SDC1_1 25
49#define INT_SDC2_0 26
50#define INT_SDC2_1 27
51#define INT_KEYSENSE 28
52#define INT_TCHSCRN_SSBI 29
53#define INT_TCHSCRN1 30
54#define INT_TCHSCRN2 31
55
56#define INT_GPIO_GROUP1 (32 + 0)
57#define INT_GPIO_GROUP2 (32 + 1)
58#define INT_PWB_I2C (32 + 2)
59#define INT_SOFTRESET (32 + 3)
60#define INT_NAND_WR_ER_DONE (32 + 4)
61#define INT_NAND_OP_DONE (32 + 5)
62#define INT_PBUS_ARM11 (32 + 6)
63#define INT_AXI_MPU_SMI (32 + 7)
64#define INT_AXI_MPU_EBI1 (32 + 8)
65#define INT_AD_HSSD (32 + 9)
66#define INT_ARM11_PMU (32 + 10)
67#define INT_ARM11_DMA (32 + 11)
68#define INT_TSIF_IRQ (32 + 12)
69#define INT_UART1DM_IRQ (32 + 13)
70#define INT_UART1DM_RX (32 + 14)
71#define INT_USB_HS (32 + 15)
72#define INT_SDC3_0 (32 + 16)
73#define INT_SDC3_1 (32 + 17)
74#define INT_SDC4_0 (32 + 18)
75#define INT_SDC4_1 (32 + 19)
76#define INT_UART2DM_RX (32 + 20)
77#define INT_UART2DM_IRQ (32 + 21)
78
79/* 22-31 are reserved */
80
81#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31)) 20#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
82 21
83#define NR_MSM_IRQS 64 22#if defined(CONFIG_ARCH_MSM7X30)
84#define NR_GPIO_IRQS 122 23#include "irqs-7x30.h"
85#define NR_BOARD_IRQS 64 24#elif defined(CONFIG_ARCH_QSD8X50)
86#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS) 25#include "irqs-8x50.h"
26#include "sirc.h"
27#elif defined(CONFIG_ARCH_MSM_ARM11)
28#include "irqs-7x00.h"
29#else
30#error "Unknown architecture specification"
31#endif
87 32
33#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
88#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n)) 34#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
35#define MSM_INT_TO_REG(base, irq) (base + irq / 32)
89 36
90#endif 37#endif
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index f4698baec976..50c7847e6002 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -17,7 +17,15 @@
17#define __ASM_ARCH_MEMORY_H 17#define __ASM_ARCH_MEMORY_H
18 18
19/* physical offset of RAM */ 19/* physical offset of RAM */
20#if defined(CONFIG_ARCH_QSD8X50) && defined(CONFIG_MSM_SOC_REV_A)
21#define PHYS_OFFSET UL(0x00000000)
22#elif defined(CONFIG_ARCH_QSD8X50)
23#define PHYS_OFFSET UL(0x20000000)
24#elif defined(CONFIG_ARCH_MSM7X30)
25#define PHYS_OFFSET UL(0x00200000)
26#else
20#define PHYS_OFFSET UL(0x10000000) 27#define PHYS_OFFSET UL(0x10000000)
28#endif
21 29
22#endif 30#endif
23 31
diff --git a/arch/arm/mach-msm/include/mach/msm_fb.h b/arch/arm/mach-msm/include/mach/msm_fb.h
new file mode 100644
index 000000000000..1f4fc81b3d8f
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_fb.h
@@ -0,0 +1,147 @@
1/* arch/arm/mach-msm/include/mach/msm_fb.h
2 *
3 * Internal shared definitions for various MSM framebuffer parts.
4 *
5 * Copyright (C) 2007 Google Incorporated
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef _MSM_FB_H_
18#define _MSM_FB_H_
19
20#include <linux/device.h>
21
22struct mddi_info;
23
24struct msm_fb_data {
25 int xres; /* x resolution in pixels */
26 int yres; /* y resolution in pixels */
27 int width; /* disply width in mm */
28 int height; /* display height in mm */
29 unsigned output_format;
30};
31
32struct msmfb_callback {
33 void (*func)(struct msmfb_callback *);
34};
35
36enum {
37 MSM_MDDI_PMDH_INTERFACE,
38 MSM_MDDI_EMDH_INTERFACE,
39 MSM_EBI2_INTERFACE,
40};
41
42#define MSMFB_CAP_PARTIAL_UPDATES (1 << 0)
43
44struct msm_panel_data {
45 /* turns off the fb memory */
46 int (*suspend)(struct msm_panel_data *);
47 /* turns on the fb memory */
48 int (*resume)(struct msm_panel_data *);
49 /* turns off the panel */
50 int (*blank)(struct msm_panel_data *);
51 /* turns on the panel */
52 int (*unblank)(struct msm_panel_data *);
53 void (*wait_vsync)(struct msm_panel_data *);
54 void (*request_vsync)(struct msm_panel_data *, struct msmfb_callback *);
55 void (*clear_vsync)(struct msm_panel_data *);
56 /* from the enum above */
57 unsigned interface_type;
58 /* data to be passed to the fb driver */
59 struct msm_fb_data *fb_data;
60
61 /* capabilities supported by the panel */
62 uint32_t caps;
63};
64
65struct msm_mddi_client_data {
66 void (*suspend)(struct msm_mddi_client_data *);
67 void (*resume)(struct msm_mddi_client_data *);
68 void (*activate_link)(struct msm_mddi_client_data *);
69 void (*remote_write)(struct msm_mddi_client_data *, uint32_t val,
70 uint32_t reg);
71 uint32_t (*remote_read)(struct msm_mddi_client_data *, uint32_t reg);
72 void (*auto_hibernate)(struct msm_mddi_client_data *, int);
73 /* custom data that needs to be passed from the board file to a
74 * particular client */
75 void *private_client_data;
76 struct resource *fb_resource;
77 /* from the list above */
78 unsigned interface_type;
79};
80
81struct msm_mddi_platform_data {
82 unsigned int clk_rate;
83 void (*power_client)(struct msm_mddi_client_data *, int on);
84
85 /* fixup the mfr name, product id */
86 void (*fixup)(uint16_t *mfr_name, uint16_t *product_id);
87
88 struct resource *fb_resource; /*optional*/
89 /* number of clients in the list that follows */
90 int num_clients;
91 /* array of client information of clients */
92 struct {
93 unsigned product_id; /* mfr id in top 16 bits, product id
94 * in lower 16 bits
95 */
96 char *name; /* the device name will be the platform
97 * device name registered for the client,
98 * it should match the name of the associated
99 * driver
100 */
101 unsigned id; /* id for mddi client device node, will also
102 * be used as device id of panel devices, if
103 * the client device will have multiple panels
104 * space must be left here for them
105 */
106 void *client_data; /* required private client data */
107 unsigned int clk_rate; /* optional: if the client requires a
108 * different mddi clk rate
109 */
110 } client_platform_data[];
111};
112
113struct mdp_blit_req;
114struct fb_info;
115struct mdp_device {
116 struct device dev;
117 void (*dma)(struct mdp_device *mpd, uint32_t addr,
118 uint32_t stride, uint32_t w, uint32_t h, uint32_t x,
119 uint32_t y, struct msmfb_callback *callback, int interface);
120 void (*dma_wait)(struct mdp_device *mdp);
121 int (*blit)(struct mdp_device *mdp, struct fb_info *fb,
122 struct mdp_blit_req *req);
123 void (*set_grp_disp)(struct mdp_device *mdp, uint32_t disp_id);
124};
125
126struct class_interface;
127int register_mdp_client(struct class_interface *class_intf);
128
129/**** private client data structs go below this line ***/
130
131struct msm_mddi_bridge_platform_data {
132 /* from board file */
133 int (*init)(struct msm_mddi_bridge_platform_data *,
134 struct msm_mddi_client_data *);
135 int (*uninit)(struct msm_mddi_bridge_platform_data *,
136 struct msm_mddi_client_data *);
137 /* passed to panel for use by the fb driver */
138 int (*blank)(struct msm_mddi_bridge_platform_data *,
139 struct msm_mddi_client_data *);
140 int (*unblank)(struct msm_mddi_bridge_platform_data *,
141 struct msm_mddi_client_data *);
142 struct msm_fb_data fb_data;
143};
144
145
146
147#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
new file mode 100644
index 000000000000..cfff0e74f128
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -0,0 +1,139 @@
1/* arch/arm/mach-msm/include/mach/msm_iomap.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_7X00_H
24#define __ASM_ARCH_MSM_IOMAP_7X00_H
25
26#include <asm/sizes.h>
27
28/* Physical base address and size of peripherals.
29 * Ordered by the virtual base addresses they will be mapped at.
30 *
31 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
32 * instruction, otherwise entry-macro.S will not compile.
33 *
34 * If you add or remove entries here, you'll want to edit the
35 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
36 * changes.
37 *
38 */
39
40#ifdef __ASSEMBLY__
41#define IOMEM(x) x
42#else
43#define IOMEM(x) ((void __force __iomem *)(x))
44#endif
45
46#define MSM_VIC_BASE IOMEM(0xE0000000)
47#define MSM_VIC_PHYS 0xC0000000
48#define MSM_VIC_SIZE SZ_4K
49
50#define MSM_CSR_BASE IOMEM(0xE0001000)
51#define MSM_CSR_PHYS 0xC0100000
52#define MSM_CSR_SIZE SZ_4K
53
54#define MSM_GPT_PHYS MSM_CSR_PHYS
55#define MSM_GPT_BASE MSM_CSR_BASE
56#define MSM_GPT_SIZE SZ_4K
57
58#define MSM_DMOV_BASE IOMEM(0xE0002000)
59#define MSM_DMOV_PHYS 0xA9700000
60#define MSM_DMOV_SIZE SZ_4K
61
62#define MSM_GPIO1_BASE IOMEM(0xE0003000)
63#define MSM_GPIO1_PHYS 0xA9200000
64#define MSM_GPIO1_SIZE SZ_4K
65
66#define MSM_GPIO2_BASE IOMEM(0xE0004000)
67#define MSM_GPIO2_PHYS 0xA9300000
68#define MSM_GPIO2_SIZE SZ_4K
69
70#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
71#define MSM_CLK_CTL_PHYS 0xA8600000
72#define MSM_CLK_CTL_SIZE SZ_4K
73
74#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
75#define MSM_SHARED_RAM_PHYS 0x01F00000
76#define MSM_SHARED_RAM_SIZE SZ_1M
77
78#define MSM_UART1_PHYS 0xA9A00000
79#define MSM_UART1_SIZE SZ_4K
80
81#define MSM_UART2_PHYS 0xA9B00000
82#define MSM_UART2_SIZE SZ_4K
83
84#define MSM_UART3_PHYS 0xA9C00000
85#define MSM_UART3_SIZE SZ_4K
86
87#ifdef CONFIG_MSM_DEBUG_UART
88#define MSM_DEBUG_UART_BASE 0xE1000000
89#if CONFIG_MSM_DEBUG_UART == 1
90#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
91#elif CONFIG_MSM_DEBUG_UART == 2
92#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
93#elif CONFIG_MSM_DEBUG_UART == 3
94#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
95#endif
96#define MSM_DEBUG_UART_SIZE SZ_4K
97#endif
98
99#define MSM_SDC1_PHYS 0xA0400000
100#define MSM_SDC1_SIZE SZ_4K
101
102#define MSM_SDC2_PHYS 0xA0500000
103#define MSM_SDC2_SIZE SZ_4K
104
105#define MSM_SDC3_PHYS 0xA0600000
106#define MSM_SDC3_SIZE SZ_4K
107
108#define MSM_SDC4_PHYS 0xA0700000
109#define MSM_SDC4_SIZE SZ_4K
110
111#define MSM_I2C_PHYS 0xA9900000
112#define MSM_I2C_SIZE SZ_4K
113
114#define MSM_HSUSB_PHYS 0xA0800000
115#define MSM_HSUSB_SIZE SZ_4K
116
117#define MSM_PMDH_PHYS 0xAA600000
118#define MSM_PMDH_SIZE SZ_4K
119
120#define MSM_EMDH_PHYS 0xAA700000
121#define MSM_EMDH_SIZE SZ_4K
122
123#define MSM_MDP_PHYS 0xAA200000
124#define MSM_MDP_SIZE 0x000F0000
125
126#define MSM_MDC_PHYS 0xAA500000
127#define MSM_MDC_SIZE SZ_1M
128
129#define MSM_AD5_PHYS 0xAC000000
130#define MSM_AD5_SIZE (SZ_1M*13)
131
132
133#if defined(CONFIG_ARCH_MSM7X30)
134#define MSM_GCC_BASE IOMEM(0xF8009000)
135#define MSM_GCC_PHYS 0xC0182000
136#define MSM_GCC_SIZE SZ_4K
137#endif
138
139#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
new file mode 100644
index 000000000000..8a00c2defbc1
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -0,0 +1,122 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_7X30_H
24#define __ASM_ARCH_MSM_IOMAP_7X30_H
25
26/* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at.
28 *
29 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
30 * instruction, otherwise entry-macro.S will not compile.
31 *
32 * If you add or remove entries here, you'll want to edit the
33 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
34 * changes.
35 *
36 */
37
38#define MSM_VIC_BASE IOMEM(0xE0000000)
39#define MSM_VIC_PHYS 0xC0080000
40#define MSM_VIC_SIZE SZ_4K
41
42#define MSM_CSR_BASE IOMEM(0xE0001000)
43#define MSM_CSR_PHYS 0xC0100000
44#define MSM_CSR_SIZE SZ_4K
45
46#define MSM_TMR_PHYS MSM_CSR_PHYS
47#define MSM_TMR_BASE MSM_CSR_BASE
48#define MSM_TMR_SIZE SZ_4K
49
50#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
51#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
52
53#define MSM_DMOV_BASE IOMEM(0xE0002000)
54#define MSM_DMOV_PHYS 0xAC400000
55#define MSM_DMOV_SIZE SZ_4K
56
57#define MSM_GPIO1_BASE IOMEM(0xE0003000)
58#define MSM_GPIO1_PHYS 0xAC001000
59#define MSM_GPIO1_SIZE SZ_4K
60
61#define MSM_GPIO2_BASE IOMEM(0xE0004000)
62#define MSM_GPIO2_PHYS 0xAC101000
63#define MSM_GPIO2_SIZE SZ_4K
64
65#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
66#define MSM_CLK_CTL_PHYS 0xAB800000
67#define MSM_CLK_CTL_SIZE SZ_4K
68
69#define MSM_CLK_CTL_SH2_BASE IOMEM(0xE0006000)
70#define MSM_CLK_CTL_SH2_PHYS 0xABA01000
71#define MSM_CLK_CTL_SH2_SIZE SZ_4K
72
73#define MSM_ACC_BASE IOMEM(0xE0007000)
74#define MSM_ACC_PHYS 0xC0101000
75#define MSM_ACC_SIZE SZ_4K
76
77#define MSM_SAW_BASE IOMEM(0xE0008000)
78#define MSM_SAW_PHYS 0xC0102000
79#define MSM_SAW_SIZE SZ_4K
80
81#define MSM_GCC_BASE IOMEM(0xE0009000)
82#define MSM_GCC_PHYS 0xC0182000
83#define MSM_GCC_SIZE SZ_4K
84
85#define MSM_TCSR_BASE IOMEM(0xE000A000)
86#define MSM_TCSR_PHYS 0xAB600000
87#define MSM_TCSR_SIZE SZ_4K
88
89#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
90#define MSM_SHARED_RAM_PHYS 0x00100000
91#define MSM_SHARED_RAM_SIZE SZ_1M
92
93#define MSM_UART1_PHYS 0xACA00000
94#define MSM_UART1_SIZE SZ_4K
95
96#define MSM_UART2_PHYS 0xACB00000
97#define MSM_UART2_SIZE SZ_4K
98
99#define MSM_UART3_PHYS 0xACC00000
100#define MSM_UART3_SIZE SZ_4K
101
102#ifdef CONFIG_MSM_DEBUG_UART
103#define MSM_DEBUG_UART_BASE 0xE1000000
104#if CONFIG_MSM_DEBUG_UART == 1
105#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
106#elif CONFIG_MSM_DEBUG_UART == 2
107#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
108#elif CONFIG_MSM_DEBUG_UART == 3
109#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
110#endif
111#define MSM_DEBUG_UART_SIZE SZ_4K
112#endif
113
114#define MSM_MDC_BASE IOMEM(0xE0200000)
115#define MSM_MDC_PHYS 0xAA500000
116#define MSM_MDC_SIZE SZ_1M
117
118#define MSM_AD5_BASE IOMEM(0xE0300000)
119#define MSM_AD5_PHYS 0xA7000000
120#define MSM_AD5_SIZE (SZ_1M*13)
121
122#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
new file mode 100644
index 000000000000..acc819eb76e5
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -0,0 +1,147 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_8X50_H
24#define __ASM_ARCH_MSM_IOMAP_8X50_H
25
26/* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at.
28 *
29 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
30 * instruction, otherwise entry-macro.S will not compile.
31 *
32 * If you add or remove entries here, you'll want to edit the
33 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
34 * changes.
35 *
36 */
37
38#define MSM_VIC_BASE IOMEM(0xE0000000)
39#define MSM_VIC_PHYS 0xAC000000
40#define MSM_VIC_SIZE SZ_4K
41
42#define MSM_CSR_BASE IOMEM(0xE0001000)
43#define MSM_CSR_PHYS 0xAC100000
44#define MSM_CSR_SIZE SZ_4K
45
46#define MSM_TMR_PHYS MSM_CSR_PHYS
47#define MSM_TMR_BASE MSM_CSR_BASE
48#define MSM_TMR_SIZE SZ_4K
49
50#define MSM_GPT_BASE MSM_TMR_BASE
51#define MSM_DGT_BASE (MSM_TMR_BASE + 0x10)
52
53#define MSM_DMOV_BASE IOMEM(0xE0002000)
54#define MSM_DMOV_PHYS 0xA9700000
55#define MSM_DMOV_SIZE SZ_4K
56
57#define MSM_GPIO1_BASE IOMEM(0xE0003000)
58#define MSM_GPIO1_PHYS 0xA9000000
59#define MSM_GPIO1_SIZE SZ_4K
60
61#define MSM_GPIO2_BASE IOMEM(0xE0004000)
62#define MSM_GPIO2_PHYS 0xA9100000
63#define MSM_GPIO2_SIZE SZ_4K
64
65#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
66#define MSM_CLK_CTL_PHYS 0xA8600000
67#define MSM_CLK_CTL_SIZE SZ_4K
68
69#define MSM_SIRC_BASE IOMEM(0xE1006000)
70#define MSM_SIRC_PHYS 0xAC200000
71#define MSM_SIRC_SIZE SZ_4K
72
73#define MSM_SCPLL_BASE IOMEM(0xE1007000)
74#define MSM_SCPLL_PHYS 0xA8800000
75#define MSM_SCPLL_SIZE SZ_4K
76
77#ifdef CONFIG_MSM_SOC_REV_A
78#define MSM_SMI_BASE 0xE0000000
79#else
80#define MSM_SMI_BASE 0x00000000
81#endif
82
83#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
84#define MSM_SHARED_RAM_PHYS (MSM_SMI_BASE + 0x00100000)
85#define MSM_SHARED_RAM_SIZE SZ_1M
86
87#define MSM_UART1_PHYS 0xA9A00000
88#define MSM_UART1_SIZE SZ_4K
89
90#define MSM_UART2_PHYS 0xA9B00000
91#define MSM_UART2_SIZE SZ_4K
92
93#define MSM_UART3_PHYS 0xA9C00000
94#define MSM_UART3_SIZE SZ_4K
95
96#ifdef CONFIG_MSM_DEBUG_UART
97#define MSM_DEBUG_UART_BASE 0xE1000000
98#if CONFIG_MSM_DEBUG_UART == 1
99#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
100#elif CONFIG_MSM_DEBUG_UART == 2
101#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
102#elif CONFIG_MSM_DEBUG_UART == 3
103#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
104#endif
105#define MSM_DEBUG_UART_SIZE SZ_4K
106#endif
107
108#define MSM_MDC_BASE IOMEM(0xE0200000)
109#define MSM_MDC_PHYS 0xAA500000
110#define MSM_MDC_SIZE SZ_1M
111
112#define MSM_AD5_BASE IOMEM(0xE0300000)
113#define MSM_AD5_PHYS 0xAC000000
114#define MSM_AD5_SIZE (SZ_1M*13)
115
116
117#define MSM_I2C_SIZE SZ_4K
118#define MSM_I2C_PHYS 0xA9900000
119
120#define MSM_HSUSB_PHYS 0xA0800000
121#define MSM_HSUSB_SIZE SZ_1K
122
123#define MSM_NAND_PHYS 0xA0A00000
124
125
126#define MSM_TSIF_PHYS (0xa0100000)
127#define MSM_TSIF_SIZE (0x200)
128
129#define MSM_TSSC_PHYS 0xAA300000
130
131#define MSM_UART1DM_PHYS 0xA0200000
132#define MSM_UART2DM_PHYS 0xA0900000
133
134
135#define MSM_SDC1_PHYS 0xA0400000
136#define MSM_SDC1_SIZE SZ_4K
137
138#define MSM_SDC2_PHYS 0xA0500000
139#define MSM_SDC2_SIZE SZ_4K
140
141#define MSM_SDC3_PHYS 0xA0600000
142#define MSM_SDC3_SIZE SZ_4K
143
144#define MSM_SDC4_PHYS 0xA0700000
145#define MSM_SDC4_SIZE SZ_4K
146
147#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 9dae1a98c77a..e6b1821cc4ea 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -1,6 +1,6 @@
1/* arch/arm/mach-msm/include/mach/msm_iomap.h 1/*
2 *
3 * Copyright (C) 2007 Google, Inc. 2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com> 4 * Author: Brian Swetland <swetland@google.com>
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
@@ -43,91 +43,12 @@
43#define IOMEM(x) ((void __force __iomem *)(x)) 43#define IOMEM(x) ((void __force __iomem *)(x))
44#endif 44#endif
45 45
46#define MSM_VIC_BASE IOMEM(0xE0000000) 46#if defined(CONFIG_ARCH_MSM7X30)
47#define MSM_VIC_PHYS 0xC0000000 47#include "msm_iomap-7x30.h"
48#define MSM_VIC_SIZE SZ_4K 48#elif defined(CONFIG_ARCH_QSD8X50)
49 49#include "msm_iomap-8x50.h"
50#define MSM_CSR_BASE IOMEM(0xE0001000) 50#else
51#define MSM_CSR_PHYS 0xC0100000 51#include "msm_iomap-7x00.h"
52#define MSM_CSR_SIZE SZ_4K
53
54#define MSM_GPT_PHYS MSM_CSR_PHYS
55#define MSM_GPT_BASE MSM_CSR_BASE
56#define MSM_GPT_SIZE SZ_4K
57
58#define MSM_DMOV_BASE IOMEM(0xE0002000)
59#define MSM_DMOV_PHYS 0xA9700000
60#define MSM_DMOV_SIZE SZ_4K
61
62#define MSM_GPIO1_BASE IOMEM(0xE0003000)
63#define MSM_GPIO1_PHYS 0xA9200000
64#define MSM_GPIO1_SIZE SZ_4K
65
66#define MSM_GPIO2_BASE IOMEM(0xE0004000)
67#define MSM_GPIO2_PHYS 0xA9300000
68#define MSM_GPIO2_SIZE SZ_4K
69
70#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
71#define MSM_CLK_CTL_PHYS 0xA8600000
72#define MSM_CLK_CTL_SIZE SZ_4K
73
74#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
75#define MSM_SHARED_RAM_PHYS 0x01F00000
76#define MSM_SHARED_RAM_SIZE SZ_1M
77
78#define MSM_UART1_PHYS 0xA9A00000
79#define MSM_UART1_SIZE SZ_4K
80
81#define MSM_UART2_PHYS 0xA9B00000
82#define MSM_UART2_SIZE SZ_4K
83
84#define MSM_UART3_PHYS 0xA9C00000
85#define MSM_UART3_SIZE SZ_4K
86
87#ifdef CONFIG_MSM_DEBUG_UART
88#define MSM_DEBUG_UART_BASE 0xE1000000
89#if CONFIG_MSM_DEBUG_UART == 1
90#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
91#elif CONFIG_MSM_DEBUG_UART == 2
92#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
93#elif CONFIG_MSM_DEBUG_UART == 3
94#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
95#endif
96#define MSM_DEBUG_UART_SIZE SZ_4K
97#endif 52#endif
98 53
99#define MSM_SDC1_PHYS 0xA0400000
100#define MSM_SDC1_SIZE SZ_4K
101
102#define MSM_SDC2_PHYS 0xA0500000
103#define MSM_SDC2_SIZE SZ_4K
104
105#define MSM_SDC3_PHYS 0xA0600000
106#define MSM_SDC3_SIZE SZ_4K
107
108#define MSM_SDC4_PHYS 0xA0700000
109#define MSM_SDC4_SIZE SZ_4K
110
111#define MSM_I2C_PHYS 0xA9900000
112#define MSM_I2C_SIZE SZ_4K
113
114#define MSM_HSUSB_PHYS 0xA0800000
115#define MSM_HSUSB_SIZE SZ_4K
116
117#define MSM_PMDH_PHYS 0xAA600000
118#define MSM_PMDH_SIZE SZ_4K
119
120#define MSM_EMDH_PHYS 0xAA700000
121#define MSM_EMDH_SIZE SZ_4K
122
123#define MSM_MDP_PHYS 0xAA200000
124#define MSM_MDP_SIZE 0x000F0000
125
126#define MSM_MDC_PHYS 0xAA500000
127#define MSM_MDC_SIZE SZ_1M
128
129#define MSM_AD5_PHYS 0xAC000000
130#define MSM_AD5_SIZE (SZ_1M*13)
131
132
133#endif 54#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_smd.h b/arch/arm/mach-msm/include/mach/msm_smd.h
new file mode 100644
index 000000000000..029463ec8756
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_smd.h
@@ -0,0 +1,109 @@
1/* linux/include/asm-arm/arch-msm/msm_smd.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __ASM_ARCH_MSM_SMD_H
18#define __ASM_ARCH_MSM_SMD_H
19
20typedef struct smd_channel smd_channel_t;
21
22extern int (*msm_check_for_modem_crash)(void);
23
24/* warning: notify() may be called before open returns */
25int smd_open(const char *name, smd_channel_t **ch, void *priv,
26 void (*notify)(void *priv, unsigned event));
27
28#define SMD_EVENT_DATA 1
29#define SMD_EVENT_OPEN 2
30#define SMD_EVENT_CLOSE 3
31
32int smd_close(smd_channel_t *ch);
33
34/* passing a null pointer for data reads and discards */
35int smd_read(smd_channel_t *ch, void *data, int len);
36
37/* Write to stream channels may do a partial write and return
38** the length actually written.
39** Write to packet channels will never do a partial write --
40** it will return the requested length written or an error.
41*/
42int smd_write(smd_channel_t *ch, const void *data, int len);
43int smd_write_atomic(smd_channel_t *ch, const void *data, int len);
44
45int smd_write_avail(smd_channel_t *ch);
46int smd_read_avail(smd_channel_t *ch);
47
48/* Returns the total size of the current packet being read.
49** Returns 0 if no packets available or a stream channel.
50*/
51int smd_cur_packet_size(smd_channel_t *ch);
52
53/* used for tty unthrottling and the like -- causes the notify()
54** callback to be called from the same lock context as is used
55** when it is called from channel updates
56*/
57void smd_kick(smd_channel_t *ch);
58
59
60#if 0
61/* these are interruptable waits which will block you until the specified
62** number of bytes are readable or writable.
63*/
64int smd_wait_until_readable(smd_channel_t *ch, int bytes);
65int smd_wait_until_writable(smd_channel_t *ch, int bytes);
66#endif
67
68typedef enum {
69 SMD_PORT_DS = 0,
70 SMD_PORT_DIAG,
71 SMD_PORT_RPC_CALL,
72 SMD_PORT_RPC_REPLY,
73 SMD_PORT_BT,
74 SMD_PORT_CONTROL,
75 SMD_PORT_MEMCPY_SPARE1,
76 SMD_PORT_DATA1,
77 SMD_PORT_DATA2,
78 SMD_PORT_DATA3,
79 SMD_PORT_DATA4,
80 SMD_PORT_DATA5,
81 SMD_PORT_DATA6,
82 SMD_PORT_DATA7,
83 SMD_PORT_DATA8,
84 SMD_PORT_DATA9,
85 SMD_PORT_DATA10,
86 SMD_PORT_DATA11,
87 SMD_PORT_DATA12,
88 SMD_PORT_DATA13,
89 SMD_PORT_DATA14,
90 SMD_PORT_DATA15,
91 SMD_PORT_DATA16,
92 SMD_PORT_DATA17,
93 SMD_PORT_DATA18,
94 SMD_PORT_DATA19,
95 SMD_PORT_DATA20,
96 SMD_PORT_GPS_NMEA,
97 SMD_PORT_BRIDGE_1,
98 SMD_PORT_BRIDGE_2,
99 SMD_PORT_BRIDGE_3,
100 SMD_PORT_BRIDGE_4,
101 SMD_PORT_BRIDGE_5,
102 SMD_PORT_LOOPBACK,
103 SMD_PORT_CS_APPS_MODEM,
104 SMD_PORT_CS_APPS_DSP,
105 SMD_PORT_CS_MODEM_DSP,
106 SMD_NUM_PORTS,
107} smd_port_id_type;
108
109#endif
diff --git a/arch/arm/mach-msm/include/mach/sirc.h b/arch/arm/mach-msm/include/mach/sirc.h
new file mode 100644
index 000000000000..7281337ee28d
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/sirc.h
@@ -0,0 +1,115 @@
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30#ifndef __ASM_ARCH_MSM_SIRC_H
31#define __ASM_ARCH_MSM_SIRC_H
32
33struct sirc_regs_t {
34 void *int_enable;
35 void *int_enable_clear;
36 void *int_enable_set;
37 void *int_type;
38 void *int_polarity;
39 void *int_clear;
40};
41
42struct sirc_cascade_regs {
43 void *int_status;
44 unsigned int cascade_irq;
45};
46
47void msm_init_sirc(void);
48void msm_sirc_enter_sleep(void);
49void msm_sirc_exit_sleep(void);
50
51#if defined(CONFIG_ARCH_MSM_SCORPION)
52
53#include <mach/msm_iomap.h>
54
55/*
56 * Secondary interrupt controller interrupts
57 */
58
59#define FIRST_SIRC_IRQ (NR_MSM_IRQS + NR_GPIO_IRQS)
60
61#define INT_UART1 (FIRST_SIRC_IRQ + 0)
62#define INT_UART2 (FIRST_SIRC_IRQ + 1)
63#define INT_UART3 (FIRST_SIRC_IRQ + 2)
64#define INT_UART1_RX (FIRST_SIRC_IRQ + 3)
65#define INT_UART2_RX (FIRST_SIRC_IRQ + 4)
66#define INT_UART3_RX (FIRST_SIRC_IRQ + 5)
67#define INT_SPI_INPUT (FIRST_SIRC_IRQ + 6)
68#define INT_SPI_OUTPUT (FIRST_SIRC_IRQ + 7)
69#define INT_SPI_ERROR (FIRST_SIRC_IRQ + 8)
70#define INT_GPIO_GROUP1 (FIRST_SIRC_IRQ + 9)
71#define INT_GPIO_GROUP2 (FIRST_SIRC_IRQ + 10)
72#define INT_GPIO_GROUP1_SECURE (FIRST_SIRC_IRQ + 11)
73#define INT_GPIO_GROUP2_SECURE (FIRST_SIRC_IRQ + 12)
74#define INT_AVS_SVIC (FIRST_SIRC_IRQ + 13)
75#define INT_AVS_REQ_UP (FIRST_SIRC_IRQ + 14)
76#define INT_AVS_REQ_DOWN (FIRST_SIRC_IRQ + 15)
77#define INT_PBUS_ERR (FIRST_SIRC_IRQ + 16)
78#define INT_AXI_ERR (FIRST_SIRC_IRQ + 17)
79#define INT_SMI_ERR (FIRST_SIRC_IRQ + 18)
80#define INT_EBI1_ERR (FIRST_SIRC_IRQ + 19)
81#define INT_IMEM_ERR (FIRST_SIRC_IRQ + 20)
82#define INT_TEMP_SENSOR (FIRST_SIRC_IRQ + 21)
83#define INT_TV_ENC (FIRST_SIRC_IRQ + 22)
84#define INT_GRP2D (FIRST_SIRC_IRQ + 23)
85#define INT_GSBI_QUP (FIRST_SIRC_IRQ + 24)
86#define INT_SC_ACG (FIRST_SIRC_IRQ + 25)
87#define INT_WDT0 (FIRST_SIRC_IRQ + 26)
88#define INT_WDT1 (FIRST_SIRC_IRQ + 27)
89
90#if defined(CONFIG_MSM_SOC_REV_A)
91#define NR_SIRC_IRQS 28
92#define SIRC_MASK 0x0FFFFFFF
93#else
94#define NR_SIRC_IRQS 23
95#define SIRC_MASK 0x007FFFFF
96#endif
97
98#define LAST_SIRC_IRQ (FIRST_SIRC_IRQ + NR_SIRC_IRQS - 1)
99
100#define SPSS_SIRC_INT_SELECT (MSM_SIRC_BASE + 0x00)
101#define SPSS_SIRC_INT_ENABLE (MSM_SIRC_BASE + 0x04)
102#define SPSS_SIRC_INT_ENABLE_CLEAR (MSM_SIRC_BASE + 0x08)
103#define SPSS_SIRC_INT_ENABLE_SET (MSM_SIRC_BASE + 0x0C)
104#define SPSS_SIRC_INT_TYPE (MSM_SIRC_BASE + 0x10)
105#define SPSS_SIRC_INT_POLARITY (MSM_SIRC_BASE + 0x14)
106#define SPSS_SIRC_SECURITY (MSM_SIRC_BASE + 0x18)
107#define SPSS_SIRC_IRQ_STATUS (MSM_SIRC_BASE + 0x1C)
108#define SPSS_SIRC_IRQ1_STATUS (MSM_SIRC_BASE + 0x20)
109#define SPSS_SIRC_RAW_STATUS (MSM_SIRC_BASE + 0x24)
110#define SPSS_SIRC_INT_CLEAR (MSM_SIRC_BASE + 0x28)
111#define SPSS_SIRC_SOFT_INT (MSM_SIRC_BASE + 0x2C)
112
113#endif
114
115#endif
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
index 574ccc493daf..d2e83f42ba16 100644
--- a/arch/arm/mach-msm/include/mach/system.h
+++ b/arch/arm/mach-msm/include/mach/system.h
@@ -21,3 +21,8 @@ static inline void arch_reset(char mode, const char *cmd)
21{ 21{
22 for (;;) ; /* depends on IPC w/ other core */ 22 for (;;) ; /* depends on IPC w/ other core */
23} 23}
24
25/* low level hardware reset hook -- for example, hitting the
26 * PSHOLD line on the PMIC to hard reset the system
27 */
28extern void (*msm_hw_reset_hook)(void);
diff --git a/arch/arm/mach-msm/include/mach/vreg.h b/arch/arm/mach-msm/include/mach/vreg.h
index 9f9e25cb718e..6626e7864e28 100644
--- a/arch/arm/mach-msm/include/mach/vreg.h
+++ b/arch/arm/mach-msm/include/mach/vreg.h
@@ -23,7 +23,7 @@ struct vreg *vreg_get(struct device *dev, const char *id);
23void vreg_put(struct vreg *vreg); 23void vreg_put(struct vreg *vreg);
24 24
25int vreg_enable(struct vreg *vreg); 25int vreg_enable(struct vreg *vreg);
26void vreg_disable(struct vreg *vreg); 26int vreg_disable(struct vreg *vreg);
27int vreg_set_level(struct vreg *vreg, unsigned mv); 27int vreg_set_level(struct vreg *vreg, unsigned mv);
28 28
29#endif 29#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-23 03:11:07 -0500