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authorHaojian Zhuang <haojian.zhuang@gmail.com>2012-06-05 05:42:23 -0400
committerHaojian Zhuang <haojian.zhuang@gmail.com>2012-06-05 05:42:23 -0400
commit10bd21c0547ba2834374ccdddbc6a984eeed432c (patch)
tree0e2c578a3e6e065ceeedb304f09c85e232ed9e34 /arch/arm/mach-mmp
parent51ce29196dee3084387aa4448d75edc282a91685 (diff)
ARM: mmp: fix missing cascade_irq in irq handler
While supporting board in non-DT mode, icu_data[i]->cascade_irq isn't assigned with correct value. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Diffstat (limited to 'arch/arm/mach-mmp')
-rw-r--r--arch/arm/mach-mmp/irq.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
index fcfe0e3bd701..e60c7d98922b 100644
--- a/arch/arm/mach-mmp/irq.c
+++ b/arch/arm/mach-mmp/irq.c
@@ -241,6 +241,7 @@ void __init mmp2_init_icu(void)
241 icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE; 241 icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE;
242 icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE; 242 icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE;
243 icu_data[1].nr_irqs = 2; 243 icu_data[1].nr_irqs = 2;
244 icu_data[1].cascade_irq = 4;
244 icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE; 245 icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE;
245 icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs, 246 icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
246 icu_data[1].virq_base, 0, 247 icu_data[1].virq_base, 0,
@@ -249,6 +250,7 @@ void __init mmp2_init_icu(void)
249 icu_data[2].reg_status = mmp_icu_base + 0x154; 250 icu_data[2].reg_status = mmp_icu_base + 0x154;
250 icu_data[2].reg_mask = mmp_icu_base + 0x16c; 251 icu_data[2].reg_mask = mmp_icu_base + 0x16c;
251 icu_data[2].nr_irqs = 2; 252 icu_data[2].nr_irqs = 2;
253 icu_data[2].cascade_irq = 5;
252 icu_data[2].virq_base = IRQ_MMP2_RTC_BASE; 254 icu_data[2].virq_base = IRQ_MMP2_RTC_BASE;
253 icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs, 255 icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
254 icu_data[2].virq_base, 0, 256 icu_data[2].virq_base, 0,
@@ -257,6 +259,7 @@ void __init mmp2_init_icu(void)
257 icu_data[3].reg_status = mmp_icu_base + 0x180; 259 icu_data[3].reg_status = mmp_icu_base + 0x180;
258 icu_data[3].reg_mask = mmp_icu_base + 0x17c; 260 icu_data[3].reg_mask = mmp_icu_base + 0x17c;
259 icu_data[3].nr_irqs = 3; 261 icu_data[3].nr_irqs = 3;
262 icu_data[3].cascade_irq = 9;
260 icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE; 263 icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE;
261 icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs, 264 icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
262 icu_data[3].virq_base, 0, 265 icu_data[3].virq_base, 0,
@@ -265,6 +268,7 @@ void __init mmp2_init_icu(void)
265 icu_data[4].reg_status = mmp_icu_base + 0x158; 268 icu_data[4].reg_status = mmp_icu_base + 0x158;
266 icu_data[4].reg_mask = mmp_icu_base + 0x170; 269 icu_data[4].reg_mask = mmp_icu_base + 0x170;
267 icu_data[4].nr_irqs = 5; 270 icu_data[4].nr_irqs = 5;
271 icu_data[4].cascade_irq = 17;
268 icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE; 272 icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE;
269 icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs, 273 icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
270 icu_data[4].virq_base, 0, 274 icu_data[4].virq_base, 0,
@@ -273,6 +277,7 @@ void __init mmp2_init_icu(void)
273 icu_data[5].reg_status = mmp_icu_base + 0x15c; 277 icu_data[5].reg_status = mmp_icu_base + 0x15c;
274 icu_data[5].reg_mask = mmp_icu_base + 0x174; 278 icu_data[5].reg_mask = mmp_icu_base + 0x174;
275 icu_data[5].nr_irqs = 15; 279 icu_data[5].nr_irqs = 15;
280 icu_data[5].cascade_irq = 35;
276 icu_data[5].virq_base = IRQ_MMP2_MISC_BASE; 281 icu_data[5].virq_base = IRQ_MMP2_MISC_BASE;
277 icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs, 282 icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
278 icu_data[5].virq_base, 0, 283 icu_data[5].virq_base, 0,
@@ -281,6 +286,7 @@ void __init mmp2_init_icu(void)
281 icu_data[6].reg_status = mmp_icu_base + 0x160; 286 icu_data[6].reg_status = mmp_icu_base + 0x160;
282 icu_data[6].reg_mask = mmp_icu_base + 0x178; 287 icu_data[6].reg_mask = mmp_icu_base + 0x178;
283 icu_data[6].nr_irqs = 2; 288 icu_data[6].nr_irqs = 2;
289 icu_data[6].cascade_irq = 51;
284 icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE; 290 icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE;
285 icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs, 291 icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
286 icu_data[6].virq_base, 0, 292 icu_data[6].virq_base, 0,
@@ -289,6 +295,7 @@ void __init mmp2_init_icu(void)
289 icu_data[7].reg_status = mmp_icu_base + 0x188; 295 icu_data[7].reg_status = mmp_icu_base + 0x188;
290 icu_data[7].reg_mask = mmp_icu_base + 0x184; 296 icu_data[7].reg_mask = mmp_icu_base + 0x184;
291 icu_data[7].nr_irqs = 2; 297 icu_data[7].nr_irqs = 2;
298 icu_data[7].cascade_irq = 55;
292 icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE; 299 icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE;
293 icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs, 300 icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
294 icu_data[7].virq_base, 0, 301 icu_data[7].virq_base, 0,