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authorGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
committerGlenn Elliott <gelliott@cs.unc.edu>2012-03-04 19:47:13 -0500
commitc71c03bda1e86c9d5198c5d83f712e695c4f2a1e (patch)
treeecb166cb3e2b7e2adb3b5e292245fefd23381ac8 /arch/arm/mach-mmp
parentea53c912f8a86a8567697115b6a0d8152beee5c8 (diff)
parent6a00f206debf8a5c8899055726ad127dbeeed098 (diff)
Merge branch 'mpi-master' into wip-k-fmlpwip-k-fmlp
Conflicts: litmus/sched_cedf.c
Diffstat (limited to 'arch/arm/mach-mmp')
-rw-r--r--arch/arm/mach-mmp/Kconfig29
-rw-r--r--arch/arm/mach-mmp/Makefile2
-rw-r--r--arch/arm/mach-mmp/aspenite.c94
-rw-r--r--arch/arm/mach-mmp/avengers_lite.c2
-rw-r--r--arch/arm/mach-mmp/brownstone.c204
-rw-r--r--arch/arm/mach-mmp/clock.h2
-rw-r--r--arch/arm/mach-mmp/common.c10
-rw-r--r--arch/arm/mach-mmp/flint.c8
-rw-r--r--arch/arm/mach-mmp/include/mach/cputype.h50
-rw-r--r--arch/arm/mach-mmp/include/mach/debug-macro.S11
-rw-r--r--arch/arm/mach-mmp/include/mach/gpio.h2
-rw-r--r--arch/arm/mach-mmp/include/mach/irqs.h4
-rw-r--r--arch/arm/mach-mmp/include/mach/memory.h2
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp-mmp2.h340
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp-pxa168.h16
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp-pxa910.h2
-rw-r--r--arch/arm/mach-mmp/include/mach/mmp2.h24
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa168.h22
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa910.h2
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-apmu.h14
-rw-r--r--arch/arm/mach-mmp/include/mach/teton_bga.h27
-rw-r--r--arch/arm/mach-mmp/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-mmp/irq-mmp2.c64
-rw-r--r--arch/arm/mach-mmp/irq-pxa168.c21
-rw-r--r--arch/arm/mach-mmp/jasper.c42
-rw-r--r--arch/arm/mach-mmp/mmp2.c36
-rw-r--r--arch/arm/mach-mmp/pxa168.c18
-rw-r--r--arch/arm/mach-mmp/pxa910.c4
-rw-r--r--arch/arm/mach-mmp/tavorevb.c2
-rw-r--r--arch/arm/mach-mmp/teton_bga.c89
-rw-r--r--arch/arm/mach-mmp/time.c41
-rw-r--r--arch/arm/mach-mmp/ttc_dkb.c6
32 files changed, 895 insertions, 297 deletions
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 6ab843eaa35b..67793a690272 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -37,25 +37,45 @@ config MACH_TTC_DKB
37 Say 'Y' here if you want to support the Marvell PXA910-based 37 Say 'Y' here if you want to support the Marvell PXA910-based
38 TTC_DKB Development Board. 38 TTC_DKB Development Board.
39 39
40config MACH_BROWNSTONE
41 bool "Marvell's Brownstone Development Platform"
42 depends on !CPU_MOHAWK
43 select CPU_MMP2
44 help
45 Say 'Y' here if you want to support the Marvell MMP2-based
46 Brown Development Platform.
47 MMP2-based board can't be co-existed with PXA168-based &
48 PXA910-based development board. Since MMP2 is compatible to
49 ARMv7 architecture.
50
40config MACH_FLINT 51config MACH_FLINT
41 bool "Marvell's Flint Development Platform" 52 bool "Marvell's Flint Development Platform"
53 depends on !CPU_MOHAWK
42 select CPU_MMP2 54 select CPU_MMP2
43 help 55 help
44 Say 'Y' here if you want to support the Marvell MMP2-based 56 Say 'Y' here if you want to support the Marvell MMP2-based
45 Flint Development Platform. 57 Flint Development Platform.
46 MMP2-based board can't be co-existed with PXA168-based & 58 MMP2-based board can't be co-existed with PXA168-based &
47 PXA910-based development board. Since MMP2 is compatible to 59 PXA910-based development board. Since MMP2 is compatible to
48 ARMv6 architecture. 60 ARMv7 architecture.
49 61
50config MACH_MARVELL_JASPER 62config MACH_MARVELL_JASPER
51 bool "Marvell's Jasper Development Platform" 63 bool "Marvell's Jasper Development Platform"
64 depends on !CPU_MOHAWK
52 select CPU_MMP2 65 select CPU_MMP2
53 help 66 help
54 Say 'Y' here if you want to support the Marvell MMP2-base 67 Say 'Y' here if you want to support the Marvell MMP2-base
55 Jasper Development Platform. 68 Jasper Development Platform.
56 MMP2-based board can't be co-existed with PXA168-based & 69 MMP2-based board can't be co-existed with PXA168-based &
57 PXA910-based development board. Since MMP2 is compatible to 70 PXA910-based development board. Since MMP2 is compatible to
58 ARMv6 architecture. 71 ARMv7 architecture.
72
73config MACH_TETON_BGA
74 bool "Marvell's PXA168 Teton BGA Development Board"
75 select CPU_PXA168
76 help
77 Say 'Y' here if you want to support the Marvell PXA168-based
78 Teton BGA Development Board.
59 79
60endmenu 80endmenu
61 81
@@ -73,8 +93,7 @@ config CPU_PXA910
73 93
74config CPU_MMP2 94config CPU_MMP2
75 bool 95 bool
76 select CPU_V6 96 select CPU_PJ4
77 select CPU_32v6K
78 help 97 help
79 Select code specific to MMP2. MMP2 is ARMv6 compatible. 98 Select code specific to MMP2. MMP2 is ARMv7 compatible.
80endif 99endif
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 8b66d06739c4..5c68382141af 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -15,5 +15,7 @@ obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o
15obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o 15obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o
16obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o 16obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
17obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o 17obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o
18obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o
18obj-$(CONFIG_MACH_FLINT) += flint.o 19obj-$(CONFIG_MACH_FLINT) += flint.o
19obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o 20obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
21obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 0629394a5fb9..06b5fa853c93 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -16,6 +16,7 @@
16#include <linux/mtd/mtd.h> 16#include <linux/mtd/mtd.h>
17#include <linux/mtd/partitions.h> 17#include <linux/mtd/partitions.h>
18#include <linux/mtd/nand.h> 18#include <linux/mtd/nand.h>
19#include <linux/interrupt.h>
19 20
20#include <asm/mach-types.h> 21#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
@@ -23,6 +24,9 @@
23#include <mach/mfp-pxa168.h> 24#include <mach/mfp-pxa168.h>
24#include <mach/pxa168.h> 25#include <mach/pxa168.h>
25#include <mach/gpio.h> 26#include <mach/gpio.h>
27#include <video/pxa168fb.h>
28#include <linux/input.h>
29#include <plat/pxa27x_keypad.h>
26 30
27#include "common.h" 31#include "common.h"
28 32
@@ -66,6 +70,43 @@ static unsigned long common_pin_config[] __initdata = {
66 GPIO115_I2S_BCLK, 70 GPIO115_I2S_BCLK,
67 GPIO116_I2S_RXD, 71 GPIO116_I2S_RXD,
68 GPIO117_I2S_TXD, 72 GPIO117_I2S_TXD,
73
74 /* LCD */
75 GPIO56_LCD_FCLK_RD,
76 GPIO57_LCD_LCLK_A0,
77 GPIO58_LCD_PCLK_WR,
78 GPIO59_LCD_DENA_BIAS,
79 GPIO60_LCD_DD0,
80 GPIO61_LCD_DD1,
81 GPIO62_LCD_DD2,
82 GPIO63_LCD_DD3,
83 GPIO64_LCD_DD4,
84 GPIO65_LCD_DD5,
85 GPIO66_LCD_DD6,
86 GPIO67_LCD_DD7,
87 GPIO68_LCD_DD8,
88 GPIO69_LCD_DD9,
89 GPIO70_LCD_DD10,
90 GPIO71_LCD_DD11,
91 GPIO72_LCD_DD12,
92 GPIO73_LCD_DD13,
93 GPIO74_LCD_DD14,
94 GPIO75_LCD_DD15,
95 GPIO76_LCD_DD16,
96 GPIO77_LCD_DD17,
97 GPIO78_LCD_DD18,
98 GPIO79_LCD_DD19,
99 GPIO80_LCD_DD20,
100 GPIO81_LCD_DD21,
101 GPIO82_LCD_DD22,
102 GPIO83_LCD_DD23,
103
104 /* Keypad */
105 GPIO109_KP_MKIN1,
106 GPIO110_KP_MKIN0,
107 GPIO111_KP_MKOUT7,
108 GPIO112_KP_MKOUT6,
109 GPIO121_KP_MKIN4,
69}; 110};
70 111
71static struct smc91x_platdata smc91x_info = { 112static struct smc91x_platdata smc91x_info = {
@@ -134,6 +175,51 @@ static struct i2c_board_info aspenite_i2c_info[] __initdata = {
134 { I2C_BOARD_INFO("wm8753", 0x1b), }, 175 { I2C_BOARD_INFO("wm8753", 0x1b), },
135}; 176};
136 177
178static struct fb_videomode video_modes[] = {
179 [0] = {
180 .pixclock = 30120,
181 .refresh = 60,
182 .xres = 800,
183 .yres = 480,
184 .hsync_len = 1,
185 .left_margin = 215,
186 .right_margin = 40,
187 .vsync_len = 1,
188 .upper_margin = 34,
189 .lower_margin = 10,
190 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
191 },
192};
193
194struct pxa168fb_mach_info aspenite_lcd_info = {
195 .id = "Graphic Frame",
196 .modes = video_modes,
197 .num_modes = ARRAY_SIZE(video_modes),
198 .pix_fmt = PIX_FMT_RGB565,
199 .io_pin_allocation_mode = PIN_MODE_DUMB_24,
200 .dumb_mode = DUMB_MODE_RGB888,
201 .active = 1,
202 .panel_rbswap = 0,
203 .invert_pixclock = 0,
204};
205
206static unsigned int aspenite_matrix_key_map[] = {
207 KEY(0, 6, KEY_UP), /* SW 4 */
208 KEY(0, 7, KEY_DOWN), /* SW 5 */
209 KEY(1, 6, KEY_LEFT), /* SW 6 */
210 KEY(1, 7, KEY_RIGHT), /* SW 7 */
211 KEY(4, 6, KEY_ENTER), /* SW 8 */
212 KEY(4, 7, KEY_ESC), /* SW 9 */
213};
214
215static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
216 .matrix_key_rows = 5,
217 .matrix_key_cols = 8,
218 .matrix_key_map = aspenite_matrix_key_map,
219 .matrix_key_map_size = ARRAY_SIZE(aspenite_matrix_key_map),
220 .debounce_interval = 30,
221};
222
137static void __init common_init(void) 223static void __init common_init(void)
138{ 224{
139 mfp_config(ARRAY_AND_SIZE(common_pin_config)); 225 mfp_config(ARRAY_AND_SIZE(common_pin_config));
@@ -143,24 +229,24 @@ static void __init common_init(void)
143 pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info)); 229 pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info));
144 pxa168_add_ssp(1); 230 pxa168_add_ssp(1);
145 pxa168_add_nand(&aspenite_nand_info); 231 pxa168_add_nand(&aspenite_nand_info);
232 pxa168_add_fb(&aspenite_lcd_info);
233 pxa168_add_keypad(&aspenite_keypad_info);
146 234
147 /* off-chip devices */ 235 /* off-chip devices */
148 platform_device_register(&smc91x_device); 236 platform_device_register(&smc91x_device);
149} 237}
150 238
151MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform") 239MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
152 .phys_io = APB_PHYS_BASE,
153 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
154 .map_io = mmp_map_io, 240 .map_io = mmp_map_io,
241 .nr_irqs = IRQ_BOARD_START,
155 .init_irq = pxa168_init_irq, 242 .init_irq = pxa168_init_irq,
156 .timer = &pxa168_timer, 243 .timer = &pxa168_timer,
157 .init_machine = common_init, 244 .init_machine = common_init,
158MACHINE_END 245MACHINE_END
159 246
160MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform") 247MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
161 .phys_io = APB_PHYS_BASE,
162 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
163 .map_io = mmp_map_io, 248 .map_io = mmp_map_io,
249 .nr_irqs = IRQ_BOARD_START,
164 .init_irq = pxa168_init_irq, 250 .init_irq = pxa168_init_irq,
165 .timer = &pxa168_timer, 251 .timer = &pxa168_timer,
166 .init_machine = common_init, 252 .init_machine = common_init,
diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c
index 69bcba11f53f..39f0878d64a0 100644
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ b/arch/arm/mach-mmp/avengers_lite.c
@@ -41,8 +41,6 @@ static void __init avengers_lite_init(void)
41} 41}
42 42
43MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform") 43MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform")
44 .phys_io = APB_PHYS_BASE,
45 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
46 .map_io = mmp_map_io, 44 .map_io = mmp_map_io,
47 .init_irq = pxa168_init_irq, 45 .init_irq = pxa168_init_irq,
48 .timer = &pxa168_timer, 46 .timer = &pxa168_timer,
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
new file mode 100644
index 000000000000..7bb78fd5a2a6
--- /dev/null
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -0,0 +1,204 @@
1/*
2 * linux/arch/arm/mach-mmp/brownstone.c
3 *
4 * Support for the Marvell Brownstone Development Platform.
5 *
6 * Copyright (C) 2009-2010 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * publishhed by the Free Software Foundation.
11 */
12
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18#include <linux/regulator/machine.h>
19#include <linux/regulator/max8649.h>
20#include <linux/regulator/fixed.h>
21#include <linux/mfd/max8925.h>
22
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25#include <mach/addr-map.h>
26#include <mach/mfp-mmp2.h>
27#include <mach/mmp2.h>
28#include <mach/irqs.h>
29
30#include "common.h"
31
32#define BROWNSTONE_NR_IRQS (IRQ_BOARD_START + 40)
33
34#define GPIO_5V_ENABLE (89)
35
36static unsigned long brownstone_pin_config[] __initdata = {
37 /* UART1 */
38 GPIO29_UART1_RXD,
39 GPIO30_UART1_TXD,
40
41 /* UART3 */
42 GPIO51_UART3_RXD,
43 GPIO52_UART3_TXD,
44
45 /* DFI */
46 GPIO168_DFI_D0,
47 GPIO167_DFI_D1,
48 GPIO166_DFI_D2,
49 GPIO165_DFI_D3,
50 GPIO107_DFI_D4,
51 GPIO106_DFI_D5,
52 GPIO105_DFI_D6,
53 GPIO104_DFI_D7,
54 GPIO111_DFI_D8,
55 GPIO164_DFI_D9,
56 GPIO163_DFI_D10,
57 GPIO162_DFI_D11,
58 GPIO161_DFI_D12,
59 GPIO110_DFI_D13,
60 GPIO109_DFI_D14,
61 GPIO108_DFI_D15,
62 GPIO143_ND_nCS0,
63 GPIO144_ND_nCS1,
64 GPIO147_ND_nWE,
65 GPIO148_ND_nRE,
66 GPIO150_ND_ALE,
67 GPIO149_ND_CLE,
68 GPIO112_ND_RDY0,
69 GPIO160_ND_RDY1,
70
71 /* PMIC */
72 PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
73
74 /* MMC0 */
75 GPIO131_MMC1_DAT3 | MFP_PULL_HIGH,
76 GPIO132_MMC1_DAT2 | MFP_PULL_HIGH,
77 GPIO133_MMC1_DAT1 | MFP_PULL_HIGH,
78 GPIO134_MMC1_DAT0 | MFP_PULL_HIGH,
79 GPIO136_MMC1_CMD | MFP_PULL_HIGH,
80 GPIO139_MMC1_CLK,
81 GPIO140_MMC1_CD | MFP_PULL_LOW,
82 GPIO141_MMC1_WP | MFP_PULL_LOW,
83
84 /* MMC1 */
85 GPIO37_MMC2_DAT3 | MFP_PULL_HIGH,
86 GPIO38_MMC2_DAT2 | MFP_PULL_HIGH,
87 GPIO39_MMC2_DAT1 | MFP_PULL_HIGH,
88 GPIO40_MMC2_DAT0 | MFP_PULL_HIGH,
89 GPIO41_MMC2_CMD | MFP_PULL_HIGH,
90 GPIO42_MMC2_CLK,
91
92 /* MMC2 */
93 GPIO165_MMC3_DAT7 | MFP_PULL_HIGH,
94 GPIO162_MMC3_DAT6 | MFP_PULL_HIGH,
95 GPIO166_MMC3_DAT5 | MFP_PULL_HIGH,
96 GPIO163_MMC3_DAT4 | MFP_PULL_HIGH,
97 GPIO167_MMC3_DAT3 | MFP_PULL_HIGH,
98 GPIO164_MMC3_DAT2 | MFP_PULL_HIGH,
99 GPIO168_MMC3_DAT1 | MFP_PULL_HIGH,
100 GPIO111_MMC3_DAT0 | MFP_PULL_HIGH,
101 GPIO112_MMC3_CMD | MFP_PULL_HIGH,
102 GPIO151_MMC3_CLK,
103
104 /* 5V regulator */
105 GPIO89_GPIO,
106};
107
108static struct regulator_consumer_supply max8649_supply[] = {
109 REGULATOR_SUPPLY("vcc_core", NULL),
110};
111
112static struct regulator_init_data max8649_init_data = {
113 .constraints = {
114 .name = "vcc_core range",
115 .min_uV = 1150000,
116 .max_uV = 1280000,
117 .always_on = 1,
118 .boot_on = 1,
119 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
120 },
121 .num_consumer_supplies = 1,
122 .consumer_supplies = &max8649_supply[0],
123};
124
125static struct max8649_platform_data brownstone_max8649_info = {
126 .mode = 2, /* VID1 = 1, VID0 = 0 */
127 .extclk = 0,
128 .ramp_timing = MAX8649_RAMP_32MV,
129 .regulator = &max8649_init_data,
130};
131
132static struct regulator_consumer_supply brownstone_v_5vp_supplies[] = {
133 REGULATOR_SUPPLY("v_5vp", NULL),
134};
135
136static struct regulator_init_data brownstone_v_5vp_data = {
137 .constraints = {
138 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
139 },
140 .num_consumer_supplies = ARRAY_SIZE(brownstone_v_5vp_supplies),
141 .consumer_supplies = brownstone_v_5vp_supplies,
142};
143
144static struct fixed_voltage_config brownstone_v_5vp = {
145 .supply_name = "v_5vp",
146 .microvolts = 5000000,
147 .gpio = GPIO_5V_ENABLE,
148 .enable_high = 1,
149 .enabled_at_boot = 1,
150 .init_data = &brownstone_v_5vp_data,
151};
152
153static struct platform_device brownstone_v_5vp_device = {
154 .name = "reg-fixed-voltage",
155 .id = 1,
156 .dev = {
157 .platform_data = &brownstone_v_5vp,
158 },
159};
160
161static struct max8925_platform_data brownstone_max8925_info = {
162 .irq_base = IRQ_BOARD_START,
163};
164
165static struct i2c_board_info brownstone_twsi1_info[] = {
166 [0] = {
167 .type = "max8649",
168 .addr = 0x60,
169 .platform_data = &brownstone_max8649_info,
170 },
171 [1] = {
172 .type = "max8925",
173 .addr = 0x3c,
174 .irq = IRQ_MMP2_PMIC,
175 .platform_data = &brownstone_max8925_info,
176 },
177};
178
179static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
180 .max_speed = 25000000,
181};
182
183static void __init brownstone_init(void)
184{
185 mfp_config(ARRAY_AND_SIZE(brownstone_pin_config));
186
187 /* on-chip devices */
188 mmp2_add_uart(1);
189 mmp2_add_uart(3);
190 mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
191 mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
192
193 /* enable 5v regulator */
194 platform_device_register(&brownstone_v_5vp_device);
195}
196
197MACHINE_START(BROWNSTONE, "Brownstone Development Platform")
198 /* Maintainer: Haojian Zhuang <haojian.zhuang@marvell.com> */
199 .map_io = mmp_map_io,
200 .nr_irqs = BROWNSTONE_NR_IRQS,
201 .init_irq = mmp2_init_irq,
202 .timer = &mmp2_timer,
203 .init_machine = brownstone_init,
204MACHINE_END
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
index 016ae94691c0..9b027d7491f5 100644
--- a/arch/arm/mach-mmp/clock.h
+++ b/arch/arm/mach-mmp/clock.h
@@ -6,7 +6,7 @@
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 */ 7 */
8 8
9#include <asm/clkdev.h> 9#include <linux/clkdev.h>
10 10
11struct clkops { 11struct clkops {
12 void (*enable)(struct clk *); 12 void (*enable)(struct clk *);
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 3b29fa7e9b08..0ec0ca80bb3e 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -10,13 +10,20 @@
10 10
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/module.h>
13 14
14#include <asm/page.h> 15#include <asm/page.h>
15#include <asm/mach/map.h> 16#include <asm/mach/map.h>
16#include <mach/addr-map.h> 17#include <mach/addr-map.h>
18#include <mach/cputype.h>
17 19
18#include "common.h" 20#include "common.h"
19 21
22#define MMP_CHIPID (AXI_VIRT_BASE + 0x82c00)
23
24unsigned int mmp_chip_id;
25EXPORT_SYMBOL(mmp_chip_id);
26
20static struct map_desc standard_io_desc[] __initdata = { 27static struct map_desc standard_io_desc[] __initdata = {
21 { 28 {
22 .pfn = __phys_to_pfn(APB_PHYS_BASE), 29 .pfn = __phys_to_pfn(APB_PHYS_BASE),
@@ -34,4 +41,7 @@ static struct map_desc standard_io_desc[] __initdata = {
34void __init mmp_map_io(void) 41void __init mmp_map_io(void)
35{ 42{
36 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 43 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
44
45 /* this is early, initialize mmp_chip_id here */
46 mmp_chip_id = __raw_readl(MMP_CHIPID);
37} 47}
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
index e4312d238eae..c4fd806b15b4 100644
--- a/arch/arm/mach-mmp/flint.c
+++ b/arch/arm/mach-mmp/flint.c
@@ -16,6 +16,7 @@
16#include <linux/smc91x.h> 16#include <linux/smc91x.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/gpio.h> 18#include <linux/gpio.h>
19#include <linux/interrupt.h>
19 20
20#include <asm/mach-types.h> 21#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
@@ -25,6 +26,8 @@
25 26
26#include "common.h" 27#include "common.h"
27 28
29#define FLINT_NR_IRQS (IRQ_BOARD_START + 48)
30
28static unsigned long flint_pin_config[] __initdata = { 31static unsigned long flint_pin_config[] __initdata = {
29 /* UART1 */ 32 /* UART1 */
30 GPIO45_UART1_RXD, 33 GPIO45_UART1_RXD,
@@ -44,7 +47,7 @@ static unsigned long flint_pin_config[] __initdata = {
44 GPIO113_SMC_RDY, 47 GPIO113_SMC_RDY,
45 48
46 /*Ethernet*/ 49 /*Ethernet*/
47 GPIO155_GPIO155, 50 GPIO155_GPIO,
48 51
49 /* DFI */ 52 /* DFI */
50 GPIO168_DFI_D0, 53 GPIO168_DFI_D0,
@@ -113,9 +116,8 @@ static void __init flint_init(void)
113} 116}
114 117
115MACHINE_START(FLINT, "Flint Development Platform") 118MACHINE_START(FLINT, "Flint Development Platform")
116 .phys_io = APB_PHYS_BASE,
117 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
118 .map_io = mmp_map_io, 119 .map_io = mmp_map_io,
120 .nr_irqs = FLINT_NR_IRQS,
119 .init_irq = mmp2_init_irq, 121 .init_irq = mmp2_init_irq,
120 .timer = &mmp2_timer, 122 .timer = &mmp2_timer,
121 .init_machine = flint_init, 123 .init_machine = flint_init,
diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h
index 83b18721d933..8a3b56dfd35d 100644
--- a/arch/arm/mach-mmp/include/mach/cputype.h
+++ b/arch/arm/mach-mmp/include/mach/cputype.h
@@ -4,36 +4,52 @@
4#include <asm/cputype.h> 4#include <asm/cputype.h>
5 5
6/* 6/*
7 * CPU Stepping OLD_ID CPU_ID CHIP_ID 7 * CPU Stepping CPU_ID CHIP_ID
8 * 8 *
9 * PXA168 A0 0x41159263 0x56158400 0x00A0A333 9 * PXA168 S0 0x56158400 0x0000C910
10 * PXA910 Y0 0x41159262 0x56158000 0x00F0C910 10 * PXA168 A0 0x56158400 0x00A0A168
11 * MMP2 Z0 0x560f5811 11 * PXA910 Y1 0x56158400 0x00F2C920
12 * PXA910 A0 0x56158400 0x00F2C910
13 * PXA910 A1 0x56158400 0x00A0C910
14 * PXA920 Y0 0x56158400 0x00F2C920
15 * PXA920 A0 0x56158400 0x00A0C920
16 * PXA920 A1 0x56158400 0x00A1C920
17 * MMP2 Z0 0x560f5811 0x00F00410
18 * MMP2 Z1 0x560f5811 0x00E00410
19 * MMP2 A0 0x560f5811 0x00A0A610
12 */ 20 */
13 21
22extern unsigned int mmp_chip_id;
23
14#ifdef CONFIG_CPU_PXA168 24#ifdef CONFIG_CPU_PXA168
15# define __cpu_is_pxa168(id) \ 25static inline int cpu_is_pxa168(void)
16 ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x84; }) 26{
27 return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
28 ((mmp_chip_id & 0xfff) == 0x168);
29}
17#else 30#else
18# define __cpu_is_pxa168(id) (0) 31#define cpu_is_pxa168() (0)
19#endif 32#endif
20 33
34/* cpu_is_pxa910() is shared on both pxa910 and pxa920 */
21#ifdef CONFIG_CPU_PXA910 35#ifdef CONFIG_CPU_PXA910
22# define __cpu_is_pxa910(id) \ 36static inline int cpu_is_pxa910(void)
23 ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; }) 37{
38 return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
39 (((mmp_chip_id & 0xfff) == 0x910) ||
40 ((mmp_chip_id & 0xfff) == 0x920));
41}
24#else 42#else
25# define __cpu_is_pxa910(id) (0) 43#define cpu_is_pxa910() (0)
26#endif 44#endif
27 45
28#ifdef CONFIG_CPU_MMP2 46#ifdef CONFIG_CPU_MMP2
29# define __cpu_is_mmp2(id) \ 47static inline int cpu_is_mmp2(void)
30 ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x58; }) 48{
49 return (((read_cpuid_id() >> 8) & 0xff) == 0x58);
50}
31#else 51#else
32# define __cpu_is_mmp2(id) (0) 52#define cpu_is_mmp2() (0)
33#endif 53#endif
34 54
35#define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); })
36#define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); })
37#define cpu_is_mmp2() ({ __cpu_is_mmp2(read_cpuid_id()); })
38
39#endif /* __ASM_MACH_CPUTYPE_H */ 55#endif /* __ASM_MACH_CPUTYPE_H */
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
index 76deff238e1c..7e2ebd3efc7c 100644
--- a/arch/arm/mach-mmp/include/mach/debug-macro.S
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -11,12 +11,11 @@
11 11
12#include <mach/addr-map.h> 12#include <mach/addr-map.h>
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mrc p15, 0, \rx, c1, c0 15 ldr \rp, =APB_PHYS_BASE @ physical
16 tst \rx, #1 @ MMU enabled? 16 ldr \rv, =APB_VIRT_BASE @ virtual
17 ldreq \rx, =APB_PHYS_BASE @ physical 17 orr \rp, \rp, #0x00017000
18 ldrne \rx, =APB_VIRT_BASE @ virtual 18 orr \rv, \rv, #0x00017000
19 orr \rx, \rx, #0x00017000
20 .endm 19 .endm
21 20
22#define UART_SHIFT 2 21#define UART_SHIFT 2
diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h
index ee8b02ed8011..7bfb827f3fe3 100644
--- a/arch/arm/mach-mmp/include/mach/gpio.h
+++ b/arch/arm/mach-mmp/include/mach/gpio.h
@@ -10,7 +10,7 @@
10#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) 10#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
11#define GPIO_REG(x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x)))) 11#define GPIO_REG(x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x))))
12 12
13#define NR_BUILTIN_GPIO (192) 13#define NR_BUILTIN_GPIO IRQ_GPIO_NUM
14 14
15#define gpio_to_bank(gpio) ((gpio) >> 5) 15#define gpio_to_bank(gpio) ((gpio) >> 5)
16#define gpio_to_irq(gpio) (IRQ_GPIO_START + (gpio)) 16#define gpio_to_irq(gpio) (IRQ_GPIO_START + (gpio))
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index b379cdec4d38..a09d328e2ddd 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -222,10 +222,8 @@
222#define IRQ_GPIO_NUM 192 222#define IRQ_GPIO_NUM 192
223#define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) 223#define IRQ_GPIO(x) (IRQ_GPIO_START + (x))
224 224
225/* Board IRQ - 64 by default, increase if not enough */
226#define IRQ_BOARD_START (IRQ_GPIO_START + IRQ_GPIO_NUM) 225#define IRQ_BOARD_START (IRQ_GPIO_START + IRQ_GPIO_NUM)
227#define IRQ_BOARD_END (IRQ_BOARD_START + 64)
228 226
229#define NR_IRQS (IRQ_BOARD_END) 227#define NR_IRQS (IRQ_BOARD_START)
230 228
231#endif /* __ASM_MACH_IRQS_H */ 229#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-mmp/include/mach/memory.h b/arch/arm/mach-mmp/include/mach/memory.h
index bdb21d70714c..d68b50a2d6a0 100644
--- a/arch/arm/mach-mmp/include/mach/memory.h
+++ b/arch/arm/mach-mmp/include/mach/memory.h
@@ -9,6 +9,6 @@
9#ifndef __ASM_MACH_MEMORY_H 9#ifndef __ASM_MACH_MEMORY_H
10#define __ASM_MACH_MEMORY_H 10#define __ASM_MACH_MEMORY_H
11 11
12#define PHYS_OFFSET UL(0x00000000) 12#define PLAT_PHYS_OFFSET UL(0x00000000)
13 13
14#endif /* __ASM_MACH_MEMORY_H */ 14#endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
index 761c2dacc079..4ad38629c3f6 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
@@ -6,178 +6,178 @@
6#define MFP_DRIVE_VERY_SLOW (0x0 << 13) 6#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
7#define MFP_DRIVE_SLOW (0x2 << 13) 7#define MFP_DRIVE_SLOW (0x2 << 13)
8#define MFP_DRIVE_MEDIUM (0x4 << 13) 8#define MFP_DRIVE_MEDIUM (0x4 << 13)
9#define MFP_DRIVE_FAST (0x8 << 13) 9#define MFP_DRIVE_FAST (0x6 << 13)
10 10
11/* GPIO */ 11/* GPIO */
12#define GPIO0_GPIO0 MFP_CFG(GPIO0, AF0) 12#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
13#define GPIO1_GPIO1 MFP_CFG(GPIO1, AF0) 13#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
14#define GPIO2_GPIO2 MFP_CFG(GPIO2, AF0) 14#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
15#define GPIO3_GPIO3 MFP_CFG(GPIO3, AF0) 15#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
16#define GPIO4_GPIO4 MFP_CFG(GPIO4, AF0) 16#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
17#define GPIO5_GPIO5 MFP_CFG(GPIO5, AF0) 17#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
18#define GPIO6_GPIO6 MFP_CFG(GPIO6, AF0) 18#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
19#define GPIO7_GPIO7 MFP_CFG(GPIO7, AF0) 19#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
20#define GPIO8_GPIO8 MFP_CFG(GPIO8, AF0) 20#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
21#define GPIO9_GPIO9 MFP_CFG(GPIO9, AF0) 21#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
22#define GPIO10_GPIO10 MFP_CFG(GPIO10, AF0) 22#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
23#define GPIO11_GPIO11 MFP_CFG(GPIO11, AF0) 23#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
24#define GPIO12_GPIO12 MFP_CFG(GPIO12, AF0) 24#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
25#define GPIO13_GPIO13 MFP_CFG(GPIO13, AF0) 25#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
26#define GPIO14_GPIO14 MFP_CFG(GPIO14, AF0) 26#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
27#define GPIO15_GPIO15 MFP_CFG(GPIO15, AF0) 27#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
28#define GPIO16_GPIO16 MFP_CFG(GPIO16, AF0) 28#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
29#define GPIO17_GPIO17 MFP_CFG(GPIO17, AF0) 29#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
30#define GPIO18_GPIO18 MFP_CFG(GPIO18, AF0) 30#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
31#define GPIO19_GPIO19 MFP_CFG(GPIO19, AF0) 31#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
32#define GPIO20_GPIO20 MFP_CFG(GPIO20, AF0) 32#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
33#define GPIO21_GPIO21 MFP_CFG(GPIO21, AF0) 33#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
34#define GPIO22_GPIO22 MFP_CFG(GPIO22, AF0) 34#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
35#define GPIO23_GPIO23 MFP_CFG(GPIO23, AF0) 35#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
36#define GPIO24_GPIO24 MFP_CFG(GPIO24, AF0) 36#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
37#define GPIO25_GPIO25 MFP_CFG(GPIO25, AF0) 37#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
38#define GPIO26_GPIO26 MFP_CFG(GPIO26, AF0) 38#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
39#define GPIO27_GPIO27 MFP_CFG(GPIO27, AF0) 39#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
40#define GPIO28_GPIO28 MFP_CFG(GPIO28, AF0) 40#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
41#define GPIO29_GPIO29 MFP_CFG(GPIO29, AF0) 41#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
42#define GPIO30_GPIO30 MFP_CFG(GPIO30, AF0) 42#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
43#define GPIO31_GPIO31 MFP_CFG(GPIO31, AF0) 43#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
44#define GPIO32_GPIO32 MFP_CFG(GPIO32, AF0) 44#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
45#define GPIO33_GPIO33 MFP_CFG(GPIO33, AF0) 45#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
46#define GPIO34_GPIO34 MFP_CFG(GPIO34, AF0) 46#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
47#define GPIO35_GPIO35 MFP_CFG(GPIO35, AF0) 47#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
48#define GPIO36_GPIO36 MFP_CFG(GPIO36, AF0) 48#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
49#define GPIO37_GPIO37 MFP_CFG(GPIO37, AF0) 49#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
50#define GPIO38_GPIO38 MFP_CFG(GPIO38, AF0) 50#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
51#define GPIO39_GPIO39 MFP_CFG(GPIO39, AF0) 51#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
52#define GPIO40_GPIO40 MFP_CFG(GPIO40, AF0) 52#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
53#define GPIO41_GPIO41 MFP_CFG(GPIO41, AF0) 53#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
54#define GPIO42_GPIO42 MFP_CFG(GPIO42, AF0) 54#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
55#define GPIO43_GPIO43 MFP_CFG(GPIO43, AF0) 55#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
56#define GPIO44_GPIO44 MFP_CFG(GPIO44, AF0) 56#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
57#define GPIO45_GPIO45 MFP_CFG(GPIO45, AF0) 57#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
58#define GPIO46_GPIO46 MFP_CFG(GPIO46, AF0) 58#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
59#define GPIO47_GPIO47 MFP_CFG(GPIO47, AF0) 59#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
60#define GPIO48_GPIO48 MFP_CFG(GPIO48, AF0) 60#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
61#define GPIO49_GPIO49 MFP_CFG(GPIO49, AF0) 61#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
62#define GPIO50_GPIO50 MFP_CFG(GPIO50, AF0) 62#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
63#define GPIO51_GPIO51 MFP_CFG(GPIO51, AF0) 63#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
64#define GPIO52_GPIO52 MFP_CFG(GPIO52, AF0) 64#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
65#define GPIO53_GPIO53 MFP_CFG(GPIO53, AF0) 65#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
66#define GPIO54_GPIO54 MFP_CFG(GPIO54, AF0) 66#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
67#define GPIO55_GPIO55 MFP_CFG(GPIO55, AF0) 67#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
68#define GPIO56_GPIO56 MFP_CFG(GPIO56, AF0) 68#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
69#define GPIO57_GPIO57 MFP_CFG(GPIO57, AF0) 69#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
70#define GPIO58_GPIO58 MFP_CFG(GPIO58, AF0) 70#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
71#define GPIO59_GPIO59 MFP_CFG(GPIO59, AF0) 71#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
72#define GPIO60_GPIO60 MFP_CFG(GPIO60, AF0) 72#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
73#define GPIO61_GPIO61 MFP_CFG(GPIO61, AF0) 73#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
74#define GPIO62_GPIO62 MFP_CFG(GPIO62, AF0) 74#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
75#define GPIO63_GPIO63 MFP_CFG(GPIO63, AF0) 75#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
76#define GPIO64_GPIO64 MFP_CFG(GPIO64, AF0) 76#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
77#define GPIO65_GPIO65 MFP_CFG(GPIO65, AF0) 77#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
78#define GPIO66_GPIO66 MFP_CFG(GPIO66, AF0) 78#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
79#define GPIO67_GPIO67 MFP_CFG(GPIO67, AF0) 79#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
80#define GPIO68_GPIO68 MFP_CFG(GPIO68, AF0) 80#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
81#define GPIO69_GPIO69 MFP_CFG(GPIO69, AF0) 81#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
82#define GPIO70_GPIO70 MFP_CFG(GPIO70, AF0) 82#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
83#define GPIO71_GPIO71 MFP_CFG(GPIO71, AF0) 83#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
84#define GPIO72_GPIO72 MFP_CFG(GPIO72, AF0) 84#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
85#define GPIO73_GPIO73 MFP_CFG(GPIO73, AF0) 85#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
86#define GPIO74_GPIO74 MFP_CFG(GPIO74, AF0) 86#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
87#define GPIO75_GPIO75 MFP_CFG(GPIO75, AF0) 87#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
88#define GPIO76_GPIO76 MFP_CFG(GPIO76, AF0) 88#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
89#define GPIO77_GPIO77 MFP_CFG(GPIO77, AF0) 89#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
90#define GPIO78_GPIO78 MFP_CFG(GPIO78, AF0) 90#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
91#define GPIO79_GPIO79 MFP_CFG(GPIO79, AF0) 91#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
92#define GPIO80_GPIO80 MFP_CFG(GPIO80, AF0) 92#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
93#define GPIO81_GPIO81 MFP_CFG(GPIO81, AF0) 93#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
94#define GPIO82_GPIO82 MFP_CFG(GPIO82, AF0) 94#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
95#define GPIO83_GPIO83 MFP_CFG(GPIO83, AF0) 95#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
96#define GPIO84_GPIO84 MFP_CFG(GPIO84, AF0) 96#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
97#define GPIO85_GPIO85 MFP_CFG(GPIO85, AF0) 97#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
98#define GPIO86_GPIO86 MFP_CFG(GPIO86, AF0) 98#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
99#define GPIO87_GPIO87 MFP_CFG(GPIO87, AF0) 99#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
100#define GPIO88_GPIO88 MFP_CFG(GPIO88, AF0) 100#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
101#define GPIO89_GPIO89 MFP_CFG(GPIO89, AF0) 101#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
102#define GPIO90_GPIO90 MFP_CFG(GPIO90, AF0) 102#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
103#define GPIO91_GPIO91 MFP_CFG(GPIO91, AF0) 103#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
104#define GPIO92_GPIO92 MFP_CFG(GPIO92, AF0) 104#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
105#define GPIO93_GPIO93 MFP_CFG(GPIO93, AF0) 105#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
106#define GPIO94_GPIO94 MFP_CFG(GPIO94, AF0) 106#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
107#define GPIO95_GPIO95 MFP_CFG(GPIO95, AF0) 107#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
108#define GPIO96_GPIO96 MFP_CFG(GPIO96, AF0) 108#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
109#define GPIO97_GPIO97 MFP_CFG(GPIO97, AF0) 109#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
110#define GPIO98_GPIO98 MFP_CFG(GPIO98, AF0) 110#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
111#define GPIO99_GPIO99 MFP_CFG(GPIO99, AF0) 111#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
112#define GPIO100_GPIO100 MFP_CFG(GPIO100, AF0) 112#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
113#define GPIO101_GPIO101 MFP_CFG(GPIO101, AF0) 113#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
114#define GPIO102_GPIO102 MFP_CFG(GPIO102, AF1) 114#define GPIO102_GPIO MFP_CFG(GPIO102, AF1)
115#define GPIO103_GPIO103 MFP_CFG(GPIO103, AF1) 115#define GPIO103_GPIO MFP_CFG(GPIO103, AF1)
116#define GPIO104_GPIO104 MFP_CFG(GPIO104, AF1) 116#define GPIO104_GPIO MFP_CFG(GPIO104, AF1)
117#define GPIO105_GPIO105 MFP_CFG(GPIO105, AF1) 117#define GPIO105_GPIO MFP_CFG(GPIO105, AF1)
118#define GPIO106_GPIO106 MFP_CFG(GPIO106, AF1) 118#define GPIO106_GPIO MFP_CFG(GPIO106, AF1)
119#define GPIO107_GPIO107 MFP_CFG(GPIO107, AF1) 119#define GPIO107_GPIO MFP_CFG(GPIO107, AF1)
120#define GPIO108_GPIO108 MFP_CFG(GPIO108, AF1) 120#define GPIO108_GPIO MFP_CFG(GPIO108, AF1)
121#define GPIO109_GPIO109 MFP_CFG(GPIO109, AF1) 121#define GPIO109_GPIO MFP_CFG(GPIO109, AF1)
122#define GPIO110_GPIO110 MFP_CFG(GPIO110, AF1) 122#define GPIO110_GPIO MFP_CFG(GPIO110, AF1)
123#define GPIO111_GPIO111 MFP_CFG(GPIO111, AF1) 123#define GPIO111_GPIO MFP_CFG(GPIO111, AF1)
124#define GPIO112_GPIO112 MFP_CFG(GPIO112, AF1) 124#define GPIO112_GPIO MFP_CFG(GPIO112, AF1)
125#define GPIO113_GPIO113 MFP_CFG(GPIO113, AF1) 125#define GPIO113_GPIO MFP_CFG(GPIO113, AF1)
126#define GPIO114_GPIO114 MFP_CFG(GPIO114, AF0) 126#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
127#define GPIO115_GPIO115 MFP_CFG(GPIO115, AF0) 127#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
128#define GPIO116_GPIO116 MFP_CFG(GPIO116, AF0) 128#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
129#define GPIO117_GPIO117 MFP_CFG(GPIO117, AF0) 129#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
130#define GPIO118_GPIO118 MFP_CFG(GPIO118, AF0) 130#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
131#define GPIO119_GPIO119 MFP_CFG(GPIO119, AF0) 131#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
132#define GPIO120_GPIO120 MFP_CFG(GPIO120, AF0) 132#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
133#define GPIO121_GPIO121 MFP_CFG(GPIO121, AF0) 133#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
134#define GPIO122_GPIO122 MFP_CFG(GPIO122, AF0) 134#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
135#define GPIO123_GPIO123 MFP_CFG(GPIO123, AF0) 135#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
136#define GPIO124_GPIO124 MFP_CFG(GPIO124, AF0) 136#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
137#define GPIO125_GPIO125 MFP_CFG(GPIO125, AF0) 137#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
138#define GPIO126_GPIO126 MFP_CFG(GPIO126, AF0) 138#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
139#define GPIO127_GPIO127 MFP_CFG(GPIO127, AF0) 139#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
140#define GPIO128_GPIO128 MFP_CFG(GPIO128, AF0) 140#define GPIO128_GPIO MFP_CFG(GPIO128, AF0)
141#define GPIO129_GPIO129 MFP_CFG(GPIO129, AF0) 141#define GPIO129_GPIO MFP_CFG(GPIO129, AF0)
142#define GPIO130_GPIO130 MFP_CFG(GPIO130, AF0) 142#define GPIO130_GPIO MFP_CFG(GPIO130, AF0)
143#define GPIO131_GPIO131 MFP_CFG(GPIO131, AF0) 143#define GPIO131_GPIO MFP_CFG(GPIO131, AF0)
144#define GPIO132_GPIO132 MFP_CFG(GPIO132, AF0) 144#define GPIO132_GPIO MFP_CFG(GPIO132, AF0)
145#define GPIO133_GPIO133 MFP_CFG(GPIO133, AF0) 145#define GPIO133_GPIO MFP_CFG(GPIO133, AF0)
146#define GPIO134_GPIO134 MFP_CFG(GPIO134, AF0) 146#define GPIO134_GPIO MFP_CFG(GPIO134, AF0)
147#define GPIO135_GPIO135 MFP_CFG(GPIO135, AF0) 147#define GPIO135_GPIO MFP_CFG(GPIO135, AF0)
148#define GPIO136_GPIO136 MFP_CFG(GPIO136, AF0) 148#define GPIO136_GPIO MFP_CFG(GPIO136, AF0)
149#define GPIO137_GPIO137 MFP_CFG(GPIO137, AF0) 149#define GPIO137_GPIO MFP_CFG(GPIO137, AF0)
150#define GPIO138_GPIO138 MFP_CFG(GPIO138, AF0) 150#define GPIO138_GPIO MFP_CFG(GPIO138, AF0)
151#define GPIO139_GPIO139 MFP_CFG(GPIO139, AF0) 151#define GPIO139_GPIO MFP_CFG(GPIO139, AF0)
152#define GPIO140_GPIO140 MFP_CFG(GPIO140, AF0) 152#define GPIO140_GPIO MFP_CFG(GPIO140, AF0)
153#define GPIO141_GPIO141 MFP_CFG(GPIO141, AF0) 153#define GPIO141_GPIO MFP_CFG(GPIO141, AF0)
154#define GPIO142_GPIO142 MFP_CFG(GPIO142, AF1) 154#define GPIO142_GPIO MFP_CFG(GPIO142, AF1)
155#define GPIO143_GPIO143 MFP_CFG(GPIO143, AF1) 155#define GPIO143_GPIO MFP_CFG(GPIO143, AF1)
156#define GPIO144_GPIO144 MFP_CFG(GPIO144, AF1) 156#define GPIO144_GPIO MFP_CFG(GPIO144, AF1)
157#define GPIO145_GPIO145 MFP_CFG(GPIO145, AF1) 157#define GPIO145_GPIO MFP_CFG(GPIO145, AF1)
158#define GPIO146_GPIO146 MFP_CFG(GPIO146, AF1) 158#define GPIO146_GPIO MFP_CFG(GPIO146, AF1)
159#define GPIO147_GPIO147 MFP_CFG(GPIO147, AF1) 159#define GPIO147_GPIO MFP_CFG(GPIO147, AF1)
160#define GPIO148_GPIO148 MFP_CFG(GPIO148, AF1) 160#define GPIO148_GPIO MFP_CFG(GPIO148, AF1)
161#define GPIO149_GPIO149 MFP_CFG(GPIO149, AF1) 161#define GPIO149_GPIO MFP_CFG(GPIO149, AF1)
162#define GPIO150_GPIO150 MFP_CFG(GPIO150, AF1) 162#define GPIO150_GPIO MFP_CFG(GPIO150, AF1)
163#define GPIO151_GPIO151 MFP_CFG(GPIO151, AF1) 163#define GPIO151_GPIO MFP_CFG(GPIO151, AF1)
164#define GPIO152_GPIO152 MFP_CFG(GPIO152, AF1) 164#define GPIO152_GPIO MFP_CFG(GPIO152, AF1)
165#define GPIO153_GPIO153 MFP_CFG(GPIO153, AF1) 165#define GPIO153_GPIO MFP_CFG(GPIO153, AF1)
166#define GPIO154_GPIO154 MFP_CFG(GPIO154, AF1) 166#define GPIO154_GPIO MFP_CFG(GPIO154, AF1)
167#define GPIO155_GPIO155 MFP_CFG(GPIO155, AF1) 167#define GPIO155_GPIO MFP_CFG(GPIO155, AF1)
168#define GPIO156_GPIO156 MFP_CFG(GPIO156, AF1) 168#define GPIO156_GPIO MFP_CFG(GPIO156, AF1)
169#define GPIO157_GPIO157 MFP_CFG(GPIO157, AF1) 169#define GPIO157_GPIO MFP_CFG(GPIO157, AF1)
170#define GPIO158_GPIO158 MFP_CFG(GPIO158, AF1) 170#define GPIO158_GPIO MFP_CFG(GPIO158, AF1)
171#define GPIO159_GPIO159 MFP_CFG(GPIO159, AF1) 171#define GPIO159_GPIO MFP_CFG(GPIO159, AF1)
172#define GPIO160_GPIO160 MFP_CFG(GPIO160, AF1) 172#define GPIO160_GPIO MFP_CFG(GPIO160, AF1)
173#define GPIO161_GPIO161 MFP_CFG(GPIO161, AF1) 173#define GPIO161_GPIO MFP_CFG(GPIO161, AF1)
174#define GPIO162_GPIO162 MFP_CFG(GPIO162, AF1) 174#define GPIO162_GPIO MFP_CFG(GPIO162, AF1)
175#define GPIO163_GPIO163 MFP_CFG(GPIO163, AF1) 175#define GPIO163_GPIO MFP_CFG(GPIO163, AF1)
176#define GPIO164_GPIO164 MFP_CFG(GPIO164, AF1) 176#define GPIO164_GPIO MFP_CFG(GPIO164, AF1)
177#define GPIO165_GPIO165 MFP_CFG(GPIO165, AF1) 177#define GPIO165_GPIO MFP_CFG(GPIO165, AF1)
178#define GPIO166_GPIO166 MFP_CFG(GPIO166, AF1) 178#define GPIO166_GPIO MFP_CFG(GPIO166, AF1)
179#define GPIO167_GPIO167 MFP_CFG(GPIO167, AF1) 179#define GPIO167_GPIO MFP_CFG(GPIO167, AF1)
180#define GPIO168_GPIO168 MFP_CFG(GPIO168, AF1) 180#define GPIO168_GPIO MFP_CFG(GPIO168, AF1)
181 181
182/* DFI */ 182/* DFI */
183#define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0) 183#define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0)
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
index ded43c455ec3..713be155a44d 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -8,6 +8,15 @@
8#define MFP_DRIVE_MEDIUM (0x2 << 13) 8#define MFP_DRIVE_MEDIUM (0x2 << 13)
9#define MFP_DRIVE_FAST (0x3 << 13) 9#define MFP_DRIVE_FAST (0x3 << 13)
10 10
11#undef MFP_CFG
12#undef MFP_CFG_DRV
13
14#define MFP_CFG(pin, af) \
15 (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
16
17#define MFP_CFG_DRV(pin, af, drv) \
18 (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
19
11/* GPIO */ 20/* GPIO */
12#define GPIO0_GPIO MFP_CFG(GPIO0, AF5) 21#define GPIO0_GPIO MFP_CFG(GPIO0, AF5)
13#define GPIO1_GPIO MFP_CFG(GPIO1, AF5) 22#define GPIO1_GPIO MFP_CFG(GPIO1, AF5)
@@ -289,4 +298,11 @@
289#define GPIO86_PWM1_OUT MFP_CFG(GPIO86, AF2) 298#define GPIO86_PWM1_OUT MFP_CFG(GPIO86, AF2)
290#define GPIO86_PWM2_OUT MFP_CFG(GPIO86, AF3) 299#define GPIO86_PWM2_OUT MFP_CFG(GPIO86, AF3)
291 300
301/* Keypad */
302#define GPIO109_KP_MKIN1 MFP_CFG(GPIO109, AF7)
303#define GPIO110_KP_MKIN0 MFP_CFG(GPIO110, AF7)
304#define GPIO111_KP_MKOUT7 MFP_CFG(GPIO111, AF7)
305#define GPIO112_KP_MKOUT6 MFP_CFG(GPIO112, AF7)
306#define GPIO121_KP_MKIN4 MFP_CFG(GPIO121, AF7)
307
292#endif /* __ASM_MACH_MFP_PXA168_H */ 308#endif /* __ASM_MACH_MFP_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
index 7e8a80f25ddc..fbd7ee8e4897 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h
@@ -6,7 +6,7 @@
6#define MFP_DRIVE_VERY_SLOW (0x0 << 13) 6#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
7#define MFP_DRIVE_SLOW (0x2 << 13) 7#define MFP_DRIVE_SLOW (0x2 << 13)
8#define MFP_DRIVE_MEDIUM (0x4 << 13) 8#define MFP_DRIVE_MEDIUM (0x4 << 13)
9#define MFP_DRIVE_FAST (0x8 << 13) 9#define MFP_DRIVE_FAST (0x6 << 13)
10 10
11/* UART2 */ 11/* UART2 */
12#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6) 12#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6)
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h
index dbba6e8a60c4..2cbf6df09b82 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -1,6 +1,8 @@
1#ifndef __ASM_MACH_MMP2_H 1#ifndef __ASM_MACH_MMP2_H
2#define __ASM_MACH_MMP2_H 2#define __ASM_MACH_MMP2_H
3 3
4#include <plat/sdhci.h>
5
4struct sys_timer; 6struct sys_timer;
5 7
6extern struct sys_timer mmp2_timer; 8extern struct sys_timer mmp2_timer;
@@ -9,8 +11,8 @@ extern void __init mmp2_init_irq(void);
9extern void mmp2_clear_pmic_int(void); 11extern void mmp2_clear_pmic_int(void);
10 12
11#include <linux/i2c.h> 13#include <linux/i2c.h>
14#include <linux/i2c/pxa-i2c.h>
12#include <mach/devices.h> 15#include <mach/devices.h>
13#include <plat/i2c.h>
14 16
15extern struct pxa_device_desc mmp2_device_uart1; 17extern struct pxa_device_desc mmp2_device_uart1;
16extern struct pxa_device_desc mmp2_device_uart2; 18extern struct pxa_device_desc mmp2_device_uart2;
@@ -22,6 +24,10 @@ extern struct pxa_device_desc mmp2_device_twsi3;
22extern struct pxa_device_desc mmp2_device_twsi4; 24extern struct pxa_device_desc mmp2_device_twsi4;
23extern struct pxa_device_desc mmp2_device_twsi5; 25extern struct pxa_device_desc mmp2_device_twsi5;
24extern struct pxa_device_desc mmp2_device_twsi6; 26extern struct pxa_device_desc mmp2_device_twsi6;
27extern struct pxa_device_desc mmp2_device_sdh0;
28extern struct pxa_device_desc mmp2_device_sdh1;
29extern struct pxa_device_desc mmp2_device_sdh2;
30extern struct pxa_device_desc mmp2_device_sdh3;
25 31
26static inline int mmp2_add_uart(int id) 32static inline int mmp2_add_uart(int id)
27{ 33{
@@ -63,5 +69,21 @@ static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data,
63 return pxa_register_device(d, data, sizeof(*data)); 69 return pxa_register_device(d, data, sizeof(*data));
64} 70}
65 71
72static inline int mmp2_add_sdhost(int id, struct sdhci_pxa_platdata *data)
73{
74 struct pxa_device_desc *d = NULL;
75
76 switch (id) {
77 case 0: d = &mmp2_device_sdh0; break;
78 case 1: d = &mmp2_device_sdh1; break;
79 case 2: d = &mmp2_device_sdh2; break;
80 case 3: d = &mmp2_device_sdh3; break;
81 default:
82 return -EINVAL;
83 }
84
85 return pxa_register_device(d, data, sizeof(*data));
86}
87
66#endif /* __ASM_MACH_MMP2_H */ 88#endif /* __ASM_MACH_MMP2_H */
67 89
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 27e1bc758623..a52b3d2f325c 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -5,11 +5,15 @@ struct sys_timer;
5 5
6extern struct sys_timer pxa168_timer; 6extern struct sys_timer pxa168_timer;
7extern void __init pxa168_init_irq(void); 7extern void __init pxa168_init_irq(void);
8extern void pxa168_clear_keypad_wakeup(void);
8 9
9#include <linux/i2c.h> 10#include <linux/i2c.h>
11#include <linux/i2c/pxa-i2c.h>
10#include <mach/devices.h> 12#include <mach/devices.h>
11#include <plat/i2c.h>
12#include <plat/pxa3xx_nand.h> 13#include <plat/pxa3xx_nand.h>
14#include <video/pxa168fb.h>
15#include <plat/pxa27x_keypad.h>
16#include <mach/cputype.h>
13 17
14extern struct pxa_device_desc pxa168_device_uart1; 18extern struct pxa_device_desc pxa168_device_uart1;
15extern struct pxa_device_desc pxa168_device_uart2; 19extern struct pxa_device_desc pxa168_device_uart2;
@@ -25,6 +29,8 @@ extern struct pxa_device_desc pxa168_device_ssp3;
25extern struct pxa_device_desc pxa168_device_ssp4; 29extern struct pxa_device_desc pxa168_device_ssp4;
26extern struct pxa_device_desc pxa168_device_ssp5; 30extern struct pxa_device_desc pxa168_device_ssp5;
27extern struct pxa_device_desc pxa168_device_nand; 31extern struct pxa_device_desc pxa168_device_nand;
32extern struct pxa_device_desc pxa168_device_fb;
33extern struct pxa_device_desc pxa168_device_keypad;
28 34
29static inline int pxa168_add_uart(int id) 35static inline int pxa168_add_uart(int id)
30{ 36{
@@ -97,4 +103,18 @@ static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info)
97{ 103{
98 return pxa_register_device(&pxa168_device_nand, info, sizeof(*info)); 104 return pxa_register_device(&pxa168_device_nand, info, sizeof(*info));
99} 105}
106
107static inline int pxa168_add_fb(struct pxa168fb_mach_info *mi)
108{
109 return pxa_register_device(&pxa168_device_fb, mi, sizeof(*mi));
110}
111
112static inline int pxa168_add_keypad(struct pxa27x_keypad_platform_data *data)
113{
114 if (cpu_is_pxa168())
115 data->clear_wakeup_event = pxa168_clear_keypad_wakeup;
116
117 return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data));
118}
119
100#endif /* __ASM_MACH_PXA168_H */ 120#endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index f13c49d6f8dc..91be75591398 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -7,8 +7,8 @@ extern struct sys_timer pxa910_timer;
7extern void __init pxa910_init_irq(void); 7extern void __init pxa910_init_irq(void);
8 8
9#include <linux/i2c.h> 9#include <linux/i2c.h>
10#include <linux/i2c/pxa-i2c.h>
10#include <mach/devices.h> 11#include <mach/devices.h>
11#include <plat/i2c.h>
12#include <plat/pxa3xx_nand.h> 12#include <plat/pxa3xx_nand.h>
13 13
14extern struct pxa_device_desc pxa910_device_uart1; 14extern struct pxa_device_desc pxa910_device_uart1;
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 919030514120..f7011ef70bf5 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -27,10 +27,24 @@
27#define APMU_DMA APMU_REG(0x064) 27#define APMU_DMA APMU_REG(0x064)
28#define APMU_GEU APMU_REG(0x068) 28#define APMU_GEU APMU_REG(0x068)
29#define APMU_BUS APMU_REG(0x06c) 29#define APMU_BUS APMU_REG(0x06c)
30#define APMU_SDH2 APMU_REG(0x0e8)
31#define APMU_SDH3 APMU_REG(0x0ec)
30 32
31#define APMU_FNCLK_EN (1 << 4) 33#define APMU_FNCLK_EN (1 << 4)
32#define APMU_AXICLK_EN (1 << 3) 34#define APMU_AXICLK_EN (1 << 3)
33#define APMU_FNRST_DIS (1 << 1) 35#define APMU_FNRST_DIS (1 << 1)
34#define APMU_AXIRST_DIS (1 << 0) 36#define APMU_AXIRST_DIS (1 << 0)
35 37
38/* Wake Clear Register */
39#define APMU_WAKE_CLR APMU_REG(0x07c)
40
41#define APMU_PXA168_KP_WAKE_CLR (1 << 7)
42#define APMU_PXA168_CFI_WAKE_CLR (1 << 6)
43#define APMU_PXA168_XD_WAKE_CLR (1 << 5)
44#define APMU_PXA168_MSP_WAKE_CLR (1 << 4)
45#define APMU_PXA168_SD4_WAKE_CLR (1 << 3)
46#define APMU_PXA168_SD3_WAKE_CLR (1 << 2)
47#define APMU_PXA168_SD2_WAKE_CLR (1 << 1)
48#define APMU_PXA168_SD1_WAKE_CLR (1 << 0)
49
36#endif /* __ASM_MACH_REGS_APMU_H */ 50#endif /* __ASM_MACH_REGS_APMU_H */
diff --git a/arch/arm/mach-mmp/include/mach/teton_bga.h b/arch/arm/mach-mmp/include/mach/teton_bga.h
new file mode 100644
index 000000000000..61a539b2cc98
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/teton_bga.h
@@ -0,0 +1,27 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/teton_bga.h
3 *
4 * Support for the Marvell PXA168 Teton BGA Development Platform.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 */
10#ifndef __ASM_MACH_TETON_BGA_H
11#define __ASM_MACH_TETON_BGA_H
12
13/* GPIOs */
14#define MMC_PWENA_GPIO 27
15#define USBHPENB_GPIO 55
16#define RTC_INT_GPIO 78
17#define LCD_VBLK_EN_GPIO 79
18#define LCD_DVDD_EN_GPIO 80
19#define RST_WIFI_GPIO 81
20#define CF_PWEN_GPIO 82
21#define USB_OC_GPIO 83
22#define PWM_GPIO 84
23#define USBHPENA_GPIO 85
24#define TS_INT_GPIO 86
25#define CIR_GPIO 108
26
27#endif /* __ASM_MACH_TETON_BGA_H */
diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h
index 85bd8a2d84b5..d6daeb7e4ef1 100644
--- a/arch/arm/mach-mmp/include/mach/uncompress.h
+++ b/arch/arm/mach-mmp/include/mach/uncompress.h
@@ -14,7 +14,7 @@
14#define UART2_BASE (APB_PHYS_BASE + 0x17000) 14#define UART2_BASE (APB_PHYS_BASE + 0x17000)
15#define UART3_BASE (APB_PHYS_BASE + 0x18000) 15#define UART3_BASE (APB_PHYS_BASE + 0x18000)
16 16
17static volatile unsigned long *UART; 17volatile unsigned long *UART;
18 18
19static inline void putc(char c) 19static inline void putc(char c)
20{ 20{
diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c
index 01342be91c3c..d21c5441a3d0 100644
--- a/arch/arm/mach-mmp/irq-mmp2.c
+++ b/arch/arm/mach-mmp/irq-mmp2.c
@@ -20,48 +20,48 @@
20 20
21#include "common.h" 21#include "common.h"
22 22
23static void icu_mask_irq(unsigned int irq) 23static void icu_mask_irq(struct irq_data *d)
24{ 24{
25 uint32_t r = __raw_readl(ICU_INT_CONF(irq)); 25 uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
26 26
27 r &= ~ICU_INT_ROUTE_PJ4_IRQ; 27 r &= ~ICU_INT_ROUTE_PJ4_IRQ;
28 __raw_writel(r, ICU_INT_CONF(irq)); 28 __raw_writel(r, ICU_INT_CONF(d->irq));
29} 29}
30 30
31static void icu_unmask_irq(unsigned int irq) 31static void icu_unmask_irq(struct irq_data *d)
32{ 32{
33 uint32_t r = __raw_readl(ICU_INT_CONF(irq)); 33 uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
34 34
35 r |= ICU_INT_ROUTE_PJ4_IRQ; 35 r |= ICU_INT_ROUTE_PJ4_IRQ;
36 __raw_writel(r, ICU_INT_CONF(irq)); 36 __raw_writel(r, ICU_INT_CONF(d->irq));
37} 37}
38 38
39static struct irq_chip icu_irq_chip = { 39static struct irq_chip icu_irq_chip = {
40 .name = "icu_irq", 40 .name = "icu_irq",
41 .mask = icu_mask_irq, 41 .irq_mask = icu_mask_irq,
42 .mask_ack = icu_mask_irq, 42 .irq_mask_ack = icu_mask_irq,
43 .unmask = icu_unmask_irq, 43 .irq_unmask = icu_unmask_irq,
44}; 44};
45 45
46static void pmic_irq_ack(unsigned int irq) 46static void pmic_irq_ack(struct irq_data *d)
47{ 47{
48 if (irq == IRQ_MMP2_PMIC) 48 if (d->irq == IRQ_MMP2_PMIC)
49 mmp2_clear_pmic_int(); 49 mmp2_clear_pmic_int();
50} 50}
51 51
52#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \ 52#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \
53static void _name_##_mask_irq(unsigned int irq) \ 53static void _name_##_mask_irq(struct irq_data *d) \
54{ \ 54{ \
55 uint32_t r; \ 55 uint32_t r; \
56 r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base)); \ 56 r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base)); \
57 __raw_writel(r, prefix##_MASK); \ 57 __raw_writel(r, prefix##_MASK); \
58} 58}
59 59
60#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ 60#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
61static void _name_##_unmask_irq(unsigned int irq) \ 61static void _name_##_unmask_irq(struct irq_data *d) \
62{ \ 62{ \
63 uint32_t r; \ 63 uint32_t r; \
64 r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base)); \ 64 r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base)); \
65 __raw_writel(r, prefix##_MASK); \ 65 __raw_writel(r, prefix##_MASK); \
66} 66}
67 67
@@ -88,8 +88,8 @@ SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
88SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ 88SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
89static struct irq_chip _name_##_irq_chip = { \ 89static struct irq_chip _name_##_irq_chip = { \
90 .name = #_name_, \ 90 .name = #_name_, \
91 .mask = _name_##_mask_irq, \ 91 .irq_mask = _name_##_mask_irq, \
92 .unmask = _name_##_unmask_irq, \ 92 .irq_unmask = _name_##_unmask_irq, \
93} 93}
94 94
95SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4); 95SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
@@ -103,14 +103,16 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num)
103 int irq; 103 int irq;
104 104
105 for (irq = start; num > 0; irq++, num--) { 105 for (irq = start; num > 0; irq++, num--) {
106 struct irq_data *d = irq_get_irq_data(irq);
107
106 /* mask and clear the IRQ */ 108 /* mask and clear the IRQ */
107 chip->mask(irq); 109 chip->irq_mask(d);
108 if (chip->ack) 110 if (chip->irq_ack)
109 chip->ack(irq); 111 chip->irq_ack(d);
110 112
111 set_irq_chip(irq, chip); 113 irq_set_chip(irq, chip);
112 set_irq_flags(irq, IRQF_VALID); 114 set_irq_flags(irq, IRQF_VALID);
113 set_irq_handler(irq, handle_level_irq); 115 irq_set_handler(irq, handle_level_irq);
114 } 116 }
115} 117}
116 118
@@ -119,8 +121,8 @@ void __init mmp2_init_icu(void)
119 int irq; 121 int irq;
120 122
121 for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { 123 for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
122 icu_mask_irq(irq); 124 icu_mask_irq(irq_get_irq_data(irq));
123 set_irq_chip(irq, &icu_irq_chip); 125 irq_set_chip(irq, &icu_irq_chip);
124 set_irq_flags(irq, IRQF_VALID); 126 set_irq_flags(irq, IRQF_VALID);
125 127
126 switch (irq) { 128 switch (irq) {
@@ -131,7 +133,7 @@ void __init mmp2_init_icu(void)
131 case IRQ_MMP2_SSP_MUX: 133 case IRQ_MMP2_SSP_MUX:
132 break; 134 break;
133 default: 135 default:
134 set_irq_handler(irq, handle_level_irq); 136 irq_set_handler(irq, handle_level_irq);
135 break; 137 break;
136 } 138 }
137 } 139 }
@@ -139,7 +141,7 @@ void __init mmp2_init_icu(void)
139 /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register 141 /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
140 * to be written to clear the interrupt 142 * to be written to clear the interrupt
141 */ 143 */
142 pmic_irq_chip.ack = pmic_irq_ack; 144 pmic_irq_chip.irq_ack = pmic_irq_ack;
143 145
144 init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2); 146 init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
145 init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2); 147 init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
@@ -147,9 +149,9 @@ void __init mmp2_init_icu(void)
147 init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); 149 init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
148 init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); 150 init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
149 151
150 set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); 152 irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
151 set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); 153 irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
152 set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); 154 irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
153 set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); 155 irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
154 set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); 156 irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
155} 157}
diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c
index 52ff2f065eba..89706a0d08f1 100644
--- a/arch/arm/mach-mmp/irq-pxa168.c
+++ b/arch/arm/mach-mmp/irq-pxa168.c
@@ -25,21 +25,21 @@
25#define PRIORITY_DEFAULT 0x1 25#define PRIORITY_DEFAULT 0x1
26#define PRIORITY_NONE 0x0 /* means IRQ disabled */ 26#define PRIORITY_NONE 0x0 /* means IRQ disabled */
27 27
28static void icu_mask_irq(unsigned int irq) 28static void icu_mask_irq(struct irq_data *d)
29{ 29{
30 __raw_writel(PRIORITY_NONE, ICU_INT_CONF(irq)); 30 __raw_writel(PRIORITY_NONE, ICU_INT_CONF(d->irq));
31} 31}
32 32
33static void icu_unmask_irq(unsigned int irq) 33static void icu_unmask_irq(struct irq_data *d)
34{ 34{
35 __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(irq)); 35 __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(d->irq));
36} 36}
37 37
38static struct irq_chip icu_irq_chip = { 38static struct irq_chip icu_irq_chip = {
39 .name = "icu_irq", 39 .name = "icu_irq",
40 .ack = icu_mask_irq, 40 .irq_ack = icu_mask_irq,
41 .mask = icu_mask_irq, 41 .irq_mask = icu_mask_irq,
42 .unmask = icu_unmask_irq, 42 .irq_unmask = icu_unmask_irq,
43}; 43};
44 44
45void __init icu_init_irq(void) 45void __init icu_init_irq(void)
@@ -47,9 +47,8 @@ void __init icu_init_irq(void)
47 int irq; 47 int irq;
48 48
49 for (irq = 0; irq < 64; irq++) { 49 for (irq = 0; irq < 64; irq++) {
50 icu_mask_irq(irq); 50 icu_mask_irq(irq_get_irq_data(irq));
51 set_irq_chip(irq, &icu_irq_chip); 51 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
52 set_irq_handler(irq, handle_level_irq);
53 set_irq_flags(irq, IRQF_VALID); 52 set_irq_flags(irq, IRQF_VALID);
54 } 53 }
55} 54}
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 80c3e7ab1e17..24172a0aad59 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -18,16 +18,18 @@
18#include <linux/regulator/machine.h> 18#include <linux/regulator/machine.h>
19#include <linux/regulator/max8649.h> 19#include <linux/regulator/max8649.h>
20#include <linux/mfd/max8925.h> 20#include <linux/mfd/max8925.h>
21#include <linux/interrupt.h>
21 22
22#include <asm/mach-types.h> 23#include <asm/mach-types.h>
23#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
24#include <mach/addr-map.h> 25#include <mach/addr-map.h>
25#include <mach/mfp-mmp2.h> 26#include <mach/mfp-mmp2.h>
26#include <mach/mmp2.h> 27#include <mach/mmp2.h>
27#include <mach/irqs.h>
28 28
29#include "common.h" 29#include "common.h"
30 30
31#define JASPER_NR_IRQS (IRQ_BOARD_START + 48)
32
31static unsigned long jasper_pin_config[] __initdata = { 33static unsigned long jasper_pin_config[] __initdata = {
32 /* UART1 */ 34 /* UART1 */
33 GPIO29_UART1_RXD, 35 GPIO29_UART1_RXD,
@@ -65,6 +67,36 @@ static unsigned long jasper_pin_config[] __initdata = {
65 67
66 /* PMIC */ 68 /* PMIC */
67 PMIC_PMIC_INT | MFP_LPM_EDGE_FALL, 69 PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
70
71 /* MMC1 */
72 GPIO131_MMC1_DAT3,
73 GPIO132_MMC1_DAT2,
74 GPIO133_MMC1_DAT1,
75 GPIO134_MMC1_DAT0,
76 GPIO136_MMC1_CMD,
77 GPIO139_MMC1_CLK,
78 GPIO140_MMC1_CD,
79 GPIO141_MMC1_WP,
80
81 /* MMC2 */
82 GPIO37_MMC2_DAT3,
83 GPIO38_MMC2_DAT2,
84 GPIO39_MMC2_DAT1,
85 GPIO40_MMC2_DAT0,
86 GPIO41_MMC2_CMD,
87 GPIO42_MMC2_CLK,
88
89 /* MMC3 */
90 GPIO165_MMC3_DAT7,
91 GPIO162_MMC3_DAT6,
92 GPIO166_MMC3_DAT5,
93 GPIO163_MMC3_DAT4,
94 GPIO167_MMC3_DAT3,
95 GPIO164_MMC3_DAT2,
96 GPIO168_MMC3_DAT1,
97 GPIO111_MMC3_DAT0,
98 GPIO112_MMC3_CMD,
99 GPIO151_MMC3_CLK,
68}; 100};
69 101
70static struct regulator_consumer_supply max8649_supply[] = { 102static struct regulator_consumer_supply max8649_supply[] = {
@@ -121,6 +153,10 @@ static struct i2c_board_info jasper_twsi1_info[] = {
121 }, 153 },
122}; 154};
123 155
156static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
157 .max_speed = 25000000,
158};
159
124static void __init jasper_init(void) 160static void __init jasper_init(void)
125{ 161{
126 mfp_config(ARRAY_AND_SIZE(jasper_pin_config)); 162 mfp_config(ARRAY_AND_SIZE(jasper_pin_config));
@@ -129,14 +165,14 @@ static void __init jasper_init(void)
129 mmp2_add_uart(1); 165 mmp2_add_uart(1);
130 mmp2_add_uart(3); 166 mmp2_add_uart(3);
131 mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info)); 167 mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));
168 mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
132 169
133 regulator_has_full_constraints(); 170 regulator_has_full_constraints();
134} 171}
135 172
136MACHINE_START(MARVELL_JASPER, "Jasper Development Platform") 173MACHINE_START(MARVELL_JASPER, "Jasper Development Platform")
137 .phys_io = APB_PHYS_BASE,
138 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
139 .map_io = mmp_map_io, 174 .map_io = mmp_map_io,
175 .nr_irqs = JASPER_NR_IRQS,
140 .init_irq = mmp2_init_irq, 176 .init_irq = mmp2_init_irq,
141 .timer = &mmp2_timer, 177 .timer = &mmp2_timer,
142 .init_machine = jasper_init, 178 .init_machine = jasper_init,
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index daf3993349f8..8e6c3ac7f7c1 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -115,6 +115,29 @@ void __init mmp2_init_irq(void)
115 mmp2_init_gpio(); 115 mmp2_init_gpio();
116} 116}
117 117
118static void sdhc_clk_enable(struct clk *clk)
119{
120 uint32_t clk_rst;
121
122 clk_rst = __raw_readl(clk->clk_rst);
123 clk_rst |= clk->enable_val;
124 __raw_writel(clk_rst, clk->clk_rst);
125}
126
127static void sdhc_clk_disable(struct clk *clk)
128{
129 uint32_t clk_rst;
130
131 clk_rst = __raw_readl(clk->clk_rst);
132 clk_rst &= ~clk->enable_val;
133 __raw_writel(clk_rst, clk->clk_rst);
134}
135
136struct clkops sdhc_clk_ops = {
137 .enable = sdhc_clk_enable,
138 .disable = sdhc_clk_disable,
139};
140
118/* APB peripheral clocks */ 141/* APB peripheral clocks */
119static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); 142static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
120static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); 143static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
@@ -126,9 +149,12 @@ static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
126static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); 149static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
127static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); 150static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
128static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); 151static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
129static APBC_CLK(rtc, MMP2_RTC, 0, 32768);
130 152
131static APMU_CLK(nand, NAND, 0xbf, 100000000); 153static APMU_CLK(nand, NAND, 0xbf, 100000000);
154static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
155static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
156static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
157static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
132 158
133static struct clk_lookup mmp2_clkregs[] = { 159static struct clk_lookup mmp2_clkregs[] = {
134 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), 160 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
@@ -142,6 +168,10 @@ static struct clk_lookup mmp2_clkregs[] = {
142 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), 168 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
143 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), 169 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
144 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), 170 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
171 INIT_CLKREG(&clk_sdh0, "sdhci-pxa.0", "PXA-SDHCLK"),
172 INIT_CLKREG(&clk_sdh1, "sdhci-pxa.1", "PXA-SDHCLK"),
173 INIT_CLKREG(&clk_sdh2, "sdhci-pxa.2", "PXA-SDHCLK"),
174 INIT_CLKREG(&clk_sdh3, "sdhci-pxa.3", "PXA-SDHCLK"),
145}; 175};
146 176
147static int __init mmp2_init(void) 177static int __init mmp2_init(void)
@@ -192,4 +222,8 @@ MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
192MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); 222MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
193MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); 223MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
194MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); 224MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
225MMP2_DEVICE(sdh0, "sdhci-pxa", 0, MMC, 0xd4280000, 0x120);
226MMP2_DEVICE(sdh1, "sdhci-pxa", 1, MMC2, 0xd4280800, 0x120);
227MMP2_DEVICE(sdh2, "sdhci-pxa", 2, MMC3, 0xd4281000, 0x120);
228MMP2_DEVICE(sdh3, "sdhci-pxa", 3, MMC4, 0xd4281800, 0x120);
195 229
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 652ae660634c..ab9f999106c7 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -77,8 +77,10 @@ static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
77static APBC_CLK(ssp3, PXA168_SSP3, 4, 0); 77static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
78static APBC_CLK(ssp4, PXA168_SSP4, 4, 0); 78static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
79static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); 79static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
80static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
80 81
81static APMU_CLK(nand, NAND, 0x01db, 208000000); 82static APMU_CLK(nand, NAND, 0x19b, 156000000);
83static APMU_CLK(lcd, LCD, 0x7f, 312000000);
82 84
83/* device and clock bindings */ 85/* device and clock bindings */
84static struct clk_lookup pxa168_clkregs[] = { 86static struct clk_lookup pxa168_clkregs[] = {
@@ -96,6 +98,8 @@ static struct clk_lookup pxa168_clkregs[] = {
96 INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), 98 INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
97 INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), 99 INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
98 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), 100 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
101 INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
102 INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
99}; 103};
100 104
101static int __init pxa168_init(void) 105static int __init pxa168_init(void)
@@ -132,6 +136,16 @@ struct sys_timer pxa168_timer = {
132 .init = pxa168_timer_init, 136 .init = pxa168_timer_init,
133}; 137};
134 138
139void pxa168_clear_keypad_wakeup(void)
140{
141 uint32_t val;
142 uint32_t mask = APMU_PXA168_KP_WAKE_CLR;
143
144 /* wake event clear is needed in order to clear keypad interrupt */
145 val = __raw_readl(APMU_WAKE_CLR);
146 __raw_writel(val | mask, APMU_WAKE_CLR);
147}
148
135/* on-chip devices */ 149/* on-chip devices */
136PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22); 150PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
137PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24); 151PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
@@ -147,3 +161,5 @@ PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55);
147PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57); 161PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57);
148PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59); 162PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
149PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61); 163PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
164PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
165PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 46f2d69bef3c..1464607aa60d 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -110,7 +110,8 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
110static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); 110static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
111static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); 111static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
112 112
113static APMU_CLK(nand, NAND, 0x01db, 208000000); 113static APMU_CLK(nand, NAND, 0x19b, 156000000);
114static APMU_CLK(u2o, USB, 0x1b, 480000000);
114 115
115/* device and clock bindings */ 116/* device and clock bindings */
116static struct clk_lookup pxa910_clkregs[] = { 117static struct clk_lookup pxa910_clkregs[] = {
@@ -123,6 +124,7 @@ static struct clk_lookup pxa910_clkregs[] = {
123 INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), 124 INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
124 INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), 125 INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
125 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), 126 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
127 INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"),
126}; 128};
127 129
128static int __init pxa910_init(void) 130static int __init pxa910_init(void)
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
index e81db7428215..c296b75c4453 100644
--- a/arch/arm/mach-mmp/tavorevb.c
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -99,8 +99,6 @@ static void __init tavorevb_init(void)
99} 99}
100 100
101MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)") 101MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)")
102 .phys_io = APB_PHYS_BASE,
103 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
104 .map_io = mmp_map_io, 102 .map_io = mmp_map_io,
105 .init_irq = pxa910_init_irq, 103 .init_irq = pxa910_init_irq,
106 .timer = &pxa910_timer, 104 .timer = &pxa910_timer,
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
new file mode 100644
index 000000000000..bbe4727b96cc
--- /dev/null
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -0,0 +1,89 @@
1/*
2 * linux/arch/arm/mach-mmp/teton_bga.c
3 *
4 * Support for the Marvell PXA168 Teton BGA Development Platform.
5 *
6 * Author: Mark F. Brown <mark.brown314@gmail.com>
7 *
8 * This code is based on aspenite.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * publishhed by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18#include <linux/gpio.h>
19#include <linux/input.h>
20#include <plat/pxa27x_keypad.h>
21#include <linux/i2c.h>
22
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25#include <mach/addr-map.h>
26#include <mach/mfp-pxa168.h>
27#include <mach/pxa168.h>
28#include <mach/teton_bga.h>
29
30#include "common.h"
31
32static unsigned long teton_bga_pin_config[] __initdata = {
33 /* UART1 */
34 GPIO107_UART1_TXD,
35 GPIO108_UART1_RXD,
36
37 /* Keypad */
38 GPIO109_KP_MKIN1,
39 GPIO110_KP_MKIN0,
40 GPIO111_KP_MKOUT7,
41 GPIO112_KP_MKOUT6,
42
43 /* I2C Bus */
44 GPIO105_CI2C_SDA,
45 GPIO106_CI2C_SCL,
46
47 /* RTC */
48 GPIO78_GPIO,
49};
50
51static unsigned int teton_bga_matrix_key_map[] = {
52 KEY(0, 6, KEY_ESC),
53 KEY(0, 7, KEY_ENTER),
54 KEY(1, 6, KEY_LEFT),
55 KEY(1, 7, KEY_RIGHT),
56};
57
58static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {
59 .matrix_key_rows = 2,
60 .matrix_key_cols = 8,
61 .matrix_key_map = teton_bga_matrix_key_map,
62 .matrix_key_map_size = ARRAY_SIZE(teton_bga_matrix_key_map),
63 .debounce_interval = 30,
64};
65
66static struct i2c_board_info teton_bga_i2c_info[] __initdata = {
67 {
68 I2C_BOARD_INFO("ds1337", 0x68),
69 .irq = gpio_to_irq(RTC_INT_GPIO)
70 },
71};
72
73static void __init teton_bga_init(void)
74{
75 mfp_config(ARRAY_AND_SIZE(teton_bga_pin_config));
76
77 /* on-chip devices */
78 pxa168_add_uart(1);
79 pxa168_add_keypad(&teton_bga_keypad_info);
80 pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info));
81}
82
83MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform")
84 .map_io = mmp_map_io,
85 .nr_irqs = IRQ_BOARD_START,
86 .init_irq = pxa168_init_irq,
87 .timer = &pxa168_timer,
88 .init_machine = teton_bga_init,
89MACHINE_END
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 66528193f939..99833b9485cf 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -9,7 +9,7 @@
9 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com> 9 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
10 * 2008-10-08: Bin Yang <bin.yang@marvell.com> 10 * 2008-10-08: Bin Yang <bin.yang@marvell.com>
11 * 11 *
12 * The timers module actually includes three timers, each timer with upto 12 * The timers module actually includes three timers, each timer with up to
13 * three match comparators. Timer #0 is used here in free-running mode as 13 * three match comparators. Timer #0 is used here in free-running mode as
14 * the clock source, and match comparator #1 used as clock event device. 14 * the clock source, and match comparator #1 used as clock event device.
15 * 15 *
@@ -26,8 +26,8 @@
26#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/irq.h> 27#include <linux/irq.h>
28#include <linux/sched.h> 28#include <linux/sched.h>
29#include <linux/cnt32_to_63.h>
30 29
30#include <asm/sched_clock.h>
31#include <mach/addr-map.h> 31#include <mach/addr-map.h>
32#include <mach/regs-timers.h> 32#include <mach/regs-timers.h>
33#include <mach/regs-apbc.h> 33#include <mach/regs-apbc.h>
@@ -42,23 +42,7 @@
42#define MAX_DELTA (0xfffffffe) 42#define MAX_DELTA (0xfffffffe)
43#define MIN_DELTA (16) 43#define MIN_DELTA (16)
44 44
45#define TCR2NS_SCALE_FACTOR 10 45static DEFINE_CLOCK_DATA(cd);
46
47static unsigned long tcr2ns_scale;
48
49static void __init set_tcr2ns_scale(unsigned long tcr_rate)
50{
51 unsigned long long v = 1000000000ULL << TCR2NS_SCALE_FACTOR;
52 do_div(v, tcr_rate);
53 tcr2ns_scale = v;
54 /*
55 * We want an even value to automatically clear the top bit
56 * returned by cnt32_to_63() without an additional run time
57 * instruction. So if the LSB is 1 then round it up.
58 */
59 if (tcr2ns_scale & 1)
60 tcr2ns_scale++;
61}
62 46
63/* 47/*
64 * FIXME: the timer needs some delay to stablize the counter capture 48 * FIXME: the timer needs some delay to stablize the counter capture
@@ -75,10 +59,16 @@ static inline uint32_t timer_read(void)
75 return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(0)); 59 return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(0));
76} 60}
77 61
78unsigned long long sched_clock(void) 62unsigned long long notrace sched_clock(void)
79{ 63{
80 unsigned long long v = cnt32_to_63(timer_read()); 64 u32 cyc = timer_read();
81 return (v * tcr2ns_scale) >> TCR2NS_SCALE_FACTOR; 65 return cyc_to_sched_clock(&cd, cyc, (u32)~0);
66}
67
68static void notrace mmp_update_sched_clock(void)
69{
70 u32 cyc = timer_read();
71 update_sched_clock(&cd, cyc, (u32)~0);
82} 72}
83 73
84static irqreturn_t timer_interrupt(int irq, void *dev_id) 74static irqreturn_t timer_interrupt(int irq, void *dev_id)
@@ -146,7 +136,6 @@ static cycle_t clksrc_read(struct clocksource *cs)
146 136
147static struct clocksource cksrc = { 137static struct clocksource cksrc = {
148 .name = "clocksource", 138 .name = "clocksource",
149 .shift = 20,
150 .rating = 200, 139 .rating = 200,
151 .read = clksrc_read, 140 .read = clksrc_read,
152 .mask = CLOCKSOURCE_MASK(32), 141 .mask = CLOCKSOURCE_MASK(32),
@@ -186,17 +175,15 @@ void __init timer_init(int irq)
186{ 175{
187 timer_config(); 176 timer_config();
188 177
189 set_tcr2ns_scale(CLOCK_TICK_RATE); 178 init_sched_clock(&cd, mmp_update_sched_clock, 32, CLOCK_TICK_RATE);
190 179
191 ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift); 180 ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
192 ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt); 181 ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt);
193 ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt); 182 ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt);
194 ckevt.cpumask = cpumask_of(0); 183 ckevt.cpumask = cpumask_of(0);
195 184
196 cksrc.mult = clocksource_hz2mult(CLOCK_TICK_RATE, cksrc.shift);
197
198 setup_irq(irq, &timer_irq); 185 setup_irq(irq, &timer_irq);
199 186
200 clocksource_register(&cksrc); 187 clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
201 clockevents_register_device(&ckevt); 188 clockevents_register_device(&ckevt);
202} 189}
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index ee65e05f0cf1..e411039ea59e 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -14,6 +14,7 @@
14#include <linux/mtd/mtd.h> 14#include <linux/mtd/mtd.h>
15#include <linux/mtd/partitions.h> 15#include <linux/mtd/partitions.h>
16#include <linux/mtd/onenand.h> 16#include <linux/mtd/onenand.h>
17#include <linux/interrupt.h>
17 18
18#include <asm/mach-types.h> 19#include <asm/mach-types.h>
19#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
@@ -24,6 +25,8 @@
24 25
25#include "common.h" 26#include "common.h"
26 27
28#define TTCDKB_NR_IRQS (IRQ_BOARD_START + 24)
29
27static unsigned long ttc_dkb_pin_config[] __initdata = { 30static unsigned long ttc_dkb_pin_config[] __initdata = {
28 /* UART2 */ 31 /* UART2 */
29 GPIO47_UART2_RXD, 32 GPIO47_UART2_RXD,
@@ -122,9 +125,8 @@ static void __init ttc_dkb_init(void)
122} 125}
123 126
124MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform") 127MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
125 .phys_io = APB_PHYS_BASE,
126 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
127 .map_io = mmp_map_io, 128 .map_io = mmp_map_io,
129 .nr_irqs = TTCDKB_NR_IRQS,
128 .init_irq = pxa910_init_irq, 130 .init_irq = pxa910_init_irq,
129 .timer = &pxa910_timer, 131 .timer = &pxa910_timer,
130 .init_machine = ttc_dkb_init, 132 .init_machine = ttc_dkb_init,
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-04 23:17:56 -0400