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authorHaojian Zhuang <haojian.zhuang@gmail.com>2012-04-12 07:02:02 -0400
committerHaojian Zhuang <haojian.zhuang@gmail.com>2012-05-05 04:35:13 -0400
commitc24b31147a0615abd6f15c9e2b6349191860db35 (patch)
treee3a3f228a5ae10b0eb1f5ea2e76496d8a529c19d /arch/arm/mach-mmp/irq-mmp2.c
parent3f4dd3224df9664a44bf05df56c7c12622f7a1c7 (diff)
ARM: mmp: support DT in irq
Merge irq-pxa168 and irq-mmp2. And support device tree also. Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, base irq starts from NR_IRQS_LEGACY. Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-mmp/irq-mmp2.c')
-rw-r--r--arch/arm/mach-mmp/irq-mmp2.c158
1 files changed, 0 insertions, 158 deletions
diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c
deleted file mode 100644
index 7895d277421e..000000000000
--- a/arch/arm/mach-mmp/irq-mmp2.c
+++ /dev/null
@@ -1,158 +0,0 @@
1/*
2 * linux/arch/arm/mach-mmp/irq-mmp2.c
3 *
4 * Generic IRQ handling, GPIO IRQ demultiplexing, etc.
5 *
6 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
7 * Copyright: Marvell International Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17
18#include <mach/irqs.h>
19#include <mach/regs-icu.h>
20#include <mach/mmp2.h>
21
22#include "common.h"
23
24static void icu_mask_irq(struct irq_data *d)
25{
26 uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
27
28 r &= ~ICU_INT_ROUTE_PJ4_IRQ;
29 __raw_writel(r, ICU_INT_CONF(d->irq));
30}
31
32static void icu_unmask_irq(struct irq_data *d)
33{
34 uint32_t r = __raw_readl(ICU_INT_CONF(d->irq));
35
36 r |= ICU_INT_ROUTE_PJ4_IRQ;
37 __raw_writel(r, ICU_INT_CONF(d->irq));
38}
39
40static struct irq_chip icu_irq_chip = {
41 .name = "icu_irq",
42 .irq_mask = icu_mask_irq,
43 .irq_mask_ack = icu_mask_irq,
44 .irq_unmask = icu_unmask_irq,
45};
46
47static void pmic_irq_ack(struct irq_data *d)
48{
49 if (d->irq == IRQ_MMP2_PMIC)
50 mmp2_clear_pmic_int();
51}
52
53#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \
54static void _name_##_mask_irq(struct irq_data *d) \
55{ \
56 uint32_t r; \
57 r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base)); \
58 __raw_writel(r, prefix##_MASK); \
59}
60
61#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
62static void _name_##_unmask_irq(struct irq_data *d) \
63{ \
64 uint32_t r; \
65 r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base)); \
66 __raw_writel(r, prefix##_MASK); \
67}
68
69#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
70static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \
71{ \
72 unsigned long status, mask, n; \
73 mask = __raw_readl(prefix##_MASK); \
74 while (1) { \
75 status = __raw_readl(prefix##_STATUS) & ~mask; \
76 if (status == 0) \
77 break; \
78 n = find_first_bit(&status, BITS_PER_LONG); \
79 while (n < BITS_PER_LONG) { \
80 generic_handle_irq(irq_base + n); \
81 n = find_next_bit(&status, BITS_PER_LONG, n+1); \
82 } \
83 } \
84}
85
86#define SECOND_IRQ_CHIP(_name_, irq_base, prefix) \
87SECOND_IRQ_MASK(_name_, irq_base, prefix) \
88SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \
89SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \
90static struct irq_chip _name_##_irq_chip = { \
91 .name = #_name_, \
92 .irq_mask = _name_##_mask_irq, \
93 .irq_unmask = _name_##_unmask_irq, \
94}
95
96SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4);
97SECOND_IRQ_CHIP(rtc, IRQ_MMP2_RTC_BASE, MMP2_ICU_INT5);
98SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17);
99SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35);
100SECOND_IRQ_CHIP(ssp, IRQ_MMP2_SSP_BASE, MMP2_ICU_INT51);
101
102static void init_mux_irq(struct irq_chip *chip, int start, int num)
103{
104 int irq;
105
106 for (irq = start; num > 0; irq++, num--) {
107 struct irq_data *d = irq_get_irq_data(irq);
108
109 /* mask and clear the IRQ */
110 chip->irq_mask(d);
111 if (chip->irq_ack)
112 chip->irq_ack(d);
113
114 irq_set_chip(irq, chip);
115 set_irq_flags(irq, IRQF_VALID);
116 irq_set_handler(irq, handle_level_irq);
117 }
118}
119
120void __init mmp2_init_icu(void)
121{
122 int irq;
123
124 for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
125 icu_mask_irq(irq_get_irq_data(irq));
126 irq_set_chip(irq, &icu_irq_chip);
127 set_irq_flags(irq, IRQF_VALID);
128
129 switch (irq) {
130 case IRQ_MMP2_PMIC_MUX:
131 case IRQ_MMP2_RTC_MUX:
132 case IRQ_MMP2_TWSI_MUX:
133 case IRQ_MMP2_MISC_MUX:
134 case IRQ_MMP2_SSP_MUX:
135 break;
136 default:
137 irq_set_handler(irq, handle_level_irq);
138 break;
139 }
140 }
141
142 /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register
143 * to be written to clear the interrupt
144 */
145 pmic_irq_chip.irq_ack = pmic_irq_ack;
146
147 init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2);
148 init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2);
149 init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5);
150 init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
151 init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
152
153 irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
154 irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
155 irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
156 irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
157 irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
158}
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