diff options
author | Lennert Buytenhek <buytenh@wantstofly.org> | 2010-11-29 04:36:07 -0500 |
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committer | Lennert Buytenhek <buytenh@wantstofly.org> | 2011-01-13 11:18:45 -0500 |
commit | a157f26b2e624ce457a8f16b54d93f6af1850f85 (patch) | |
tree | 367633c4f38e648d07aeff05e2a38e604d929471 /arch/arm/mach-mmp/irq-mmp2.c | |
parent | 5638538117ea81063b0611a7374c0d65133860ec (diff) |
ARM: mmp: irq_data conversion.
Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
Diffstat (limited to 'arch/arm/mach-mmp/irq-mmp2.c')
-rw-r--r-- | arch/arm/mach-mmp/irq-mmp2.c | 46 |
1 files changed, 24 insertions, 22 deletions
diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c index 01342be91c3c..fa037038e7b8 100644 --- a/arch/arm/mach-mmp/irq-mmp2.c +++ b/arch/arm/mach-mmp/irq-mmp2.c | |||
@@ -20,48 +20,48 @@ | |||
20 | 20 | ||
21 | #include "common.h" | 21 | #include "common.h" |
22 | 22 | ||
23 | static void icu_mask_irq(unsigned int irq) | 23 | static void icu_mask_irq(struct irq_data *d) |
24 | { | 24 | { |
25 | uint32_t r = __raw_readl(ICU_INT_CONF(irq)); | 25 | uint32_t r = __raw_readl(ICU_INT_CONF(d->irq)); |
26 | 26 | ||
27 | r &= ~ICU_INT_ROUTE_PJ4_IRQ; | 27 | r &= ~ICU_INT_ROUTE_PJ4_IRQ; |
28 | __raw_writel(r, ICU_INT_CONF(irq)); | 28 | __raw_writel(r, ICU_INT_CONF(d->irq)); |
29 | } | 29 | } |
30 | 30 | ||
31 | static void icu_unmask_irq(unsigned int irq) | 31 | static void icu_unmask_irq(struct irq_data *d) |
32 | { | 32 | { |
33 | uint32_t r = __raw_readl(ICU_INT_CONF(irq)); | 33 | uint32_t r = __raw_readl(ICU_INT_CONF(d->irq)); |
34 | 34 | ||
35 | r |= ICU_INT_ROUTE_PJ4_IRQ; | 35 | r |= ICU_INT_ROUTE_PJ4_IRQ; |
36 | __raw_writel(r, ICU_INT_CONF(irq)); | 36 | __raw_writel(r, ICU_INT_CONF(d->irq)); |
37 | } | 37 | } |
38 | 38 | ||
39 | static struct irq_chip icu_irq_chip = { | 39 | static struct irq_chip icu_irq_chip = { |
40 | .name = "icu_irq", | 40 | .name = "icu_irq", |
41 | .mask = icu_mask_irq, | 41 | .irq_mask = icu_mask_irq, |
42 | .mask_ack = icu_mask_irq, | 42 | .irq_mask_ack = icu_mask_irq, |
43 | .unmask = icu_unmask_irq, | 43 | .irq_unmask = icu_unmask_irq, |
44 | }; | 44 | }; |
45 | 45 | ||
46 | static void pmic_irq_ack(unsigned int irq) | 46 | static void pmic_irq_ack(struct irq_data *d) |
47 | { | 47 | { |
48 | if (irq == IRQ_MMP2_PMIC) | 48 | if (d->irq == IRQ_MMP2_PMIC) |
49 | mmp2_clear_pmic_int(); | 49 | mmp2_clear_pmic_int(); |
50 | } | 50 | } |
51 | 51 | ||
52 | #define SECOND_IRQ_MASK(_name_, irq_base, prefix) \ | 52 | #define SECOND_IRQ_MASK(_name_, irq_base, prefix) \ |
53 | static void _name_##_mask_irq(unsigned int irq) \ | 53 | static void _name_##_mask_irq(struct irq_data *d) \ |
54 | { \ | 54 | { \ |
55 | uint32_t r; \ | 55 | uint32_t r; \ |
56 | r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base)); \ | 56 | r = __raw_readl(prefix##_MASK) | (1 << (d->irq - irq_base)); \ |
57 | __raw_writel(r, prefix##_MASK); \ | 57 | __raw_writel(r, prefix##_MASK); \ |
58 | } | 58 | } |
59 | 59 | ||
60 | #define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ | 60 | #define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ |
61 | static void _name_##_unmask_irq(unsigned int irq) \ | 61 | static void _name_##_unmask_irq(struct irq_data *d) \ |
62 | { \ | 62 | { \ |
63 | uint32_t r; \ | 63 | uint32_t r; \ |
64 | r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base)); \ | 64 | r = __raw_readl(prefix##_MASK) & ~(1 << (d->irq - irq_base)); \ |
65 | __raw_writel(r, prefix##_MASK); \ | 65 | __raw_writel(r, prefix##_MASK); \ |
66 | } | 66 | } |
67 | 67 | ||
@@ -88,8 +88,8 @@ SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ | |||
88 | SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ | 88 | SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ |
89 | static struct irq_chip _name_##_irq_chip = { \ | 89 | static struct irq_chip _name_##_irq_chip = { \ |
90 | .name = #_name_, \ | 90 | .name = #_name_, \ |
91 | .mask = _name_##_mask_irq, \ | 91 | .irq_mask = _name_##_mask_irq, \ |
92 | .unmask = _name_##_unmask_irq, \ | 92 | .irq_unmask = _name_##_unmask_irq, \ |
93 | } | 93 | } |
94 | 94 | ||
95 | SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4); | 95 | SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4); |
@@ -103,10 +103,12 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num) | |||
103 | int irq; | 103 | int irq; |
104 | 104 | ||
105 | for (irq = start; num > 0; irq++, num--) { | 105 | for (irq = start; num > 0; irq++, num--) { |
106 | struct irq_data *d = irq_get_irq_data(irq); | ||
107 | |||
106 | /* mask and clear the IRQ */ | 108 | /* mask and clear the IRQ */ |
107 | chip->mask(irq); | 109 | chip->irq_mask(d); |
108 | if (chip->ack) | 110 | if (chip->irq_ack) |
109 | chip->ack(irq); | 111 | chip->irq_ack(d); |
110 | 112 | ||
111 | set_irq_chip(irq, chip); | 113 | set_irq_chip(irq, chip); |
112 | set_irq_flags(irq, IRQF_VALID); | 114 | set_irq_flags(irq, IRQF_VALID); |
@@ -119,7 +121,7 @@ void __init mmp2_init_icu(void) | |||
119 | int irq; | 121 | int irq; |
120 | 122 | ||
121 | for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { | 123 | for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { |
122 | icu_mask_irq(irq); | 124 | icu_mask_irq(irq_get_irq_data(irq)); |
123 | set_irq_chip(irq, &icu_irq_chip); | 125 | set_irq_chip(irq, &icu_irq_chip); |
124 | set_irq_flags(irq, IRQF_VALID); | 126 | set_irq_flags(irq, IRQF_VALID); |
125 | 127 | ||
@@ -139,7 +141,7 @@ void __init mmp2_init_icu(void) | |||
139 | /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register | 141 | /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register |
140 | * to be written to clear the interrupt | 142 | * to be written to clear the interrupt |
141 | */ | 143 | */ |
142 | pmic_irq_chip.ack = pmic_irq_ack; | 144 | pmic_irq_chip.irq_ack = pmic_irq_ack; |
143 | 145 | ||
144 | init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2); | 146 | init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2); |
145 | init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2); | 147 | init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2); |