ARM: mmp: support DT in irq

Merge irq-pxa168 and irq-mmp2. And support device tree also.

Since CONFIG_SPARSE_IRQ is enabled in arch-mmp, base irq starts from
NR_IRQS_LEGACY.

Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>

2 files changed, 22 insertions, 9 deletions

diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
index 9cff9e7a2b26..bd152e24e6d7 100644
--- a/arch/arm/mach-mmp/include/mach/entry-macro.S
+++ b/arch/arm/mach-mmp/include/mach/entry-macro.S
@@ -6,13 +6,15 @@
  * published by the Free Software Foundation.
  */
 
+#include <asm/irq.h>
 #include <mach/regs-icu.h>
 
         .macro  get_irqnr_preamble, base, tmp
         mrc     p15, 0, \tmp, c0, c0, 0         @ CPUID
         and     \tmp, \tmp, #0xff00
         cmp     \tmp, #0x5800
-        ldr     \base, =ICU_VIRT_BASE
+        ldr     \base, =mmp_icu_base
+        ldr     \base, [\base, #0]
         addne   \base, \base, #0x10c            @ PJ1 AP INT SEL register
         addeq   \base, \base, #0x104            @ PJ4 IRQ SEL register
         .endm
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index d0e746626a3d..fb492a50a817 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -125,7 +125,7 @@
 #define IRQ_MMP2_RTC_MUX                5
 #define IRQ_MMP2_TWSI1                  7
 #define IRQ_MMP2_GPU                    8
-#define IRQ_MMP2_KEYPAD                 9
+#define IRQ_MMP2_KEYPAD_MUX             9
 #define IRQ_MMP2_ROTARY                 10
 #define IRQ_MMP2_TRACKBALL              11
 #define IRQ_MMP2_ONEWIRE                12
@@ -163,11 +163,11 @@
 #define IRQ_MMP2_DMA_FIQ                47
 #define IRQ_MMP2_DMA_RIQ                48
 #define IRQ_MMP2_GPIO                   49
-#define IRQ_MMP2_SSP_MUX                51
+#define IRQ_MMP2_MIPI_HSI1_MUX          51
 #define IRQ_MMP2_MMC2                   52
 #define IRQ_MMP2_MMC3                   53
 #define IRQ_MMP2_MMC4                   54
-#define IRQ_MMP2_MIPI_HSI               55
+#define IRQ_MMP2_MIPI_HSI0_MUX          55
 #define IRQ_MMP2_MSP                    58
 #define IRQ_MMP2_MIPI_SLIM_DMA          59
 #define IRQ_MMP2_PJ4_FREQ_CHG           60
@@ -186,8 +186,14 @@
 #define IRQ_MMP2_RTC_ALARM              (IRQ_MMP2_RTC_BASE + 0)
 #define IRQ_MMP2_RTC                    (IRQ_MMP2_RTC_BASE + 1)
 
+/* secondary interrupt of INT #9 */
+#define IRQ_MMP2_KEYPAD_BASE            (IRQ_MMP2_RTC_BASE + 2)
+#define IRQ_MMP2_KPC                    (IRQ_MMP2_KEYPAD_BASE + 0)
+#define IRQ_MMP2_ROTORY                 (IRQ_MMP2_KEYPAD_BASE + 1)
+#define IRQ_MMP2_TBALL                  (IRQ_MMP2_KEYPAD_BASE + 2)
+
 /* secondary interrupt of INT #17 */
-#define IRQ_MMP2_TWSI_BASE              (IRQ_MMP2_RTC_BASE + 2)
+#define IRQ_MMP2_TWSI_BASE              (IRQ_MMP2_KEYPAD_BASE + 3)
 #define IRQ_MMP2_TWSI2                  (IRQ_MMP2_TWSI_BASE + 0)
 #define IRQ_MMP2_TWSI3                  (IRQ_MMP2_TWSI_BASE + 1)
 #define IRQ_MMP2_TWSI4                  (IRQ_MMP2_TWSI_BASE + 2)
@@ -212,11 +218,16 @@
 #define IRQ_MMP2_COMMRX                 (IRQ_MMP2_MISC_BASE + 14)
 
 /* secondary interrupt of INT #51 */
-#define IRQ_MMP2_SSP_BASE               (IRQ_MMP2_MISC_BASE + 15)
-#define IRQ_MMP2_SSP1_SRDY              (IRQ_MMP2_SSP_BASE + 0)
-#define IRQ_MMP2_SSP3_SRDY              (IRQ_MMP2_SSP_BASE + 1)
+#define IRQ_MMP2_MIPI_HSI1_BASE         (IRQ_MMP2_MISC_BASE + 15)
+#define IRQ_MMP2_HSI1_CAWAKE            (IRQ_MMP2_MIPI_HSI1_BASE + 0)
+#define IRQ_MMP2_MIPI_HSI_INT1          (IRQ_MMP2_MIPI_HSI1_BASE + 1)
+
+/* secondary interrupt of INT #55 */
+#define IRQ_MMP2_MIPI_HSI0_BASE         (IRQ_MMP2_MIPI_HSI1_BASE + 2)
+#define IRQ_MMP2_HSI0_CAWAKE            (IRQ_MMP2_MIPI_HSI0_BASE + 0)
+#define IRQ_MMP2_MIPI_HSI_INT0          (IRQ_MMP2_MIPI_HSI0_BASE + 1)
 
-#define IRQ_MMP2_MUX_END                (IRQ_MMP2_SSP_BASE + 2)
+#define IRQ_MMP2_MUX_END                (IRQ_MMP2_MIPI_HSI0_BASE + 2)
 
 #define IRQ_GPIO_START                  128
 #define MMP_NR_BUILTIN_GPIO             192