Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (370 commits)
  ARM: S3C2443: Add set_rate and round_rate calls for armdiv clock
  ARM: S3C2443: Remove #if 0 for clk_mpll
  ARM: S3C2443: Update notes on MPLLREF clock
  ARM: S3C2443: Further clksrc-clk conversions
  ARM: S3C2443: Change to using plat-samsung clksrc-clk implementation
  USB: Fix s3c-hsotg build following Samsung platform header moves
  ARM: S3C64XX: Reintroduce unconditional build of audio device
  ARM: 5961/1: ux500: fix CLKRST addresses
  ARM: 5977/1: arm: Enable backtrace printing on oops when PC is corrupted
  ASoC: Fix S3C64xx IIS driver for Samsung header reorg
  ARM: S3C2440: Fix plat-s3c24xx move of s3c2440/s3c2442 support
  [ARM] pxa: fix typo in mxm8x10.h
  [ARM] pxa/raumfeld: set GPIO drive bits for LED pins
  [ARM] pxa/zeus: Add support for mcp2515 CAN bus
  [ARM] pxa/zeus: Add support for onboard max6369 watchdog
  [ARM] pxa/zeus: Add Eurotech as the manufacturer
  [ARM] pxa/zeus: Correct the USB host initialisation flags
  [ARM] pxa/zeus: Allow usage of 8250-compatible UART in uncompress
  [ARM] pxa: refactor uncompress.h for non-PXA uarts
  [ARM] mmp2: fix incorrect calling of chip->mask_ack() for 2nd level cascaded IRQs
  ...

1 files changed, 41 insertions, 0 deletions

diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 98ccbee4bd0c..712af03fd1af 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -69,6 +69,47 @@
 #define APBC_PXA910_ASFAR       APBC_REG(0x050)
 #define APBC_PXA910_ASSAR       APBC_REG(0x054)
 
+/*
+ * APB Clock register offsets for MMP2
+ */
+#define APBC_MMP2_RTC           APBC_REG(0x000)
+#define APBC_MMP2_TWSI1         APBC_REG(0x004)
+#define APBC_MMP2_TWSI2         APBC_REG(0x008)
+#define APBC_MMP2_TWSI3         APBC_REG(0x00c)
+#define APBC_MMP2_TWSI4         APBC_REG(0x010)
+#define APBC_MMP2_ONEWIRE       APBC_REG(0x014)
+#define APBC_MMP2_KPC           APBC_REG(0x018)
+#define APBC_MMP2_TB_ROTARY     APBC_REG(0x01c)
+#define APBC_MMP2_SW_JTAG       APBC_REG(0x020)
+#define APBC_MMP2_TIMERS        APBC_REG(0x024)
+#define APBC_MMP2_UART1         APBC_REG(0x02c)
+#define APBC_MMP2_UART2         APBC_REG(0x030)
+#define APBC_MMP2_UART3         APBC_REG(0x034)
+#define APBC_MMP2_GPIO          APBC_REG(0x038)
+#define APBC_MMP2_PWM0          APBC_REG(0x03c)
+#define APBC_MMP2_PWM1          APBC_REG(0x040)
+#define APBC_MMP2_PWM2          APBC_REG(0x044)
+#define APBC_MMP2_PWM3          APBC_REG(0x048)
+#define APBC_MMP2_SSP0          APBC_REG(0x04c)
+#define APBC_MMP2_SSP1          APBC_REG(0x050)
+#define APBC_MMP2_SSP2          APBC_REG(0x054)
+#define APBC_MMP2_SSP3          APBC_REG(0x058)
+#define APBC_MMP2_SSP4          APBC_REG(0x05c)
+#define APBC_MMP2_SSP5          APBC_REG(0x060)
+#define APBC_MMP2_AIB           APBC_REG(0x064)
+#define APBC_MMP2_ASFAR         APBC_REG(0x068)
+#define APBC_MMP2_ASSAR         APBC_REG(0x06c)
+#define APBC_MMP2_USIM          APBC_REG(0x070)
+#define APBC_MMP2_MPMU          APBC_REG(0x074)
+#define APBC_MMP2_IPC           APBC_REG(0x078)
+#define APBC_MMP2_TWSI5         APBC_REG(0x07c)
+#define APBC_MMP2_TWSI6         APBC_REG(0x080)
+#define APBC_MMP2_TWSI_INTSTS   APBC_REG(0x084)
+#define APBC_MMP2_UART4         APBC_REG(0x088)
+#define APBC_MMP2_RIPC          APBC_REG(0x08c)
+#define APBC_MMP2_THSENS1       APBC_REG(0x090) /* Thermal Sensor */
+#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4)
+
 /* Common APB clock register bit definitions */
 #define APBC_APBCLK     (1 << 0)  /* APB Bus Clock Enable */
 #define APBC_FNCLK      (1 << 1)  /* Functional Clock Enable */